LIST OF EXPERIMENTS

1. Verification of Boolean theorems using digital logic gates 2. Design and implementation of combinational circuits using basic gates for arbitrary functions, code converters, etc. 3. Design and implementation of 4-bit binary adder / sub tractor using basic gates and MSI devices 4. Design and implementation of parity generator / checker using basic gates and MSI devices 5. Design and implementation of magnitude comparator 6. Design and implementation of application using multiplexers/ Demultiplexers 7. Design and implementation of Shift registers 8. Design and implementation of Synchronous and Asynchronous counters 9. Simulation of combinational circuits using Hardware Description Language (VHDL/ Verilog HDL software required) 10. Simulation of sequential circuits using HDL (VHDL/ Verilog HDL software required)

Digital lab manual

B.KALAIMATHI AP/ECE

AND GATE: SYMBOL: PIN DIAGRAM:

OR GATE:

Digital lab manual

B.KALAIMATHI AP/ECE

EX. NO: 1

STUDY OF BASIC DIGITAL ICs

DATE:

AIM: To study about the basic digital IC and verify their truth tables. APPARATUS REQUIRED:

S.NO 1 2

APPARATUS NAME IC Trainer Kit Patch Cords

RANGE

QUANTITY 1

14

COMPONENTS REQUIRED:

S.NO 1 2 3 4 5 6

COMPONENTS AND Gate OR Gate NAND Gate NOR Gate XOR Gate NOT Gate

RANGE IC 7408 IC 7432 IC 7400 IC 7402 IC 7486 IC 7404

QUANTITY 1 1 1 1 1 1

Digital lab manual

B.KALAIMATHI AP/ECE

NOT GATE: SYMBOL: PIN DIAGRAM:

X-OR GATE : SYMBOL : PIN DIAGRAM :

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

NOR GATE:

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the truth table of Digital logic gates and the working of various gates are studied and verified.

VIVA QUESTIONS: 1. Draw the Pin diagram for all IC. 2. Explain the working procedure. 3. Draw the symbol diagram for all IC? 4. Explain the truth table. 5. Inside an IC 7408, How many AND gates are there? 6. How do you identify the gates? 7. Define an IC? 8. Difference between AND gate and OR gate? 9. Differentiate between NAND gate and NOR gate?

Digital lab manual

B.KALAIMATHI AP/ECE

DEMORGAN S THEOREM: a) (x+y)=xy x

U4A 1 3 2 74AC04 74ALS1032A 1 2

x+y
U5A

(x+ y)

TRUTH TABLE: x 0 0 1 a) (xy)=x+y Y 0 1 0 (x+y) 1 0 0 x 1 1 0 y 1 0 1 xy 1 0 0

TRUTH TABLE: X 0 0 1 1 Y 0 1 0 1 (xy) 1 1 1 0 x 1 1 0 0 y 1 0 1 0 x+y 1 1 1 0

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO.: 2

VERFICATION OF BOOLEAN THEORM USING LOGIC GATES

DATE:

AIM: To design the following Boolean theorem using logic gates and verify the truth table. APPARATUS REQUIRED: SI.NO 1. 2. 3. APPARATUS NAME Digital trainer kit ICs Connecting wires RANGE QUANTITY

1 7432,7408,7404 Each 1 _ As required

THEOREM: DEMORGAN,S THEOREM: a) (x+y)=xy b) (xy)=x+y ABSORBTION THEOREM: a) x+xy=x b) x(x+y)=x DISTRIBUTION THEOREM: a) x+(y+z)=(x+y)+z b) x(yz)=(xy)z OTHER THEORM: a) x+x=x b) x+x=1 DUALITY THEOREM: a) A(B+C)=AB+AC b) A+(BC)=(A+B)(A+C)

Digital lab manual

B.KALAIMATHI AP/ECE

ABSORBTION THEOREM: a) x+xy=x

TRUTH TABLE: X 0 0 1 1 b) x(x+y)=x Y 0 1 0 1 x+xy 0 0 1 1 X 0 0 1 1

TRUTH TABLE: x 0 0 1 1 Y 0 1 0 1 x+y 0 1 1 1 x(x+y) 0 0 1 1 x 0 0 1 1

Digital lab manual

B.KALAIMATHI AP/ECE

PROCEDURE: 1. Make a circuit connections are as the circuit diagram. 2. Given the VCC s on all ICs. 3. Given the input and output for the following theorem connection in DTK. 4. Verify the output of the truth table for the following theorem. (i) Demorgantheorem. (ii) Distributive theorem. (iii) Absorbtion theorem (iv) Basic Boolean theorem.

Digital lab manual

B.KALAIMATHI AP/ECE

DISTRIBUTIVE THEOREM: a) x+(y+z)=(x+y)+z

TRUTH TABLE: x 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 x+(y+z) 0 1 1 1 0 1 1 1 (x+y)+z 0 1 1 1 1 1 1 1

Digital lab manual

B.KALAIMATHI AP/ECE

b) x(y+z)=(xy)z

TRUTH TABLE: x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 x(yz) 0 0 0 0 0 0 0 1 (xy)z 0 0 0 0 0 0 0 1

OTHER THEOREM: a) x+x=x b) x+x=1

Digital lab manual

B.KALAIMATHI AP/ECE

TRUTH TABLE: x 0 1 TRUTH TABLE: x 0 1 x 1 0 x+x 1 1 x 0 1 x+x 0 1

DUALITY THEOREM:

TRUTH TABLE:

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

A+BC 0 0 0 1 1 1 1 1

(A+B)(A+C) 0 0 0 1 1 1 1 1

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the boolean theorem was verified using logic gates.

VIVA QUESTIONS 1. 2. 3. 4. What is Boolean theorem? What is Boolean algebra? What is the difference between Boolean algebra and logic gates? True or False: The commutative law of Boolean addition states that A+B= AxB

5. Applying Demorgans theorem to the expression , we get 6. What is the aim for using Boolean algebra to simplify logic expressions? 7. Boolean algebra is different from ordinary algebra in which way? 8. What are the basic theorems of Boolean algebra? 9. What are demorgans law? 10. Explain the uses of Demorgans law.

Digital lab manual

B.KALAIMATHI AP/ECE

CIRCUIT DIAGRAM:

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO.: 3

DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING BASIC GATES FOR ARBITRARY FUNCTIONS, CODE CONVERTERS

DATE:

AIM: To design and implement the combinational circuits using logic gates arbitary function and code converters and verify the truth table. APPARATUS REQUIRED: SI.NO 1 2 3 APPARATUS Digital trainer kit IC 7408,7432,7411,7404,7402,7486,7404 Patch cords & connecting wires QUANTITY 1 Each1 As required

Digital lab manual

B.KALAIMATHI AP/ECE

TRURTH TABLE:

S.NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

INPUT A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

OUTPUT F= D'B'+C'(B '+A'D) 1 1 1 0 0 1 0 0 0 1 1 1 0 0 0 0

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

BINARY TO GRAY CODE CONVERTOR: LOGIC DIAGRAM:

K-Map for G3:

G3 = B 3 K-Map for G2:

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

K-Map for G1:

K-Map for G0:

TRUTH TABLE: | Binary input B3 B2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

| B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Gray code output G2 G1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

| G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

GRAY CODE TO BINARY CONVERTOR : LOGIC DIAGRAM:

K-Map for B3:

B3 = G3

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

K-Map for B2:

K-Map for B1:

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

K-Map for B0:

TRUTH TABLE: | Gray Code G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 | B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary Code B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 | B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

BCD TO EXCESS-3 CONVERTOR : LOGIC DIAGRAM:

K-Map for E3:

E3 = B3 + B2 (B0 + B1)

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

K-Map for E2:

K-Map for E1:

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

K-Map for E0:

TRUTH TABLE: | B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BCD input B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 | B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 x x x x x x Excess 3 output E2 E1 0 1 1 1 1 0 0 0 0 1 x x x x x x 1 0 0 1 1 0 0 1 1 0 x x x x x x | E0 1 0 1 0 1 0 1 0 1 0 x x x x x x

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

EXCESS-3 TO BCD CONVERTOR:

LOGIC DIAGRAM:

K-Map for B3:

B3=E3 E2 +E3 E1 E0 Digital lab manual B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

K-Map for B2:

K-Map for B1:

B1=E1

E0

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

K-Map for B0:

TRUTH TABLE: EXCESS 3 CODE E2 E1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 BINARY CODE B2 B1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0

E3 0 0 0 0 0 1 1 1 1 1

E0 1 0 1 0 1 0 1 0 1 0

B3 0 0 0 0 0 0 0 0 1 1

B0 0 1 0 1 0 1 0 1 0 1

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the design and the implementation of circuit using logic gates for arbitary function and code converters were done and the truth tables were verified. VIVA QUESTIONS: 1. Draw the circuit diagram for Boolean function 2. Draw the circuit diagram for Truth table 3. Explain the working procedure. 4. What is K-Map 5. What are the characteristics of Boolean function 6. Mention some application of Boolean function 7. Difference between SOP and POS 8. Draw the K-Map for the Boolean function 9. What is SOP 10. What is POS 11. Differentiate BCD & Excess 3 code 12. What is BCD? 13. What is the base for Binary? 14. How will you convert Binary to Gray? 15. What is Gray Code? 16. Give the conversion process of Excess 3 to BCD 17. What are the logic gates used in converting Gray code to Binary? 18. What is the need of code converters? 19. How will you design Code converters? 20. What is the difference between Positive and Negative logic? Digital lab manual B.KALAIMATHI AP/ECE

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM: 4-BIT BINARY ADDER

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO. : AIM:

DESIGN OF 4-BIT ADDER AND SUBTRACTOR

DATE :

To design and implement 4-bit adder and subtractor using IC 7483. APPARATUS REQUIRED: Sl.No. COMPONENT 1. IC 2. EX-OR GATE 3. NOT GATE 3. IC TRAINER KIT 4. PATCH CORDS

SPECIFICATION IC 7483 IC 7486 IC 7404 -

QTY. 1 1 1 1 As required

Digital lab manual

B.KALAIMATHI AP/ECE

LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR

Digital lab manual

B.KALAIMATHI AP/ECE

PROCEDURE: 1. Connections were given as per circuit diagram. 2. Logical inputs were given as per truth table 3. Observe the logical output and verify with the truth tables.

Digital lab manual

B.KALAIMATHI AP/ECE

TRUTH TABLE

Input Data A

Input Data B

Addition S4 S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 B 1 1 0 0 0 0 0

Subtraction D4 D3 D2 D1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1

A4 A3 A2 A1 B4 B3 B2 B1 C 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 1

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL RESULT: Thus the 4 bit binary adder, 4 bit binary subtractor and BCD adder were designed using logic gates and their truth table was verified. 2 2 1 5

VIVA QUESTIONS 1. Distinguish between Full Adder , 4 bit Binary adder 2. What is BCD? 3. How many pins are there in Ic 7483? 4. What is the need of Binary adder? 5. What is a Carry Look ahead Adder? 6. Is IC 7483 can be used for Adders and Subtractors? How? 7. Give the difference between a Half adder and a Parallel adder 8. How multipliers are utilized using adders 9. What is 4 bit subtraction? 10. Compare BCD adder , Binary adder

Digital lab manual

B.KALAIMATHI AP/ECE

EVEN PARITY GENERATOR CIRCUIT X Y Z

74LS86
1 2 5 3

74LS86
4 6

X 0 0 0 0 1 1 1 1

EVEN PARITY BIT(P) GENERATOR Y Z EVEN PARITY BIT(P) 0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1

PARITY GENERATOR/CHECKER (74LS180)

I6 I7 PE PO E O GND

Vcc I5 I4 I3 I2 I1 I0

74LS180

PARITY GENERATOR/CHECKER (74LS180)- PIN DETAILS

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO.:

DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER

DATE:

AIM: To design a combinational logic circuit for parity bit generator and parity bit receiver circuit APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. COMPONENT EX-OR GATE 9-bit PARITY GENERATOR/CHECKER IC TRAINER KIT PATCH CORDS SPECIFICATIO N IC 7486 IC 74180 QTY. 1 1 1 As required

PROCEDURE 1. Reduce PARITY GENERATOR/CHECKER functions using Theorems or Karnaugh-MAP method 2. Construct the Combinational Logic Circuit for reduced resulting function using corresponding Gates ICs and MSI Devices 3. For various combinations of input verify the output and tabulate the result

Digital lab manual

B.KALAIMATHI AP/ECE

DESIGN EVEN PARITY GENERATOR X MESSAGE Y Z EVEN PARITY GENERATOR

PARITY BIT (P)

EVEN PARITY CHECKER CIRCUIT

74LS86 X
1 2

Y P8

74LS86
4 5 6

74LS86 Z
9 10

EVEN PARITY BIT(P) CHECKER X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 ERROR No YES YES No YES No No YES YES No No YES No YES YES No

Digital lab manual

B.KALAIMATHI AP/ECE

EVEN PARITY GENERATOR From the truth table the expression for P is P = XYZ + XYZ + XYZ + XYZ = Z [XY+ XY] + Z [XY + XY] = Z [XY + XY] + Z [XY + XY]

PXYZ
EVEN PARITY CHECKER X MESSAGE Y Z P EVEN PARITY GENERATOR

CHECK BIT (C)

From the truth table the expression for C parity error checks can be derived as,

C xyzp xyzp xyzp xyzp xyzp xyzp xyzp xyzp

xyzp xyzp xyzp xyzp xyzp xyzp xyzp xyzp (xy xy)(zp zp) (xy xy)(zp zp)

C X Y ZP
FUNCTION TABLE

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the parity checker and parity generator circuit were designed using logic gates and their truth table was verified.

VIVA QUESTIONS 1. What is Parity? 2. Where Parity is necessary? 3. How parity is generated? 4. Where will we use parity checkers? 5. What is odd parity? 6. Give an example for an even parity? 7. How many errors can be corrected using a parity checker? 8. Why parity is used in digital circuits rather than analog circuits? 9. Can the IC 74180 work as parity generator and checker? 10. What is the disadvantage of parity?

Digital lab manual

B.KALAIMATHI AP/ECE

LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR

K MAP

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO.:

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR AIM: To design and implement (i) (ii) 2 bit magnitude comparator using basic gates. 8 bit magnitude comparator using IC 7485.

DATE:

APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. 7. COMPONENT AND GATE X-OR GATE OR GATE NOT GATE 4-BIT MAGNITUDE COMPARATOR IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7408 IC 7486 IC 7432 IC 7404 IC 7485 QTY. 2 1 1 1 2 1 As required

Digital lab manual

B.KALAIMATHI AP/ECE

TRUTH TABLE: A1 A0 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0

A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

Digital lab manual

B.KALAIMATHI AP/ECE

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0) x3 PROCEDURE: 1. Connections are given as per circuit diagram. 2. Logical inputs are given as per circuit diagram. 3. Observe the output and verify the truth table. x2 x1 x0

Digital lab manual

B.KALAIMATHI AP/ECE

PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM: 8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE: A 0000 0001 0000 0000 0001 0000 0000 0000 0001 B 0000 0000 0001 A>B 0 1 0 A=B 1 0 0 A<B 0 0 1

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the magnitude comparator circuit was designed using logic gates and their truth table was verified.

VIVA QUESTIONS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. What is the need of Comparators? What is Magnitude Comparator? How magnitude Comparators are achieved using gates? What is 8 bit Magnitude Comparator? What is the use of IC 7485? What is the pin no 8 of IC 7485? Is 7485 is a 14 pin IC? Which gate is used as a single bit Comparator? What is advantage of Ex-Nor gate? If A=1,B=0 What is the result in Magnitude comparator?

Digital lab manual

B.KALAIMATHI AP/ECE

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 0 0 1 1

S0 0 1 0 1

INPUTS Y D0 D0 S1 S0 D1 D1 S1 S0 D2 D2 S1 S0 D3 D3 S1 S0

Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO. :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER AIM: To design and implement multiplexer and demultiplexer using logic gates. APPARATUS REQUIRED: Sl.No. 1. 2. 3. 2. 3. COMPONENT 3 I/P AND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7411 IC 7432 IC 7404 QTY. 2 1 1 1 As required

DATE:

PROCEDURE: 1. Connections are given as per circuit diagram. 2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

Digital lab manual

B.KALAIMATHI AP/ECE

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 0 0 1 1

S0 0 1 0 1

Y = OUTPUT D0 D1 D2 D3

Digital lab manual

B.KALAIMATHI AP/ECE

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 0 0 1 1

S0 0 1 0 1

INPUT X D0 = X S1 S0 X D1 = X S1 S0 X D2 = X S1 S0 X D3 = X S1 S0

Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0

Digital lab manual

B.KALAIMATHI AP/ECE

LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE: INPUT S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0 OUTPUT D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the multiplexer and de-multiplexer circuit was designed using logic gates and their truth table was verified.

VIVA QUESTIONS 1. What is Mux? 2. What is the use of select lines? 3. What is a Demultiplexer? 4. Differentiate 2:1, 4:1 Multiplexer 5. What is called as Distributor? Why? 6. What is the use of IC 74150? 7. Why Mux is called as selector? 8. What is the use of IC 74154? 9. Will you design 8:1 Multiplexor using logic gates? 10. Why 74154 is used rather than logic gates?

Digital lab manual

B.KALAIMATHI AP/ECE

PIN DIAGRAM:

LOGIC DIAGRAM: SERIAL IN SERIAL OUT:

TRUTH TABLE: CLK Serial in Serial out

1 2 3 4 5 6 7 Digital lab manual

1 0 0 1 X X X

0 0 0 1 0 0 1 B.KALAIMATHI AP/ECE

EX NO. :

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER AIM: To design and implement (i) Serial in serial out (ii) Serial in parallel out (iii) Parallel in serial out (iv) Parallel in parallel out APPARATUS REQUIRED: S No. 1. 2. 3. 4. COMPONENT D FLIP FLOP OR GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7474 IC 7432 QTY. 2 1 1 As required

DATE:

PROCEDURE: 1. Connections are given as per circuit diagram. 2. Logical inputs are given as per circuit diagram. 3. Observe the output and verify the truth table.

Digital lab manual

B.KALAIMATHI AP/ECE

LOGIC DIAGRAM: SERIAL IN PARALLEL OUT:

TRUTH TABLE: OUTPUT CLK 1 2 3 4 DATA 1 0 0 1 QA 1 0 0 1 QB 0 1 0 0 QC 0 0 1 0 QD 0 0 1 1

LOGIC DIAGRAM: PARALLEL IN SERIAL OUT:

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

TRUTH TABLE: CLK 0 1 2 3 Q3 1 0 0 0 Q2 0 0 0 0 Q1 0 0 0 0 Q0 1 0 0 0 O/P 1 0 0 1

LOGIC DIAGRAM: PARALLEL IN PARALLEL OUT:

TRUTH TABLE: DATA INPUT CLK 1 2 DA 1 1 DB 0 0 DC 0 1 DD 1 0 QA 1 1 OUTPUT QB 0 0 QC 0 1 QD 1 0

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA RESULT: TOTAL 2 2 1 5

Thus the various shift registers were designed successfully using flip-flops and their truth tables were verified successfully.

VIVA QUESTIONS 1. What is a Register? 2. What is a Shift Register? 3. What is the basic device used in a Shift register? 4. What is the of Shift registers? 5. Give one application of shift register 6. What is SISO shift register? What is the IC used for it? 7. What is a Ring Counter? 8. What is a Bi-directional Shift register? 9. What is a PISO shift register? 10. Which is faster? A PISO,PIPO

Digital lab manual

B.KALAIMATHI AP/ECE

4-BIT ASYNCHRONOUS DOWN COUNTER:

TRUTH TABLE 4-BIT ASYNCHRONOUS DOWN COUNTER:

CLK INPUT Q3 Q2 Q1 Q0 (1) 1 1 1 1 (1) 1 1 1 0 (1) 1 1 0 1 (1) 1 1 0 0 (1) 1 0 1 1 (1) 1 0 1 0 (1) 1 0 0 1 (1) 1 0 0 0 (1) 0 1 1 1 (1) 0 1 1 0 (1) 0 1 0 1 (1) 0 1 0 0 (1) 0 0 1 1 (1) 0 0 1 0 (1) 0 0 0 1 (1) 0 0 0 0 (1)-positive edge input

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO. :

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND ASYNCHRONOUS COUNTERS

DATE:

AIM: To design and implement 4 bit synchronous and asynchronous counter using logic gates. APPARATUS REQUIRED: Sl.No. 1. 2. 3. 6. 7. COMPONENT JK FLIP FLOP NAND GATE AND GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7476 IC 7400 IC 7408 QTY. 1 1 1 1 as required

PROCEDURE COUNTERS 1. Construct the circuit as in circuit diagram. 2. Output of the mono pulse generator is given to clk input of Flip-Flop and set the pulse generator to manual mode. 3. To verify the count sequence, apply manually not less then 7/8 pulses and verify the truth table.

Digital lab manual

B.KALAIMATHI AP/ECE

DESIGN PROCEDURE FOR COUNTERS 1. COUNTER WITH NON-BINARY SEQUENCE STEP 1 (STATE DIAGRAM)

STEP 2 EXCITATION TABLE Note: From this excitation table the logic circuit is designed using karnaugh map Present State Next State Flip-flop excitation A B C A B C Ja Ka Jb Kb Jc 0 0 0 0 0 1 0 X 0 X 1 0 0 1 0 1 0 0 X 1 X X 0 1 0 0 1 1 1 X X 1 0 1 0 0 1 0 1 X 0 0 X 1 1 0 1 1 1 0 X 0 1 X X 1 1 0 0 0 0 X 1 X 1 0 STEP 3 CIRCUIT DIAGRAM
A B C

Kc X 1 X X 1 X

4 1 16

J CLK K

15

9 6

J CLK K

11

4 1 16

J CLK K

15

14

12

QB 7476

14

7476 CLK logic 1

7476

Digital lab manual

B.KALAIMATHI AP/ECE

4-BIT SYNCHRONOUS UP COUNTER:

TRUTH TABLE 4-BIT SYNCHRONOUS UP COUNTER: CLK INPUT Q3 Q2 Q1 Q0 (1) 0 0 0 0 (1) 0 0 0 1 (1) 0 0 1 0 (1) 0 0 1 1 (1) 0 1 0 0 (1) 0 1 0 1 (1) 0 1 1 0 (1) 0 1 1 1 (1) 1 0 0 0 (1) 1 0 0 1 (1) 1 0 1 0 (1) 1 0 1 1 (1) 1 1 0 0 (1) 1 1 0 1 (1) 1 1 1 0 (1) 1 1 1 1 (1)-positive edge input

Digital lab manual

B.KALAIMATHI AP/ECE

(MOD-10) SYNCHRONOUS UP COUNTER:

TRUTH TABLE - (MOD-10) SYNCHRONOUS UP COUNTER:

CLK INPUT Q3 Q2 Q1 Q0 (1) 0 0 0 0 (1) 0 0 0 1 (1) 0 0 1 0 (1) 0 0 1 1 (1) 0 1 0 0 (1) 0 1 0 1 (1) 0 1 1 0 (1) 0 1 1 1 (1) 1 0 0 0 (1) 1 0 0 1 (1)-positive edge input

Digital lab manual

B.KALAIMATHI AP/ECE

DEPT OF ECE PERFORMANCE OBSERVATION VIVA RESULT: TOTAL 2 2 1 5

Thus, the 4-bit Synchronous and Asynchronous counters were designed, implemented using logic gates.

VIVA QUESTIONS 1. What is counter? 2. Why do we need counters? How are counters made? 3. What is synchronous counter? 4. What is the difference between synchronous and asynchronous counter? 5. What advantages do synchronous counters have over asynchronous counter? 6. The combinational element of a counter can be made with 7. What are the applications of synchronous counter? 8. Which flipflop is used to made synchronous counter? 9. What is flipflop? 10. What are the different types of synchronous counter? 11. What is a Counter? 12. What is Up/Down counter? 13. What are the applications of Flipflops? 14. What is the use of a Clock signal? 15. What are the types of Triggering methods in F/Fs 16. Compare Synchronous, Asynchronous counters? 17. What is State diagram? 18. What is the disadvantage of Synchronous counter? 19. How will you design a synchronous counter? 20. What are the types of Flipflops?

Digital lab manual

B.KALAIMATHI AP/ECE

Digital lab manual

B.KALAIMATHI AP/ECE

EX NO. :

SIMULATION OF COMBINATIONAL CIRCUIT USING HDL

DATE:

AIM: To design and simulate (i) Adder and Subtractor (ii) Multiplexer and De-multiplexer TOOLS REQUIRED XILINX Software Modelsim simulator PROCEDURE Write and draw the Digital logic system. Write the Verilog HDL code for above system. Open project navigator Select File New project Give the file name and press next Give the entity name and select Verilog HDL module and press next Give the inputs and outputs and specify input or output or in-out and select next Then give finish and the entity and the architecture details appear by itself Enter the Verilog HDL code in after architecture. Check the syntax and simulate the above Verilog HDL code (using ModelSim or Xilinx) and verify the output waveform as obtained. Verify the graph with the truth table PROGRAM: HALF ADDER module half_adder(in_x, in_y, out_sum, out_carry); input in_x; input in_y; output out_sum; output out_carry; xor (out_sum, in_x, in_y); and (out_carry, in_x, in_y); end module;

Digital lab manual

B.KALAIMATHI AP/ECE

FULL ADDER module full_adder(x, y, z, sum, carry); input x; input y; output sum; output carry; wire a, b, c; xor (sum, x, y, z); and (a, x, y); and (b, y, z); and (c, z, x); or (carry, a, b, c); end module;

HALF SUBTRACTOR module half_subtractor (x, y, diff, borrow); input x; input y; output diff; output borrow; wire ybar; not (ybar, y); xor (diff, x, y); and (borrow, x, ybar); end module;

Digital lab manual

B.KALAIMATHI AP/ECE

FULL SUBRACTOR module fullsub(a, b, c, borrow, dif); input a; input b; input c; output borrow; output dif; wire d,e,f; xor(dif,a,b,c); and(d,~a,b); and(e,b,c); and(f,~a,c); or(borrow,d,e,f); endmodule MULTIPLEXER module mux_4 to 1 ( y, I1, I2, I3, I4, S0, S1); input I1, I2, I3, I4, S0, S1; output y; wire S1bar, S0bar, a, b, c, d; not (S1bar, S1); not (S0bar, S0); and (a, S1bar, S0bar, I1); and (b, S1bar, S0, I2); and (c, S1, S0bar, I3); and (d, S1, S0, I4); or (y, a, b, c, d); end module;

Digital lab manual

B.KALAIMATHI AP/ECE

DE-MULTIPLEXER module mux_4 to 1 ( Y1, Y2, Y3, Y4, I, S0, S1); input I, S0, S1; output Y1, Y2, Y3, Y4; wire S1bar, S0bar; not (S1bar, S1); not (S0bar, S0); and (Y1, S1bar, S0bar, I); and (Y2, S1bar, S0, I); and (Y3, S1, S0bar, I); and (Y4, S1, S0, I); or (y, a, b, c, d); end module;

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the simulation of adders, subtractors, multiplexer and demultiplexer using XILINX software were done and simulated their circuit using modelsim simulator.

Digital lab manual

B.KALAIMATHI AP/ECE

EXNO. :

SIMULATION OF SEQUENTIAL CIRCUITS USING HDL

DATE:

AIM: To design and simulate (i) Ripple counter (ii) Shift registers TOOLS REQUIRED XILINX Software Modelsim simulator PROCEDURE Write and draw the Digital logic system. Write the Verilog HDL code for above system. Open project navigator Select File New project Give the file name and press next Give the entity name and select Verilog HDL module and press next Give the inputs and outputs and specify input or output or in-out and select next Then give finish and the entity and the architecture details appear by itself Enter the Verilog HDL code in after architecture. Check the syntax and simulate the above Verilog HDL code (using ModelSim or Xilinx) and verify the output waveform as obtained. Verify the graph with the truth table

Digital lab manual

B.KALAIMATHI AP/ECE

PROGRAM RIPPLE COUNTER module counter (count, load, in, clk, clr, a, c); input count, load, clk, clr; input [3:0] in; output c; output [3:0] a; reg [3:0] a; assign c = count & ~load & (a = = 4b1111); always @ (posedge CLK or negedge clr) if (~clr) A = 4b0000; else if (load) a = in; else if (count) a = a + 1b1; else a = a; end module;

SISO SHIFT REGISTER module shift (clk, SE, SI, SO); input SE, SI; output SO; reg [3:0] temp; always @ (posedge clk) begin if (SE) begin temp = temp << 1; temp[0] = SI; end; begin assign SO = temp [3]; end module;

Digital lab manual

B.KALAIMATHI AP/ECE

SIPO SHIFT REGISTER module shift (clk, SE, SI, PO); input SE, SI; output PO [3:0]; reg [3:0] temp; always @ (posedge clk) begin if (SE) begin temp = {temp [2:0], SI}; end; begin assign PO = temp; end module;

DEPT OF ECE PERFORMANCE OBSERVATION VIVA TOTAL 2 2 1 5

RESULT: Thus the simulation of ripple counter, shift registers using XILINX software were done and simulated their circuit using modelsim simulator.

Digital lab manual

B.KALAIMATHI AP/ECE