UM180FDKMFC_C

UMC 0.18um Mixed Mode/RF CMOS 1.8V / 3.3V 1P6M Processes Release Note

Copyright UMC, 2008 All information contained herein is subject to change without prior notice. No liability shall be incurred from its use or application.

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Revision History
Revision 2.0 2.1 Date 2002/11/29 2003/05/26 Description
Original Release 1. 2. 3. 4. 5. 6. 7. 8. 9. DFII Layer change (GT-RPT-000601-001 -> GT-RPT-030225-001) Add auLvs Cellview Add ivpcell Cellview L_SLCR20K_RF PCell terminal bug fix Modify Dynamic Link netlist for MM devices Modify pin names "SUB" -> "B" for Assura Modify MOS CAP pin names to "D G S B" MIMCAPM_RF CSYMBOL modify for LPE issue Add this layer for RFMOS source area

2.2 2.3

2003/06/18 2003/11/26

Fix NCAP_MM and PCAP_MM layout 1. 2. 3. 4. 5. 6. 7. 8. Add ADS, Eldo and HspiceS view on pcapacitor and presistor Fix auLvs CDF settings of pcapacitor and presistor MM MOS Callback supports variable input Modify MM MOS terminal mapping for DC current annotation bug Add IP tag information Add Metal Pin Layer Fixed Component description (Page 56) L_SLCR20K_RF part Add in section 6.1

2.4 2.5P1

2004/03/17 2004/08/10

MIMCAPS_MM bottom plate tap default value modified 1. Fix CONT position for all MM MOS/MOSCAP for dog bone shape and the gate width equals to 0.01um multiplied by odd numbers Add SEPGND layer 99(0) Change VTXXX rule Add hspice view on presistor and pcapacitor MIMCAPM_RF pcell update to meet TLR change MIMCAPM_RF, multiplier factor RNHR_RF, RNNPO_RF and RNPPO_RF support

2. 3. 4. 5.

6. 2.6P1 2005/03/17

Technology file and display.drf aligned to new official release

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C01_PB 2006/12/25
1.

Revision 0.18um CMOS Mixed Mode/RF FDK from

GT-DBT-021202-003 V2.6P1 to G-9FD-MIXED_MODE/RFCMOS18-1.8V/ 3.3V-1P6M-MMC/UM180FDKMFC-FDK VC01_PB.

2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

Generator one signal package and include Model Files. Update Interconnect Capacitance. Update Calibre DRC/LVS/XRC command files. Update Assura DRC/LVS/LPE command files. Update technology file. Modify MIMCAPM_RF callback for fix bug. Update EDR. Update Spice Model Update TLR Modify RM6 width minimum value to 1.2u for fix typo in this document. Modify MIMCAPS_MM range to 1.28u ~ 100u. Removed Devices: RSND_MM RSPD_MM RSNWELL_MM RNND_MM RNPD_MM RM1_MM RM2_MM RM3_MM RM4_MM RM5_MM RM6_MM Update Assura DRC & LVS command files. Update Calibre DRC & LVS command files. Update EDR. Update TLR. Updata Mask Tooling. Update official layer mapping table. Update Spice Model. Update technology file. Revised DIODE (DION_MM, DIOP_MM) for range scalable. Added hspiceD view. Fixed MIMCAPM_RF does not support m= in auCdl view. Fixed bug of MIMCAPS_MM multiplier parameter in Spectre view.

C02_PB

2008/12/15

1.

2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.

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14. Revised G-01 DSM number
G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM-8C to G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM

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Table of Contents
GENERAL DESCRIPTION ................................................................................................................... 6 FDK CHECKLISTS ............................................................................................................................... 7 KNOWN PROBLEMS AND SOLUTIONS ........................................................................................... 13

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General Description
In the front-end, we build fundamental components of UMC processes in the Cadence Composer library and simulate the circuit using Cadence Analog Design Environment. The back-end is done with the Cadence's Virtuoso custom layout editor by using parameterized cells (PCell), which includes a schematic driven layout to provide an automatic and complete design flow. Through the procedure, the designer can reduce the risk of errors.

This design flow provides excellent integration and links between process technology, device modeling, circuit front-end design and circuit back-end design. The implementation of the design flow helps the circuit designers much more efficiently designing their products. For the detailed information about FDK, please contact the customer engineers near you.

This version of FDK has passed the quality assurance checking, and the design verification has been made. It follows the information below.

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FDK Checklists
Table 1. Foundry Process Documents DSM List Classification Design Support Manual Electrical Design Rule Topological Layout Rule Interconnect Capacitance SPICE Modeling Mask Tooling DRC Rule Deck LVS Rule Deck LPE Rule Deck Official Layer Mapping Table Spec. No.
G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM

Version

Date
2008/12/10 2008/10/30 2007/12/07 2006/05/10 2006/05/30 2008/11/20 2007/03/15 2008/09/25 2008/05/02 2008/12/01 2008/12/09 2006/07/21 2006/08/24 2008/01/29

2.1_P1 2.1_P1 G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR 2.10_P1 G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP 1.2_P1 G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TRI_WELL/MMC-SPICE-8C 1.4_P2 G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TWIN_WELL/MMC-SPICE-8C 1.6_P2 G-06-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-MASKTOOL-8C 2.6_P1 G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-DRC 2.10_P3 G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/ASSURA-DRC 2.10_P1 G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-LVS 2.1_P2 G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/ASSURA-LVS 2.1_P2 G-DF-MIXED_MODE/RFCMOS18-1P6M-MMC/TOP_METAL20.6K/XRC-LPE 1.2_P1 G-DF-MIXED_MODE/RFCMOS18-1P6M-MMC/TOP_METAL20.6K/ASSURA-LPE 1.2_P1
G-DF-GENERATION18-VIRTUOSO-TF

2.10_P1

NOTE: 1. The DRC rule decks included in this Design Kit are not covering all the Topological Layout Rules. Please consult your Account Manager to obtain the complete set and the latest versions of DRC rule decks before the tape-out phase. 2. The model files and rule decks included in this release Design Kit were available at the time of this revision. The user needs to obtain the latest model files and rule decks through your Account Manager.

Table 2. EDA Tools Supported and Verified for Use with this FDK Classification Schematic Entry Simulation Interface Simulation Tool Layout Editor DRC Tool LVS Tool Parasitic RC Extractor EDA Tools Cadence Composer Cadence Analog Design Environment Cadence Spectre Synopsys Hspice Cadence Virtuoso Mentor Calibre Cadence Assura Mentor Calibre Cadence Assura Mentor XRC Cadence Assura Version 5.1.41_ISR 5.1.41_ISR 5.1.41_ISR 2008.03 5.1.41_ISR 2007.4-44.36 3.2.0 2007.4-44.36 3.2.0 2007.4-44.36 3.2.0

NOTE: This Design Kit did not verify the other EDA tools not mentioned above.

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Table 3. Component List Spectre Netlist Hspice Netlist

Device Name

Symbol View

Spectre Sim.

* SDL Check

Layout View

Device Type

Hspice Sim.

DRC Check V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

Model Type

CDL Netlist

MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS MOS BJT BJT

N_18_MM N_33_MM P_18_MM P_33_MM N_BPW_18_MM N_BPW_33_MM N_LV_18_MM N_LV_33_MM P_LV_18_MM P_LV_33_MM N_ZERO_18_MM N_ZERO_33_MM N_L18W500_18_RF N_L34W500_33_RF N_PO7W500_18_RF N_PO7W500_33_RF P_L18W500_18_RF P_L34W500_33_RF P_PO7W500_18_RF P_PO7W500_33_RF PNP_V50X50_MM

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 2 2 2 3 3 3 3 3 3 2

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

*C *C *C *C *C *C *C *C *C *C *C *C *S *S *S *S *S *S *S *S *C *C *C *C *C *S *S *S *S *S *S *S

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

PNP_V100X100_MM Diode DION_MM Diode DIOP_MM Diode DIONW_MM RES RES RES RES RES RES CAP RNHR1000_MM RNNPO_MM RNPPO_MM RNNPO_RF RNPPO_RF RNHR_RF VARDIOP_RF

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LVS Check V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

Terminals

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CAP CAP CAP CAP CAP IND PAD VARMIS_18_RF MIMCAPM_RF MIMCAPS_MM NCAP_MM PCAP_MM L_SLCR20K_RF PAD_RF 3 3 2 3 3 3 2 V V V V V V V *S *S *S *S *S *S *S V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V

NOTE: (*) C represents compact model; S represents sub-circuit type; SDL represents schematic driven layout.

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Table 4. FDK Component Table UMC_DSM Device 1.8V PMOS CELL name P_18_MM Cell view Device model file No of model No of symbol Model range Name of terminals file terminals terminal 0.24u<=W<=100u 4 D, G, S, B 4 0.18u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 4 D, G, S, B 4 0.18u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 4 D, G, S, B 4 0.18u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 4 D, G, S, B 4 0.24u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 4 D, G, S, B 4 0.24u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 4 D, G, S, B 4 0.3u<=L<=50u 1<=Nf<=10000 W=5.0u 4 D, G, S, B 4 0.2u<=L<=0.5u Nf=7 W=5.0u 4 D, G, S, B 4 0.2u<=L<=0.5u Nf=7 W=5.0u 4 D, G, S, B 4 0.34u<=L<=0.8u Nf=7 W=5.0u 4 D, G, S, B 4 0.34u<=L<=0.8u Nf=7 W=5.0u 4 D, G, S, B 4 L=0.18u 5<=Nf<=21 W=5.0u 4 D, G, S, B 4 L=0.18u 5<=Nf<=21 W=5.0u 4 D, G, S, B 4 L=0.34u 5<=Nf<=21 W=5.0u 4 D, G, S, B 4 L=0.34u 5<=Nf<=21 0.24u<=W<=100u 4 D, G, S, B 4 0.34u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 4 D, G, S, B 4 0.34u<=L<=50u 1<=Nf<=10000 0.8u<=W<=100u 4 D, G, S, B 4 0.5u<=L<=50u 1<=Nf<=10000

1.8V NMOS 1.8V TWELL NMOS 1.8V Low Vt PMOS 1.8V Low Vt NMOS 1.8V Zero Vt NMOS 1.8V RF NMOS
(Length scalable)

N_18_MM

N_BPW_18_MM

P_LV_18_MM

N_LV_18_MM

N_ZERO_18_MM

N_PO7W500_18_RF

1.8V RF PMOS
(Length scalable)

P_PO7W500_18_RF

3.3V RF NMOS
(Length scalable)

N_PO7W500_33_RF

3.3V RF PMOS
(Length scalable)

P_PO7W500_33_RF

1.8V RF NMOS
(Nf scalable)

N_L18W500_18_RF

1.8V RF PMOS
(Nf scalable)

P_L18W500_18_RF

3.3V RF NMOS
(Nf scalable)

N_L34W500_33_RF

3.3V RF PMOS
(Nf scalable)

P_L34W500_33_RF

3.3V PMOS

P_33_MM

3.3V NMOS 3.3V Low Vt NMOS

N_33_MM

N_LV_33_MM

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3.3V Low Vt PMOS 3.3V Zero Vt NMOS 3.3V TWELL NMOS N+/Pwell Diode P+/Nwell Diode Nwell/Psub Diode P+/Nwell/PSUB PNP Bipolar Tr. (5*5) P+/Nwell/PSUB PNP Bipolar Tr. (10*10) Non-Salicide P+ Poly Resistor Non-Salicide N+ Poly Resistor HR Poly Resistor HR Poly Resistor N+ Poly Resistor P+ Poly Resistor NMOS Capacitor PMOS Capacitor MIM Capacitor 0.8u<=W<=100u 0.5u<=L<=50u 1<=Nf<=10000 0.8u<=W<=100u 0.5u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 0.34u<=L<=50u 1<=Nf<=10000 0.94u<=W<=160u 0.94u<=L<=200u 0.94u<=W<=160u 0.94u<=L<=200u Emitter W=1080u Emitter L=90u Emitter W=5u Emitter L=5u Emitter W=10u Emitter L=10u 0.18u<=W<=20u 0.6u<=L<=1000u 0.18u<=W<=20u 0.6u<=L<=1000u 0.18u<=W<=20u 1.0u<=L<=1000u 2u<=W<=10u 2u<=L<=100u 1<=L/W<=10 2u<=W<=10u 2u<=L<=100u 1<=L/W<=10 2u<=W<=10u 2u<=L<=100u 1<=L/W<=10 0.24u<=W<=100u 0.18u<=L<=50u 1<=Nf<=10000 0.24u<=W<=100u 0.18u<=L<=50u 1<=Nf<=10000 1.28u<=W<=100u 1.28u<=L<=100u Single Retangle: NX=1 NY=1 10u<=W<=70u 10u<=L<=70u 1<=L/W<=6 Multi Retangle: 1<=NX<=7
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P_LV_33_MM

D, G, S, B

N_ZERO_33_MM

D, G, S, B

N_BPW_33_MM DION_MM DIOP_MM DIONW_MM PNP_V50X50_MM

4 2 2 2 3

D, G, S, B PLUS, MINUS PLUS, MINUS PLUS, MINUS C, B, E

4 2 2 2 3

PNP_V100X100_MM

C, B, E

RNPPO_MM

PLUS, MINUS, B

RNNPO_MM RNHR1000_MM RNHR_RF

3 3 3

PLUS, MINUS, B PLUS, MINUS, B PLUS, MINUS, B

3 3 3

RNNPO_RF

PLUS, MINUS, B

RNPPO_RF

PLUS, MINUS, B

NCAP_MM

D, G, B

PCAP_MM MIMCAPS_MM

3 2

D, G, B PLUS, MINUS

4 2

RF MIM capacitor

MIMCAPM_RF

PLUS, MINUS, B

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1<=NY<=7 W=10u L=10u 1<=NY/NX<=6 1.8V MIS Varactor P+/Nwell Junction Varactor Spiral Inductor RF Pad VARMIS_18_RF VARDIOP_RF 3 3 PLUS, MINUS, B PLUS, MINUS, B 3 3 24<=Nf<=120 30<=Nf<=120 126u<=D<=238u 6.0u<=W<=20u 1.5<=N<=5.5 1<=index<=5

L_SLCR20K_RF PAD_RF

3 2

PLUS, MINUS, B PLUS, PSUB

3 2

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Known Problems and Solutions

DIODE (DION_MM, DIOP_MM) For the backward compatibility, the diode PCells keep the fixed layout size provided in previous FDK package as the default (W = 80um, L=100um). Design variable does not support MOS dog-bone status. We do not recommend user use design variable when MOS width is less than 0.48um (dog-bone status). This function is not support in this package. Slot rule violation of MOSCAP (NCAP_MM & PCAP_MM) When the size of ME1 of MOSCAP is larger than 30um is 20um, it will violate the DRC rule of metal slot (6.1A_M1). Designer should follow the slot rule and add slot manually. The width of connection line which on L_SLCR20K_RF terminals (PLUS & MINUS). As the width of connection lines on L_SLCR20K_RF are not coincident the width of terminals, the DRC rule, 4.31H, will be violated. For avoid the DRC violation, user should connect to the terminals with ME6, and the layer width must be coincident with the width of terminals. Warning messages about layers does not defined in DFII when Assura LVS running. When running Assura LVS flow, it shows warning message about layer (VSTRES drawing) & (IRAM drawing) are not defined in DFII. These alerts will not impact the LVS execution, and user can ignore it. The resistance (r), capacitance (c) & inductance (l) on Calibre view. When building calibre view, the value of r, c & l will be set to default value. These parameters are for reference only and will not affect the post simulation.

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