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Test evaluation - Fault coverage
An important problem in testing is test evaluation, which
refers to determining the effectiveness, or quality, of the
test.
The effectiveness of a test set is quantifiable.
It is the percentage of the faults detected by a test and is
known as the Fault coverage
Khosrow Ghadiri VLSI Design for Testability
EE Dept. SJSU
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known as the Fault coverage.
A more realistic expression is:
Where detectable fault =all faults untestable faults.
Fault detected
Fault coverage
Total #of faults
=
Fault detected
Fault coverage
Detectablefaults
=
PRTPG: an LFST
Reliability and testing
Khosrow Ghadiri VLSI Design for Testability
EE Dept. SJSU
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Q
Q D
Q
Q D
Q
Q D
1
2 3
Test Application
Off-chip and on-chip testing
Off chip: requires expensive testers
On chip: uses the embedded testing technique
On chip may also be done during normal operation of the
circuit: on-line testing
Khosrow Ghadiri VLSI Design for Testability
EE Dept. SJSU
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circuit: on line testing
On Line Testing
On line testing
Circuit Under
Encoded
Output
N
N
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EE Dept. SJSU
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Test
Checker
N
P
On- vs Off-Chip Testing
On- vs off-chip testing
HighBandwidth
LowBandwidth
HighBandwidth
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EE Dept. SJSU
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Analog
Logic
RAM
Embeddedtest External test
Source/
sink
Logic
RAM
Analog
Embeddedtest External test
5
Test Economics
High quality requires a large investment in time and
money.
The life cycle of a product is shorter than its design cycle
Time to market need thus to be shorten
Testing is necessary for reliability and for improving yield
Khosrow Ghadiri VLSI Design for Testability
EE Dept. SJSU
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Testing is necessary for reliability and for improving yield
Disciplined design to facilitate testing is know as design
for test (DFT)
Time to Market
Revenue loss due to a delay in arrival of the product to
market.
T A
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EE Dept. SJSU
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Timein Months
R
e
v
e
n
u
e
s
AT
Timeto
Market
Loss of
Revenues
Revenue peak
Yield
The yield Y of IC manufacturing is defined as:
It is hard to find exact value of Y because:
Lack of data for a part once they are sold
#
# #
G
Y
G B
=
+
Khosrow Ghadiri VLSI Design for Testability
EE Dept. SJSU
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Lack of data for a part once they are sold
Lack of possibility to test all chip
Test may pass as good, bad chip (miss the fault not
modeled)
Many factor effect the yield:
Die area of wafer
Process maturity
# of process steps
Yield mathematical models
Murphy yield model:
where A is the area, D is defect density.
The defect level is the fraction of the bad chip that passed
1
AD
e
Y
AD
=
L A
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EE Dept. SJSU
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the test. Measured in defect per million (DPM) thus a defect
level of 0.1% is equivalent to 1000 DPM.
Williams model:
Where t is the fault coverage of functional test used.
For small DL of less than 1000 DPM
where TT=1-T is the testing transparency
( ) 1 1 DL Y T =
( ln ) DL TT Y =
Yield and Defect Level
Yield and Defect Level.
Defect Level
1
% DPM
10000
5000
Y=50% Y=90%
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EE Dept. SJSU
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0.1
0.01
0.001
TT%
1000
500
100
50
10
.01 0.1 1 10
99.99 99.9 99 90 C%
Yield and Fault Coverage
Yield and Fault Coverage.
20
25
30
L
e
v
e
l
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EE Dept. SJSU
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0
5
10
15
0 10 20 30 40 50 60 70 80 90 100
Fault Coverage
D
e
f
e
c
t
L