I have some understanding of IC design flow (digital IC section): "Ic design process and the use of tools introduced

" I think the IC design process in accordance with the different features and applications can be roughly divided into three parts, the figures were IC, analog IC and FPGA. Both the similarities between the three different points there. During the design, the use of software tools have the same and different. Digital Asic design process using the tool front-end to back-end general-purpose digital Asic (top to bottom) at the time of verification algorithms generally use C language or verilog modeling algorithms to the system, using the behavioral description of the algorithm functions correctly or not be simulated . Generally more common method is to use the C language in the Matlab software environment for algorithm verification. After the algorithm validation is complete, the need for the work that will be converted into the corresponding algorithm behavioral or register transfer level description of the function and its simulation. In the tool can be used at this stage there are many commonly used Active-HDL, Mentor Modelsim series of software and QuestaSim series (the former using three nuclear simulation, which uses one core, so that the latter can be under a different locale Description mixed simulation). After completion of work is required for the simulation according to the standard foundry process library digital unit provided on the front of the representation of a function to obtain the integrated code to obtain a mapping of the actual circuit by the gate circuit composed of a standard cell library corresponding to the code. In the integrated process, to be developed according to the design specifications of various constraints to enable integrated circuit map to get to meet the design requirements, but also pay attention to the various information given comprehensive report constraint violations, and use this information to modify the code or algorithms. Tools used in the integrated process is the most important Synopsys DC and PC. Library-related technology and layout done after a comprehensive, practical use of integrated circuits resulting mapping, timing constraints and foundry can provide automatic placement and routing operation done. At this point the commonly used software from Synopsys and Cadence's ASTRO Se tool. After completion of automatic placement and routing can extract parasitic parameters based on information generated layout files for parasitic interconnect delay and post-simulation contains. Commonly used parasitic extraction tools AVANTI of STAR-RC and Cadence's DRECULA or Diva, both need to layout and technology library files automatically get software to import layout parasitic extraction performed. Cadence software can also import the layout to be repaired on the territory are not satisfied with the automatic placement and routing to get. After the end of the parasitic extraction of parasitic parameters obtained with the automatic placement and routing information obtained netlist import PT timing parameter contains parasitic extraction, and then use the extracted netlist timing parameters at the bottom mark after the anti-simulation, observation Timing simulation meets the design specifications. If you meet the basic design is complete, does not meet the needs iterative modification. The timing needs to have an anti-standard file software is PT, and the timing of the anti-labeled anti-standard file back netlist after synthesis and postsimulation software more, such as Modelsim and Nclaunch (NC mainly for large-scale systems, and Modelsim mainly is designed for small, because the former is a workstation which work platform is PC). Full custom

digital Asic or mixed signal ASIC (from top to bottom, bottom to top in conjunction with) when you need to make full custom digital chips , the traditional top-down design process is not completely worked. The biggest difference is that in order to achieve full-custom chip smaller size and power consumption, higher integration may not use a standard digital cell library provided by the manufacturer but through communication with foundry design to meet their own needs technology library. For example, the design is the use of full-custom design approach of Xilinx FPGA chip. For full custom designs, but also requires the use of algorithm validation, functional description and simulation, synthesis, parasitic extraction and post-simulation process, but relatively universal Asic design, at the time after doing the simulation can be used full-custom analog After the simulation method for simulation without the need for anti-target timing process, because the standard library of digital technology in the design of full custom Asic is not used when the foundry provided but according to the design needs of digital technology library of their own design. So for full custom Asic design is concerned, it's the need to adopt a standard analog simulation library foundry provided after due to the use of antistandard timing and simulation using simulation methods to get the final layout corresponding information, and therefore may be time-consuming than the design Asic more general type. Full-custom design flow using software, the same algorithm simulation and functional verification software with general-purpose use. However, this step is not the same comprehensive, and full custom designs for general use Cadence software designed more as a full-custom design is more like analog circuit design. In this step prior to first comprehensive design specification based on timing and power allocation for each module, and the best can be refined to each gate-level circuits. Then to build the required cell library design designer needs upon request. Because full custom integrated ic This step is more like the use of the designer's own definition of library building blocks of the process control factors and human experience is more important, where you can make a good layout Dachu higher circuit efficiency. Here you can first use the cadence of the Virtuoso layout and schematic entry tools to build on the basis of the establishment of a single tube in accordance with the requirements of the basic cell library design specifications, and then based on proven algorithms and functional description, using the basic cell library constructed to Circuit layout structure to give the entire chip, each chip last signal according to a relation to the operation of the circuit wiring. The above operations can be done in Virtuoso Cadence's IC 5.1 integrated design environment, when the full-custom layout Asic after the completion of the basic layout on the set, and then based on the basic cell library based on the territory of the corresponding full-chip circuit to build full corresponding full-chip circuit chip layout. At this point you can use Cadence's Diva or Drucla tools DRC, ERC, LVS checking, and parameter extraction can be carried out according to the layout using the above tools. Then extract the parameters obtained with the full-chip netlist time or fullchip circuit structures obtained after full-chip simulation. If you do not want to use the Cadence simulation or when the system is not too large simulation can be used Hsim simulation. Hsim layout when using the need to extract parasitics and full-chip circuit based on the basic cell library netlist. (There are no details of where the need for specific elaborate back down). Note that code style during Universal Digital Asic design, because the code style a direct impact on the effect of integrated software, code-style specification can get higher performance chip circuitry. Also, note that when writing code to make use of the code and can be integrated to avoid glitches and metastability circuit description systematic approach appear. Making full custom digital cell

libraries must pay attention to the establishment of Asic design time, when you create a logical addition to meeting the basic functions but also pay attention to the relationship between the ratio of width to length units constructed between power consumption and delay, it is best to build Based on the circuit structure of a variety of different expressions such as verilog and schematics. This facilitates further behind the analysis and simulation. In addition, full-custom digital IC design digital circuits will often be analyzed as an analog circuit power consumption and delay, so you can use the analog-digital hybrid approach to the design of the circuit simulation based on self-built cell library, which can be relatively full circuit simulation significantly improve simulation speed, relatively full circuit of digital simulation to be more accurate delay information. But for power simulation or simulation can only use the full circuit. The most important general point is that the layout of the layout of the digital IC can be automated using software, and is more of a full custom layout experienced designers rely achieved. These are part of the digital IC, a little personal opinion and everyone together, to welcome you to point out errors and shortcomings of the place! !