DDR System Design Considerations

Integrated Technology Group Micron

DDR Overview

SSTL2 Signal Levels

Driver

Receiver

December, 00

SSTL2 Double Ended Termination

VTTTermination Island VTT/VREF Generator

SSTL_2

Address/Cmnd Chip Selects

PC266 SDRAM Reg. DIMM

Chipset
North Bridge
SSTL_2

PC266 SDRAM Reg. DIMM

Address / Command

VTT Termination Island

Data/Strobe/Mask

December, 00

SSTL2 Single Ended Termination

VTT/VREF Generator

SSTL_2

Address/Cmnd Chip Selects

Chipset
North Bridge
SSTL_2

PC266 SDRAM Reg. DIMM

PC266 SDRAM Reg. DIMM

Address/Command

VTT Termination Island

Data/Strobe/Mask

December, 00

Use Single Parallel Termination Resistor With Series Resistor

m Lower system cost m Easier motherboard route m Improved bandwidth m Lower skew due to ISI m Reduced skew due to crosstalk if done properly
Consider crosstalk effects in the connector pinout

December, 00

Double Data Rate Motherboard Components

VDD generator switching regulator Series Seriestermination termination resistor resistorpacks packs
V DD V DD

Differential Differential clock clock synthesizer synthesizer

TT V TT V TT

Processor Processor

NB NB
CLK CLK

V /REF active VTT TT/REF active termination termination voltage voltage switching regulator switching regulator V TT V TTvoltage voltageisland island de-couple de-couplethoroughly thoroughly to VSS V DD and VSS

Four-layer motherboard

December, 00

Typical Signaling for DDR Main Memory

m The values for the series and termination resistors vary depending on the system design

December, 00

VTT/VREF Implementation

Goals of VTT and VREF Design

m Minimize timing skew due to
Asymmetric logic highs versus logic lows Noise on VREF or VTT Offset of VTT relative to VREF Drift of VREF or VTT over voltage and temperature External component mismatch

m Minimize cost m Minimize power dissipation

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VREF Requirements
m Track 50% of (VDDQ-VSSQ) over
Voltage Temperature Noise

m Supplies minimal DC current (input leakage only) and only small transient currents
Input to NFET gates of a differential pair

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VREF Tracking to VDDQ

VDDQ A VREF A VSSQ VDDQ B VREF B VSSQ

VDDQ VREF VSSQ

C C

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VREF Recommendations
m Use global VREF distribution scheme
Eliminates variation and tracking of multiple generators Best performance if kept clean

m Use simple resistor divider with 1% or better accuracy

Inexpensive to use Tracks voltage and temperature well

m Use VREFOUT pin of ML6554

Resistor divider is integrated on-chip Fewer external components Best accuracy and matching to V TT

due to trimming

Minimizes DC error caused by the load current of multiple device input leakage

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VREF Generation
m Example of VREF generation using a resistor divider

VDD

VDDQ

VDDQ

VDDQ

R VREF

R VSS VSS VSS VSS

Discrete Resistors or VREF ( OUT) of ML6654

December, 00

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VREF Layout Recommendations

m Maintain a 15-20 mil clearance from other nets m Use distributed decoupling scheme
Minimizes capacitor ESL Localizes transient currents and returns

m Simple implementation by routing on top signal layer trace

VREF is at connector pin 1 Isolate VREF and/or shield with VDDQ and VSSQ

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VREF PCB Routing

December, 00

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VTT Requirements
m Track 50% of (VDDQ-VSSQ) over
Voltage Temperature Noise

m Maintain <40mV offset from VREF over these conditions m Source and sink DC current for signal termination
Absolute maximum current is 2.6-2.9A for a 64/72-bit channel

December, 00

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VTT Recommendations
m Several solutions exist that are tradeoffs of cost, integration, and performance
Standard analog components (Motorola, National, Fairchild, etc.)
High current output, good accuracy

Switching regulator with discrete MOSFETs (such as LTC1430)

High current output (10A), good accuracy, semi-integrated

Switching regulator with integrated MOSFETs (such as ML6554)

Adequate current output (3A) and accuracy, highest integration, lowest cost

December, 00

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VTT Recommendations
(continued)
m Use global VREF as input reference to minimize tracking error and offset m Use high-quality filter components
Low Rs on filter inductor Low ESR and ESL on filter capacitor to minimize DC and dynamic offset
Recommend the use of multiple parallel capacitors and/or Sanyo OS-CONs to minimize ESR and ESL

December, 00

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VTT Regulation Circuit

m VTT regulation circuit using Micro Linear ML6554

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VTT Layout Recommendations

m Decouple to VSSQ
Decouple at both ends, and distribute decoupling across the island to localize transient currents and minimize ESL

m Place termination resistors on a top layer V TT island

Island is at the end of the bus and non-obstructing Use wide-island trace for current capacity Place VTT generator as close to termination resistors as possible to minimize impedance (inductance)

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VTT Island PCB Layout

ML6554 Regulator

Vtt Power Plane Decoupling Capacitors

Termination Resistors

December, 00

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2.5 Volt Regulation

m 2.5 volt regulation circuit using Linear Technology LTC1530-2.5

December, 00

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2.5 Volt Regulation Layout

m Regulated V2.5 ties to solid power plane under DIMMs and DRAM controller portion of Samurai DDR

Vcc Input LTC1530 Regulator Regulated V2.5

December, 00

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Voltage Margining

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VREF/VTT Margining
m Use the V REF In pin on the ML6554 to margin V REF and VTT
VTT and VREF out follow VREF In

m VREF specification is 0.49*VDD to 0.51*VDD m VTT specification is V REF +/- 40mV m Use simple resistor divider below connected to VREF In pin on ML6554

VREF In On ML6554 1K 1K

VDD 0.1uF 0.1uF 100 ohm Variable Resistor

December, 00

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VDD Margining
m VDD specification is 2.3 to 2.7 volts m To margin VDD change LTC1530-2.5 to LTC1530-ADJ m Adjust VDD with resistor divider R1/R2.

December, 00

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VDD Margining
+5 volts input

2.5 Volt Vdd output

R1 R2

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Board Implementation

29

Registered-Only Motherboard Topology

VREF

Difntl Clk Drvr

Mem Clock
SSTL_2

CK/CK#

VTT/VREF Generator

Address/Cmnd Chip Selects

Chipset
North Bridge
SSTL_2

PC266 SDRAM Reg. DIMM

PC266 PC266 PC266 A A SDRAM SDRAM SDRAM A Reg. Reg. Reg. DIMM DIMM DIMM

VTT Termination Island

Data/Strobe/Mask

December, 00

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Unbuffered/Registered Motherboard Topology

Vref Clocks
Vtt/Vref Generator

PC2100 Address/Command B DDR B DIMM

PC2100 DDR Add/Comnd B DIMM

Address/Command A

VTT Termination Island

Chipset
North Bridge

Add/Comnd A

PC2100 PC2100 DDR A DDR Chip Selects DIMM DIMM Data/DM/DQS

December, 00

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PCB Considerations
m PC2100 DDR can be implemented in a low-cost PCB (standard PC100 motherboard technology) m Standard pad, anti-pad and via sizes can be used m No additional PCB test requirements relative to PC100

December, 00

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PCB Routing
m DDR channel can be implemented in a 2S 2P board
Controller BGA ballout determines whether a four-layer board can be used, not the memory channel Two signal layers to get from controller to series resistor The channel can be routed on one signal layer from the series termination resistor out, with the exception of point-to-point signals

December, 00

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Reference Motherboard Routing

m Maintain signal reference through DDR channel
Route signals on layers adjacent to a common reference plane. Route each data group (8 x DQ + DQS + DM) on same layer to match propagation delays and minimize skew. Address and control matching is less critical. Separate data and control nets to minimize crosstalk.

m Routing Rules
5 mil trace/15 mil space on all in group SSTL nets Connector rules: 5 mil trace, 2 mil space from antipad, 7 mils from trace

December, 00

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Micron Samurai DDR Trace length matching rules

m Match trace lengths for each data group (8 x DQ + DQS + DM) to 0.1 inch from controller to first DIMM. m Match trace lengths to +/- 500 mils across the entire channel.
m Match composite length from controller bond pad to first DIMM pad
LBGA + Lcontroller-R + LR-DIMM = matched

m Length matching from last DIMM pad to parallel termination resistor is less critical

December, 00

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Length Matching from Controller to 1st DIMM Pin

LC-R1 LBGA1
RS RT

LR-D1
RS RT

LC-R2 LBGA2

LR-D2

LBGA1 + LC-R1 + LR-D1 = LBGA2 + LC-R2 + LR-D2

December, 00

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PCB Channel Routing Through the DIMMs

m A 5-mil width / 7-mil space board will yield:
Three vertical signal-routing channels Two diagonal signal-routing channels Second layer void except for point-to-point signals Lowest skew due to propagation-velocity mismatch between different signal layers

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Routing Through DIMMs

Series Resistors

Two Diagonal Signals

December, 00 38

Three Vertical Signals

Termination Resistor Placement

m Motherboard series resistors should be close to the first DIMM
Best performance for READ from last module Limiting case Simplifies routing and controller congestion

December, 00

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System Design Examples

December, 00

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DDR Memory Route 1st Layer

December, 00

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DDR Memory Route 2nd Layer

December, 00

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Reference Motherboard Stack-Up

m Reference board stack-up
6 Layer Board

4.5-Mils 6.5-Mils 30-Mils 6.5-Mils 4.5-Mils

Signal 1 GND Signal 2 Signal 3 Power Signal 4

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Questions and Answers

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