5M570ZT144I5N

3.
DC and Switching Characteristics for MAX V Devices

May 2011 MV51003-1.2 MV51003-1.2
This chapter covers the electrical and switching characteristics for MAX V devices. Electrical characteristics include operating conditions and power consumptions. This chapter also describes the timing model and specifications. You must consider the recommended DC and switching conditions described in this chapter to maintain the highest possible performance and reliability of the MAX V devices. This chapter contains the following sections:

Operating Conditions on page 31 Power Consumption on page 310 Timing Model and Specifications on page 310
Operating Conditions
Table 31 through Table 315 on page 39 list information about absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for MAX V devices.
Absolute Maximum Ratings

Table 31 lists the absolute maximum ratings for the MAX V device family.
Table 31. Absolute Maximum Ratings for MAX V Devices (Note 1), (2) Symbol VCCINT VCCIO VI IOUT TSTG TAMB TJ Parameter Internal supply voltage I/O supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias (3) TQFP and BGA packages under bias Conditions With respect to ground Minimum 0.5 0.5 0.5 25 65 65 Maximum 2.4 4.6 4.6 25 150 135 135 Unit V V V mA C C C
Notes to Table 31:

(1) For more information, refer to the Operating Requirements for Altera Devices Data Sheet. (2) Conditions beyond those listed in Table 31 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) For more information about under bias conditions, refer to Table 32.
2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
MAX V Device Handbook May 2011

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32
Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions
Recommended Operating Conditions

Table 32 lists recommended operating conditions for the MAX V device family.
Table 32. Recommended Operating Conditions for MAX V Devices Symbol VCCINT (1) Parameter 1.8-V supply voltage for internal logic and in-system programming (ISP) Supply voltage for I/O buffers, 3.3-V operation Supply voltage for I/O buffers, 2.5-V operation VCCIO (1) Supply voltage for I/O buffers, 1.8-V operation Supply voltage for I/O buffers, 1.5-V operation Supply voltage for I/O buffers, 1.2-V operation VI VO TJ Input voltage Output voltage Operating junction temperature Conditions MAX V devices (2), (3), (4) Commercial range Industrial range Extended range (5)
Notes to Table 32:
(1) MAX V device ISP and/or user flash memory (UFM) programming using JTAG or logic array is not guaranteed outside the recommended operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM, Altera recommends that you read back the UFM contents and verify it against the intended write data). (2) The minimum DC input is 0.5 V. During transitions, the inputs may undershoot to 2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) During transitions, the inputs may overshoot to the voltages shown below based on the input duty cycle. The DC case is equivalent to 100% duty cycle. For more information about 5.0-V tolerance, refer to the Using MAX V Devices in Multi-Voltage Systems chapter. Max. Duty Cycle VIN 4.0 V 100% (DC) 4.1 V 90% 4.2 V 50% 4.3 V 30% 4.4 V 17% 4.5 V 10% (4) All pins, including the clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (5) For the extended temperature range of 100 to 125C, MAX V UFM programming (erase/write) is only supported using the JTAG interface. UFM programming using the logic array interface is not guaranteed in this range.
Minimum 1.71 3.00 2.375 1.71 1.425 1.14 0.5 0 0 40 40
Maximum 1.89 3.60 2.625 1.89 1.575 1.26 4.0 VCCIO 85 100 125
Unit V V V V V V V V C C C
MAX V Device Handbook
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Programming/Erasure Specifications
Table 33 lists the programming/erasure specifications for the MAX V device family.
Table 33. Programming/Erasure Specifications for MAX V Devices Parameter Erase and reprogram cycles
Note to Table 33:
(1) This value applies to the commercial grade devices. For the industrial grade devices, the value is 100 cycles.
Block UFM Configuration flash memory (CFM)
Minimum
Typical
Maximum 1000 (1) 100
Unit Cycles Cycles
DC Electrical Characteristics
Table 34 lists DC electrical characteristics for the MAX V device family.
Table 34. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 1 of 2) Symbol II IOZ Parameter Tri-stated I/O pin leakage current Conditions Minimum 10 10 Typical Maximum 10 10 Unit A A
Input pin leakage current VI = VCCIO max to 0 V (2) VO = VCCIO max to 0 V (2) 5M40Z, 5M80Z, 5M160Z, and 5M240Z (Commercial grade) (4), (5) 5M240Z (Commercial grade) (6)
25
90
27
96
ICCSTANDBY
VCCINT supply current (standby) (3)
5M40Z, 5M80Z, 5M160Z, and 5M240Z (Industrial grade) (5), (7) 5M240Z (Industrial grade) (6) 5M570Z (Commercial grade) (4) 5M570Z (Industrial grade) (7) 5M1270Z and 5M2210Z VCCIO = 3.3 V VCCIO = 2.5 V MAX V devices VCCIO = 3.3 V (11)
5 10 25 45 80
25 27 27 27 2 400 190
139 152 96 152 40 25 40 60 95 130
A A A A mA mV mV mA k k k k k
VSCHMITT (8) ICCPOWERUP
Hysteresis for Schmitt trigger input (9) VCCINT supply current during power-up (10)
RPULLUP
Value of I/O pin pull-up resistor during user mode and ISP
VCCIO = 2.5 V (11) VCCIO = 1.8 V (11) VCCIO = 1.5 V (11) VCCIO = 1.2 V (11)
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Table 34. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 2 of 2) Symbol IPULLUP CIO CGCLK Parameter I/O pin pull-up resistor current when I/O is unprogrammed Input capacitance for user I/O pin Input capacitance for dual-purpose GCLK/user I/O pin Conditions Minimum Typical Maximum 300 Unit A
pF
pF
Notes to Table 34:

(1) Typical values are for TA = 25C, VCCINT = 1.8 V and VCCIO = 1.2, 1.5, 1.8, 2.5, or 3.3 V. (2) This value is specified for normal device operation. The value may vary during power-up. This applies to all VCCIO settings (3.3, 2.5, 1.8, 1.5, and 1.2 V). (3) VI = ground, no load, and no toggling inputs. (4) Commercial temperature ranges from 0C to 85C with the maximum current at 85C. (5) Not applicable to the T144 package of the 5M240Z device. (6) Only applicable to the T144 package of the 5M240Z device. (7) Industrial temperature ranges from 40C to 100C with the maximum current at 100C. (8) This value applies to commercial and industrial range devices. For extended temperature range devices, the V SCHMITT typical value is 300 mV for VCCIO = 3.3 V and 120 mV for VCCIO = 2.5 V. (9) The TCK input is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I/O standards. (10) This is a peak current value with a maximum duration of tCONFIG time. (11) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
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Output Drive Characteristics

Figure 31 shows the typical drive strength characteristics of MAX V devices.
Figure 31. Output Drive Characteristics of MAX V Devices (Note 1)
MAX V Output Drive IOH Characteristics (Maximum Drive Strength)
70
60
MAX V Output Drive IOL Characteristics (Maximum Drive Strength)

3.3-V VCCIO
3.3-V VCCIO
Typical I O Output Current (mA) Typical IO Output Current (mA)
60
50
50
40
40
2.5-V VCCIO
2.5-V VCCIO
30
30
20
1.8-V VCCIO 1.5-V VCCIO
20
10
10
1.2-V VCCIO (2)

0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
0 0.0 0.5
1.2-V VCCIO (2)
1.0
1.5
2.0
2.5
3.0
3.5
Voltage (V)
Voltage (V)
MAX V Output Drive IOH Characteristics (Minimum Drive Strength)

35 30
MAX V Output Drive IOL Characteristics (Minimum Drive Strength)

3.3-V VCCIO
3.3-V VCCIO
Typical IO Output Current (mA) Typical IO Output Current (mA)
30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 25
20
2.5-V VCCIO
2.5-V VCCIO
15
10
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Voltage (V)
Voltage (V)
Notes to Figure 31:

(1) The DC output current per pin is subject to the absolute maximum rating of Table 31 on page 31. (2) 1.2-V VCCIO is only applicable to the maximum drive strength.
I/O Standard Specifications

Table 35 through Table 313 on page 38 list the I/O standard specifications for the MAX V device family.
Table 35. 3.3-V LVTTL Specifications for MAX V Devices Symbol VCCIO VIH VIL VOH VOL Parameter I/O supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions IOH = 4 mA (1) IOL = 4 mA (1) Minimum 3.0 1.7 0.5 2.4 Maximum 3.6 4.0 0.8 0.45 Unit V V V V V
Note to Table 35:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the MAX V Device Architecture chapter.
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Table 36. 3.3-V LVCMOS Specifications for MAX V Devices Symbol VCCIO VIH VIL VOH VOL Parameter I/O supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions VCCIO = 3.0, IOH = 0.1 mA (1) VCCIO = 3.0, IOL = 0.1 mA (1) Minimum 3.0 1.7 0.5 VCCIO 0.2 Maximum 3.6 4.0 0.8 0.2 Unit V V V V V
Note to Table 36:

Table 37. 2.5-V I/O Specifications for MAX V Devices Symbol VCCIO VIH VIL VOH Parameter I/O supply voltage High-level input voltage Low-level input voltage High-level output voltage Conditions IOH = 0.1 mA (1) IOH = 1 mA (1) IOH = 2 mA (1) IOL = 0.1 mA (1) VOL Low-level output voltage IOL = 1 mA (1) IOL = 2 mA (1)
Note to Table 37:
Minimum 2.375 1.7 0.5 2.1 2.0 1.7
Maximum 2.625 4.0 0.7 0.2 0.4 0.7
Unit V V V V V V V V V
Table 38. 1.8-V I/O Specifications for MAX V Devices Symbol VCCIO VIH VIL VOH VOL Parameter I/O supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions IOH = 2 mA (1) IOL = 2 mA (1) Minimum 1.71 0.65 VCCIO 0.3 VCCIO 0.45 Maximum 1.89 2.25 (2) 0.35 VCCIO 0.45 Unit V V V V V
Notes to Table 38:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the MAX V Device Architecture chapter. (2) This maximum VIH reflects the JEDEC specification. The MAX V input buffer can tolerate a VIH maximum of 4.0, as specified by the VI parameter in Table 32 on page 32.
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Table 39. 1.5-V I/O Specifications for MAX V Devices Symbol VCCIO VIH VIL VOH VOL Parameter I/O supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions IOH = 2 mA (1) IOL = 2 mA (1) Minimum 1.425 0.65 VCCIO 0.3 0.75 VCCIO Maximum 1.575 VCCIO + 0.3 (2) 0.35 VCCIO 0.25 VCCIO Unit V V V V V
Notes to Table 39:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the MAX V Device Architecture chapter. (2) This maximum VIH reflects the JEDEC specification. The MAX V input buffer can tolerate a VIH maximum of 4.0, as specified by the VI parameter in Table 32 on page 32.
Table 310. 1.2-V I/O Specifications for MAX V Devices Symbol VCCIO VIH VIL VOH VOL Parameter I/O supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions IOH = 2 mA (1) IOL = 2 mA (1) Minimum 1.14 0.8 VCCIO 0.3 0.75 VCCIO Maximum 1.26 VCCIO + 0.3 0.25 VCCIO 0.25 VCCIO Unit V V V V V
Note to Table 310:

Table 311. 3.3-V PCI Specifications for MAX V Devices (Note 1) Symbol VCCIO VIH VIL VOH VOL Parameter I/O supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions IOH = 500 A IOL = 1.5 mA Minimum 3.0 0.5 VCCIO 0.5 0.9 VCCIO Typical 3.3 Maximum 3.6 VCCIO + 0.5 0.3 VCCIO 0.1 VCCIO Unit V V V V V
Note to Table 311:

(1) 3.3-V PCI I/O standard is only supported in Bank 3 of the 5M1270Z and 5M2210Z devices.
Table 312. LVDS Specifications for MAX V Devices (Note 1) Symbol VCCIO VOD VOS Parameter I/O supply voltage Differential output voltage swing Output offset voltage Conditions Minimum 2.375 247 1.125 Typical 2.5 1.25 Maximum 2.625 600 1.375 Unit V mV V
Note to Table 312:

(1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R).
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Table 313. RSDS Specifications for MAX V Devices (Note 1) Symbol VCCIO VOD VOS Parameter I/O supply voltage Differential output voltage swing Output offset voltage Conditions Minimum 2.375 247 1.125 Typical 2.5 1.25 Maximum 2.625 600 1.375 Unit V mV V
Note to Table 313:

(1) Supports emulated RSDS output using a three-resistor network (RSDS_E_3R).
Bus Hold Specifications

Table 314 lists the bus hold specifications for the MAX V device family.
Table 314. Bus Hold Specifications for MAX V Devices VCCIO Level Parameter Conditions 1.2 V Min Low sustaining current High sustaining current Low overdrive current High overdrive current VIN > VIL (maximum) VIN < VIH (minimum) 0 V < VIN < VCCIO 0 V < VIN < VCCIO 10 10 Max 130 130 1.5 V Min 20 20 Max 160 160 1.8 V Min 30 30 Max 200 200 2.5 V Min 50 50 Max 300 300 3.3 V Min 70 70 Max 500 500 A A A A Unit
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Power-Up Timing
Table 315 lists the power-up timing characteristics for the MAX V device family.
Table 315. Power-Up Timing for MAX V Devices Symbol Parameter Device 5M40Z 5M80Z 5M160Z 5M240Z (2) tCONFIG The amount of time from when minimum VCCINT is reached until the device enters user mode (1) 5M240Z (3) 5M570Z 5M1270Z (4) 5M1270Z (5) 5M2210Z
Notes to Table 315:
(1) For more information about power-on reset (POR) trigger voltage, refer to the Hot Socketing and Power-On Reset in MAX V Devices chapter. (2) Not applicable to the T144 package of the 5M240Z device. (3) Only applicable to the T144 package of the 5M240Z device. (4) Not applicable to the F324 package of the 5M1270Z device. (5) Only applicable to the F324 package of the 5M1270Z device.
Temperature Range Commercial and industrial Extended Commercial and industrial Extended Commercial and industrial Extended Commercial and industrial Extended Commercial and industrial Extended Commercial and industrial Extended Commercial and industrial Extended Commercial and industrial Extended Commercial and industrial Extended
Min
Typ
Max 200 300 200 300 200 300 200 300 300 400 300 400 300 400 450 500 450 500
Unit s s s s s s s s s s s s s s s s s s
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Chapter 3: DC and Switching Characteristics for MAX V Devices Power Consumption
Power Consumption
You can use the Altera PowerPlay Early Power Estimator and PowerPlay Power Analyzer to estimate the device power. f For more information about these power analysis tools, refer to the PowerPlay Early Power Estimator for Altera CPLDs User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook.
Timing Model and Specifications

MAX V devices timing can be analyzed with the Altera Quartus II software, a variety of industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 32. MAX V devices have predictable internal delays that allow you to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation.
Figure 32. Timing Model for MAX V Devices
Output and Output Enable Data Delay
t R4
Data-In/LUT Chain User Flash Memory Logic Element

LUT Delay
tIODR tIOE
t C4
Output Routing Delay
t LOCAL
t LUT
Register Control Delay
tCOMB tCO tSU tH tPRE tCLR
t FASTIO
I/O Input Delay t IN
Input Routing Delay tDL
Output Delay t OD t XZ t ZX
I/O Pin
tC
I/O Pin
INPUT
t GLOB Global Input Delay

To Adjacent LE Register Delays
From Adjacent LE Combinational Path Delay Data-Out
You can derive the timing characteristics of any signal path from the timing model and parameters of a particular device. You can calculate external timing parameters, which represent pin-to-pin timing delays, as the sum of the internal parameters. f For more information, refer to AN629: Understanding Timing in Altera CPLDs.
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Chapter 3: DC and Switching Characteristics for MAX V Devices Timing Model and Specifications
311
Preliminary and Final Timing

This section describes the performance, internal, external, and UFM timing specifications. All specifications are representative of the worst-case supply voltage and junction temperature conditions. Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 316 lists the status of the MAX V device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under the worst-case voltage and junction temperature conditions.
Table 316. Timing Model Status for MAX V Devices Device 5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z Final v v v v v v v
Performance
Table 317 lists the MAX V device performance for some common designs. All performance values were obtained with the Quartus II software compilation of megafunctions.
Table 317. Device Performance for MAX V Devices (Part 1 of 2) Performance Resources Used Resource Used Design Size and Function Mode 16-bit counter (1) 64-bit counter (1) 16-to-1 multiplexer LE 32-to-1 multiplexer 16-bit XOR function 16-bit decoder with single address line LEs 16 64 11 24 5 5 UFM Blocks 0 0 0 0 0 0 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 184.1 83.2 17.4 12.5 9.0 9.2 C5, I5 118.3 80.5 20.4 25.3 16.1 16.1 5M1270Z/ 5M2210Z C4 247.5 154.8 8.0 9.0 6.6 6.6 C5, I5 201.1 125.8 9.3 11.4 8.2 8.2 MHz MHz ns ns ns ns Unit
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Table 317. Device Performance for MAX V Devices (Part 2 of 2) Performance Resources Used Resource Used Design Size and Function Mode 512 16 512 16 UFM 512 8 512 16
Notes to Table 317:
(1) This design is a binary loadable up counter. (2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used. (3) This design is configured for read-only operation. Read and write ability increases the number of LEs used. (4) This design is asynchronous. (5) The I2C megafunction is verified in hardware up to 100-kHz serial clock line rate.
5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 10.0 9.7 (4) 100 (5) C5, I5 10.0 9.7 (4) 100 (5)
5M1270Z/ 5M2210Z C4 10.0 8.0 (4) 100 (5) C5, I5 10.0 8.0 (4) 100 (5)
Unit
LEs 3 37 73 142
UFM Blocks 1 1 1 1
None SPI (2) Parallel (3) I2C (3)
MHz MHz MHz kHz
Internal Timing Parameters

Internal timing parameters are specified on a speed grade basis independent of device density. Table 318 through Table 325 on page 319 list the MAX V device internal timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and MultiTrack interconnects. f For more information about each internal timing microparameters symbol, refer to AN629: Understanding Timing in Altera CPLDs.
Table 318. LE Internal Timing Microparameters for MAX V Devices (Part 1 of 2) 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Symbol Parameter Min tLUT tCOMB tCLR tPRE tSU tH tCO LE combinational look-up table (LUT) delay Combinational path delay LE register clear delay LE register preset delay LE register setup time before clock LE register hold time after clock LE register clock-to-output delay 401 401 260 0 C4 Max 1,215 243 380 Min 545 545 321 0 C5, I5 Max 2,247 309 494 Min 309 309 271 0 5M1270Z/ 5M2210Z C4 Max 742 192 305 Min 381 381 333 0 C5, I5 Max 914 236 376 ps ps ps ps ps ps ps Unit
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Table 318. LE Internal Timing Microparameters for MAX V Devices (Part 2 of 2) 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Symbol Parameter Min tCLKHL tC Minimum clock high or low time Register control delay 253 C4 Max 1,356 Min 339 C5, I5 Max 1,741 Min 216 5M1270Z/ 5M2210Z C4 Max 1,114 Min 266 C5, I5 Max 1,372 ps ps Unit
Table 319. IOE Internal Timing Microparameters for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Symbol Parameter Min tFASTIO tIN tGLOB (1) tIOE tDL tOD (2) tXZ (3) tZX (4) Data output delay from adjacent LE to I/O block I/O input pad and buffer delay I/O input pad and buffer delay used as global signal pin Internally generated output enable delay Input routing delay Output delay buffer and pad delay Output buffer disable delay Output buffer enable delay C4 Max 170 907 Min C5, I5 Max 428 986 Min 5M1270Z/ 5M2210Z C4 Max 207 920 Min C5, I5 Max 254 1,132 ps ps Unit
2,261
3,322
1,974
2,430
ps
530 318 1,319 1,045 1,160
1,410 509 1,543 1,276 1,353
374 291 1,383 982 1,303
460 358 1,702 1,209 1,604
ps ps ps ps ps
Notes to Table 319:

(1) Delay numbers for tGLOB differ for each device density and speed grade. The delay numbers for tGLOB, shown in Table 319, are based on a 5M240Z device target. (2) For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 334 on page 324 and Table 335 on page 325. (3) For more information about tXZ delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 322 on page 315 and Table 323 on page 315. (4) For more information about tZX delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 320 on page 314 and Table 321 on page 314.
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Table 320 through Table 323 list the adder delays for tZX and tXZ microparameters when using an I/O standard other than 3.3-V LVTTL with 16 mA drive strength.
Table 320. tZX IOE Microparameter Adders for Fast Slew Rate for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Standard Min 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI LVDS RSDS 16 mA 8 mA 8 mA 4 mA 14 mA 7 mA 6 mA 3 mA 4 mA 2 mA 3 mA 20 mA C4 Max 0 72 0 72 126 196 608 681 1162 1245 1889 72 126 126 Min C5, I5 Max 0 74 0 74 127 197 610 685 1157 1244 1856 74 127 127 Min 5M1270Z/ 5M2210Z C4 Max 0 101 0 101 155 545 721 2012 1590 3269 2860 18 155 155 Min C5, I5 Max 0 125 0 125 191 671 888 2477 1957 4024 3520 22 191 191 ps ps ps ps ps ps ps ps ps ps ps ps ps ps Unit
Table 321. tZX IOE Microparameter Adders for Slow Slew Rate for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Standard Min 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI 16 mA 8 mA 8 mA 4 mA 14 mA 7 mA 6 mA 3 mA 4 mA 2 mA 3 mA 20 mA C4 Max 5,951 6,534 5,951 6,534 9,110 9,830 21,800 23,020 39,120 40,670 69,505 6,534 Min C5, I5 Max 6,063 6,662 6,063 6,662 9,237 9,977 21,787 23,037 39,067 40,617 70,461 6,662 Min 5M1270Z/ 5M2210Z C4 Max 6,012 8,785 6,012 8,785 10,072 12,945 21,185 24,597 34,517 39,717 55,800 35 Min C5, I5 Max 5,743 8,516 5,743 8,516 9,803 12,676 20,916 24,328 34,248 39,448 55,531 44 ps ps ps ps ps ps ps ps ps ps ps ps Unit
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Table 322. tXZ IOE Microparameter Adders for Fast Slew Rate for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Standard Min 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI LVDS RSDS 16 mA 8 mA 8 mA 4 mA 14 mA 7 mA 6 mA 3 mA 4 mA 2 mA 3 mA 20 mA C4 Max 0 69 0 69 7 66 45 34 166 190 300 69 7 7 Min C5, I5 Max 0 69 0 69 10 69 37 25 155 179 283 69 10 10 Min 5M1270Z/ 5M2210Z C4 Max 0 74 0 74 46 82 7 119 339 464 817 80 46 46 Min C5, I5 Max 0 91 0 91 56 101 8 147 418 571 1,006 99 56 56 ps ps ps ps ps ps ps ps ps ps ps ps ps ps Unit
Table 323. tXZ IOE Microparameter Adders for Slow Slew Rate for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Standard Min 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI 16 mA 8 mA 8 mA 4 mA 14 mA 7 mA 6 mA 3 mA 4 mA 2 mA 3 mA 20 mA C4 Max 171 112 171 112 213 166 441 496 765 903 1,159 112 Min C5, I5 Max 174 116 174 116 213 166 438 494 755 897 1,130 116 Min 5M1270Z/ 5M2210Z C4 Max 73 758 73 758 32 714 96 963 238 1,319 400 303 Min C5, I5 Max 132 553 132 553 173 509 109 758 33 1,114 195 373 ps ps ps ps ps ps ps ps ps ps ps ps Unit
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The default slew rate setting for MAX V devices in the Quartus II design software is fast.
Table 324. UFM Block Internal Timing Microparameters for MAX V Devices (Part 1 of 2) 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Symbol Parameter Min tACLK tASU Address register clock period Address register shift signal setup to address register clock Address register shift signal hold to address register clock Address register data in setup to address register clock Address register data in hold from address register clock Data register clock period Data register shift signal setup to data register clock Data register shift signal hold from data register clock Data register data in setup to data register clock Data register data in hold from data register clock Program signal to data clock hold time Maximum delay between program rising edge to UFM busy signal rising edge Minimum delay allowed from UFM busy signal going low to program signal going low Maximum length of busy pulse during a program 100 C4 Max Min 100 C5, I5 Max Min 100 5M1270Z/ 5M2210Z C4 Max Min 100 C5, I5 Max ns Unit
20
20
20
20
ns
tAH
20
20
20
20
ns
tADS
20
20
20
20
ns
tADH tDCLK tDSS
20 100 60
20 100 60
20 100 60
20 100 60
ns ns ns
tDSH
20
20
20
20
ns
tDDS tDDH tDP
20
20
20
20
ns
20 0
20 0
20 0
20 0
ns ns
tPB
960
960
960
960
ns
tBP
20
20
20
20
ns
tPPMX
100
100
100
100
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Table 324. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 2) 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Symbol Parameter Min tAE Minimum erase signal to address clock hold time Maximum delay between the erase rising edge to the UFM busy signal rising edge Minimum delay allowed from the UFM busy signal going low to erase signal going low Maximum length of busy pulse during an erase Delay from data register clock to data register output Delay from OSC_ENA signal reaching UFM to rising clock of OSC leaving the UFM Maximum read access time Maximum delay between the OSC_ENA rising edge to the erase/program signal rising edge Minimum delay allowed from the erase/program signal going low to OSC_ENA signal going low 0 C4 Max Min 0 C5, I5 Max Min 0 5M1270Z/ 5M2210Z C4 Max Min 0 C5, I5 Max ns Unit
tEB
960
960
960
960
ns
tBE
20
20
20
20
ns
tEPMX tDCO
500
500
500
500
ms
ns
tOE
180
180
180
180
ns
tRA
65
65
65
65
ns
tOSCS
250
250
250
250
ns
tOSCH
250
250
250
250
ns
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Figure 33 through Figure 35 show the read, program, and erase waveforms for UFM block timing parameters listed in Table 324.
Figure 33. UFM Read Waveform
ARShft ARClk ARDin DRShft DRClk DRDin DRDout OSC_ENA Program Erase Busy tADS tDSS tDCO tDCLK 16 Data Bits tDSH tASU tACLK 9 Address Bits tAH tADH
Figure 34. UFM Program Waveform

ARShft ARClk ARDin DRShft DRClk DRDin DRDout OSC_ENA Program Erase Busy
tPPMX
tASU
9 Address Bits tACLK
tAH tADH
tADS tDSS
16 Data Bits tDCLK
tDSH
tDDS
tDDH tOSCS tOSCH
tPB
tBP
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Figure 35. UFM Erase Waveform

ARShft ARClk ARDin DRShft DRClk DRDin DRDout OSC_ENA Program Erase Busy tEB tEPMX tBE tOSCS tOSCH tADS tASU tACLK
9 Address Bits
tAH tADH
Table 325. Routing Delay Internal Timing Microparameters for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Routing Min tC4 tR4 tLOCAL C4 Max 860 655 1,143 Min C5, I5 Max 1,973 1,479 2,947 Min 5M1270Z/ 5M2210Z C4 Max 561 445 731 Min C5, I5 Max 690 548 899 ps ps ps Unit
External Timing Parameters

External timing parameters are specified by device density and speed grade. All external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the maximum drive strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different drive strengths, use the I/O standard input and output delay adders in Table 332 on page 323 through Table 336 on page 325. f For more information about each external timing parameters symbol, refer to AN629: Understanding Timing in Altera CPLDs.
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Table 326 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices.
Table 326. Global Clock External I/O Timing Parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z Devices (Note 1), (2) C4 Symbol tPD1 tPD2 tSU tH tCO tCH tCL tCNT fCNT Parameter Worst case pin-to-pin delay through one LUT Best case pin-to-pin delay through one LUT Global clock setup time Global clock hold time Global clock to output delay Global clock high time Global clock low time Minimum global clock period for 16-bit counter Maximum global clock frequency for 16-bit counter Condition Min 10 pF 10 pF 10 pF 2.4 0 2.0 253 253 5.4 Max 7.9 5.8 6.6 184.1 Min 4.6 0 2.0 339 339 8.4 Max 14.0 8.5 8.6 118.3 ns ns ns ns ns ps ps ns MHz C5, I5 Unit
Notes to Table 326:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. (2) Not applicable to the T144 package of the 5M240Z device.
Table 327 lists the external I/O timing parameters for the T144 package of the 5M240Z device.
Table 327. Global Clock External I/O Timing Parameters for the 5M240Z Device (Note 1), (2) C4 Symbol tPD1 tPD2 tSU tH tCO tCH tCL tCNT fCNT Parameter Worst case pin-to-pin delay through one LUT Best case pin-to-pin delay through one LUT Global clock setup time Global clock hold time Global clock to output delay Global clock high time Global clock low time Minimum global clock period for 16-bit counter Maximum global clock frequency for 16-bit counter Condition Min 10 pF 10 pF 10 pF 2.2 0 2.0 253 253 5.4 Max 9.5 5.7 6.7 184.1 Min 4.4 0 2.0 339 339 8.4 Max 17.7 8.5 8.7 118.3 ns ns ns ns ns ps ps ns MHz C5, I5 Unit
Notes to Table 327:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. (2) Only applicable to the T144 package of the 5M240Z device.
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Table 328 lists the external I/O timing parameters for the 5M570Z device.
Table 328. Global Clock External I/O Timing Parameters for the 5M570Z Device (Note 1) C4 Symbol tPD1 tPD2 tSU tH tCO tCH tCL tCNT fCNT Parameter Worst case pin-to-pin delay through one LUT Best case pin-to-pin delay through one LUT Global clock setup time Global clock hold time Global clock to output delay Global clock high time Global clock low time Minimum global clock period for 16-bit counter Maximum global clock frequency for 16-bit counter Condition Min 10 pF 10 pF 10 pF 2.2 0 2.0 253 253 5.4 Max 9.5 5.7 6.7 184.1 Min 4.4 0 2.0 339 339 8.4 Max 17.7 8.5 8.7 118.3 ns ns ns ns ns ps ps ns MHz C5, I5 Unit
Note to Table 328:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency.
Notes to Table 329:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. (2) Not applicable to the F324 package of the 5M1270Z device.
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Table 330 lists the external I/O timing parameters for the F324 package of the 5M1270Z device.
Notes to Table 330:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. (2) Only applicable to the F324 package of the 5M1270Z device.
Table 331. Global Clock External I/O Timing Parameters for the 5M2210Z Device (Note 1) C4 Symbol tPD1 tPD2 tSU tH tCO tCH tCL tCNT fCNT Parameter Worst case pin-to-pin delay through one LUT Best case pin-to-pin delay through one LUT Global clock setup time Global clock hold time Global clock to output delay Global clock high time Global clock low time Minimum global clock period for 16-bit counter Maximum global clock frequency for 16-bit counter Condition Min 10 pF 10 pF 10 pF 1.5 0 2.0 216 216 4.0 Max 9.1 4.8 6.0 247.5 Min 1.9 0 2.0 266 266 5.0 Max 11.2 5.9 7.4 201.1 ns ns ns ns ns ps ps ns MHz C5, I5 Unit
Note to Table 331:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency.
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External Timing I/O Delay Adders

The I/O delay timing parameters for the I/O standard input and output adders and the input delays are specified by speed grade, independent of device density. Table 332 through Table 336 on page 325 list the adder delays associated with I/O pins for all packages. If you select an I/O standard other than 3.3-V LVTTL, add the input delay adder to the external tSU timing parameters listed in Table 326 on page 320 through Table 331. If you select an I/O standard other than 3.3-V LVTTL with 16 mA drive strength and fast slew rate, add the output delay adder to the external tCO and tPD listed in Table 326 on page 320 through Table 331.
Table 332. External Timing Input Delay Adders for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z I/O Standard Min Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger C4 Max 0 387 0 387 42 429 378 681 1,055 0 Min C5, I5 Max 0 442 0 442 42 483 368 658 1,010 0 Min 5M1270Z/ 5M2210Z C4 Max 0 480 0 480 246 787 695 1,334 2,324 0 Min C5, I5 Max 0 591 0 591 303 968 855 1,642 2,860 0 ps ps ps ps ps ps ps ps ps ps Unit
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI
Table 333. External Timing Input Delay tGLOB Adders for GCLK Pins for MAX V Devices (Part 1 of 2) 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z I/O Standard Min Without Schmitt Trigger With Schmitt Trigger C4 Max 0 387 Min C5, I5 Max 0 442 Min 5M1270Z/ 5M2210Z C4 Max 0 400 Min C5, I5 Max 0 493 ps ps Unit
3.3-V LVTTL
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Table 333. External Timing Input Delay tGLOB Adders for GCLK Pins for MAX V Devices (Part 2 of 2) 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z I/O Standard Min Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger C4 Max 0 387 242 429 378 681 1,055 0 Min C5, I5 Max 0 442 242 483 368 658 1,010 0 Min 5M1270Z/ 5M2210Z C4 Max 0 400 287 550 459 1,111 2,067 7 Min C5, I5 Max 0 493 353 677 565 1,368 2,544 9 ps ps ps ps ps ps ps ps Unit
3.3-V LVCMOS
2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI
Table 334. External Timing Output Delay and tOD Adders for Fast Slew Rate for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z I/O Standard Min 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI LVDS RSDS 16 mA 8 mA 8 mA 4 mA 14 mA 7 mA 6 mA 3 mA 4 mA 2 mA 3 mA 20 mA C4 Max 0 39 0 39 122 196 624 686 1,188 1,279 1,911 39 122 122 Min C5, I5 Max 0 58 0 58 129 188 624 694 1,184 1,280 1,883 58 129 129 Min 5M1270Z/ 5M2210Z C4 Max 0 84 0 84 158 251 738 850 1,376 1,517 2,206 4 158 158 Min C5, I5 Max 0 104 0 104 195 309 909 1,046 1,694 1,867 2,715 5 195 195 ps ps ps ps ps ps ps ps ps ps ps ps ps ps Unit
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Table 335. External Timing Output Delay and tOD Adders for Slow Slew Rate for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z I/O Standard Min 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI 16 mA 8 mA 8 mA 4 mA 14 mA 7 mA 6 mA 3 mA 4 mA 2 mA 3 mA 20 mA C4 Max 5,913 6,488 5,913 6,488 9,088 9,808 21,758 23,028 39,068 40,578 69,332 6,488 Min C5, I5 Max 6,043 6,645 6,043 6,645 9,222 9,962 21,782 23,032 39,032 40,542 70,257 6,645 Min 5M1270Z/ 5M2210Z C4 Max 6,612 7,313 6,612 7,313 10,021 10,881 21,134 22,399 34,499 36,281 55,796 339 Min C5, I5 Max 6,293 6,994 6,293 6,994 9,702 10,562 20,815 22,080 34,180 35,962 55,477 418 ps ps ps ps ps ps ps ps ps ps ps ps Unit
Table 336. IOE Programmable Delays for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z Parameter Min Input Delay from Pin to Internal Cells = 1 Input Delay from Pin to Internal Cells = 0 C4 Max 1,858 569 Min C5, I5 Max 2,214 616 Min 5M1270Z/ 5M2210Z C4 Max 1,592 115 Min C5, I5 Max 1,960 142 ps ps Unit
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Maximum Input and Output Clock Rates

Table 337 and Table 338 list the maximum input and output clock rates for standard I/O pins in MAX V devices.
Table 337. Maximum Input Clock Rate for I/Os for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ 5M2210Z C4, C5, I5 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger With Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger Without Schmitt Trigger 304 304 304 304 304 304 304 304 200 200 150 120 304 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
I/O Standard
Unit
Table 338. Maximum Output Clock Rate for I/Os for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ 5M2210Z C4, C5, I5 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI LVDS RSDS 304 304 304 304 200 200 150 120 304 304 200 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
I/O Standard
Unit
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LVDS and RSDS Output Timing Specifications

Table 339 lists the emulated LVDS output timing specifications for MAX V devices.
Table 339. Emulated LVDS Output Timing Specifications for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ 5M2210Z Parameter Mode C4, C5, I5 Min 10 9 8 7 Data rate (1), (2) 6 5 4 3 2 1 tDUTY Total jitter (3) tRISE tFALL
Notes to Table 339:
(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the twothe maximum data rate supported by LVDS_E_3R I/O buffer or 2x (FMAX of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through the Quartus II timing analysis of the complete design. (2) For the input clock pin to achieve 304 Mbps, use I/O standard with VCCIO of 2.5 V and above. (3) This specification is based on external clean clock source.
Unit Max 304 304 304 304 304 304 304 304 304 304 55 0.2 450 450 Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps % UI ps ps
45
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Table 340 lists the emulated RSDS output timing specifications for MAX V devices.
Table 340. Emulated RSDS Output Timing Specifications for MAX V Devices 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ 5M2210Z Parameter Mode C4, C5, I5 Min 10 9 8 7 Data rate (1) 6 5 4 3 2 1 tDUTY Total jitter (2) tRISE tFALL
Notes to Table 340:
(1) For the input clock pin to achieve 200 Mbps, use I/O standard with VCCIO of 1.8 V and above. (2) This specification is based on external clean clock source.
Unit Max 200 200 200 200 200 200 200 200 200 200 55 0.2 450 450 Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps % UI ps ps
45
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JTAG Timing Specifications

Figure 36 shows the timing waveform for the JTAG signals for the MAX V device family.
Figure 36. JTAG Timing Waveform for MAX V Devices
TMS
TDI
tJCP tJCH tJCL
tJPSU
tJPH
TCK
tJPZX tJPCO tJSSU tJSH tJPXZ
TDO Signal to be Captured

Signal to be Driven
tJSZX
tJSCO
tJSXZ
Table 341 lists the JTAG timing parameters and values for the MAX V device family.
Table 341. JTAG Timing Parameters for MAX V Devices (Part 1 of 2) Symbol Parameter TCK clock period for V CCIO1 = 3.3 V tJCP (1) TCK clock period for V CCIO1 = 2.5 V TCK clock period for V CCIO1 = 1.8 V TCK clock period for V CCIO1 = 1.5 V tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX TCK clock high time TCK clock low time JTAG port setup time (2) JTAG port hold time JTAG port clock to output (2) JTAG port high impedance to valid output (2) JTAG port valid output to high impedance (2) Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Min 55.5 62.5 100 143 20 20 8 10 8 10 Max 15 15 15 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Chapter 3: DC and Switching Characteristics for MAX V Devices Document Revision History
Table 341. JTAG Timing Parameters for MAX V Devices (Part 2 of 2) Symbol tJSXZ
Notes to Table 341:
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO degrades the maximum TCK frequency. (2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS operation, the tJPSU minimum is 6 ns and tJPCO, tJPZX, and tJPXZ are maximum values at 35 ns.
Parameter Update register valid output to high impedance
Min
Max 25
Unit ns
Document Revision History

Table 342 lists the revision history for this chapter.
Table 342. Document Revision History Date May 2011 January 2011 December 2010 Version 1.2 1.1 1.0 Changes Updated Table 32, Table 315, Table 316, and Table 333. Updated Table 337, Table 338, Table 339, and Table 340. Initial release.
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3.

DC and Switching Characteristics for MAX V Devices

Absolute Maximum Ratings

Notes to Table 31:

MAX V Device Handbook May 2011

This datasheet has been downloaded from http://www.digchip.com at this page

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

Recommended Operating Conditions

Minimum 1.71 3.00 2.375 1.71 1.425 1.14 0.5 0 0 40 40

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

Block UFM Configuration flash memory (CFM)

Maximum 1000 (1) 100

Unit Cycles Cycles

VCCINT supply current (standby) (3)

139 152 96 152 40 25 40 60 95 130

VSCHMITT (8) ICCPOWERUP

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

Notes to Table 34:

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

Output Drive Characteristics

MAX V Output Drive IOL Characteristics (Maximum Drive Strength)

1.8-V VCCIO 1.5-V VCCIO

1.8-V VCCIO 1.5-V VCCIO

1.2-V VCCIO (2)

1.2-V VCCIO (2)

MAX V Output Drive IOH Characteristics (Minimum Drive Strength)

MAX V Output Drive IOL Characteristics (Minimum Drive Strength)

1.8-V VCCIO 1.5-V VCCIO

1.8-V VCCIO 1.5-V VCCIO

0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Notes to Figure 31:

I/O Standard Specifications

Note to Table 35:

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

Note to Table 36:

Minimum 2.375 1.7 0.5 2.1 2.0 1.7

Maximum 2.625 4.0 0.7 0.2 0.4 0.7

Notes to Table 38:

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

Notes to Table 39:

Note to Table 310:

Note to Table 311:

Note to Table 312:

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

Note to Table 313:

Bus Hold Specifications

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Operating Conditions

MAX V Device Handbook

Chapter 3: DC and Switching Characteristics for MAX V Devices Power Consumption

Timing Model and Specifications

Data-In/LUT Chain User Flash Memory Logic Element

tCOMB tCO tSU tH tPRE tCLR

I/O Input Delay t IN

Input Routing Delay tDL

t GLOB Global Input Delay

From Adjacent LE Combinational Path Delay Data-Out

MAX V Device Handbook