HDL Lab Manual For VTU

HDL LAB MANUAL
PART-A
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PROCEDURE FOR EXECUTION OF HDL CODE IN XILINX 9.2i

01. Double Click on the Project Navigator
02. To close the Existing Project. File Close Project
03. To create a new project File New project. Give the project Name specify the Location. o Click on Next. With the device properties Specified below
o Click on Next. Select New Source. o Select the New source wizard, (Verilog Module or VHDL Module). o Give the file name. o Click on Next. Type the Entity Name and Architecture, Specify the ports. o Click on Next Finish. Click on Next Next Finish.
04. Double Click on *.vhd file and type the Program 05. Double click on Check syntax in Synthesize. 06. Change the Sources for to Behavioral Simulation. 07. Go to Project New Source
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Select the Test Bench Waveform
Click on NextNext Finish
Enter the data according to the code(either Sequential or Combinational) And Click on Finish
08. Force the data by clicking on the Blue Color areas. 09. Save the file. 10.Change the source for to Behavioral.
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11. Double Click on Simulate behavioral model in the Process Window.
To synthesize the Code using Spartan 2 kit. 11. Change the source for to Synthesis/ Implementation. 12. Go to User constraints and double click on Assign Package pins and Enter the pin details in LOC column. Save it
Select the first option (XST Default) and click OK.
13. Go to Generate Programming file and double click on Configure Device. Click on finish. Load the *.bit file to the IC. Right click on the IC and Load the program.
14. Check the output using GPIO kit.
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1. Logic gates Aim: To realize all the logic gates using HDL Description. Logic Diagram:
AND Truth Table:
OR
NAND
NOR
XOR
NOT
AND a 0 0 1 1 b 0 1 0 1 y(0) 0 0 0 1
OR y(1) 0 1 1 1
NAND y(2) 1 1 1 0
NOR y(3) 1 0 0 0
XOR y(4) 0 1 1 0
NOT y(5) 1 0 1 0
VHDL Description: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gates is Port ( a,b : in STD_LOGIC; y: out STD_LOGIC_VECTOR (5 downto 0)); end gates; architecture Behavioral of gates is begin y(0)<= a and b; y(1)<= a or b; y(2)<= a nand b; y(3)<= a nor b; y(4)<= a xor b; y(5)<= not b; end Behavioral; Verilog Description: module gates(a,b, y); input a,b; output [5:0] y; assign y[0]=a & b; assign y[1]=a | b; assign y[2]=~(a & b); assign y[3]=~(a | b); assign y[4]=~(a ^ b); assign y[5]=~ b;
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endmodule Output Graph:
Date: ____________ Observation
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Lab coordinator : ______________________ Lab coordinator: _______________________ 2. Binary to gray conversion Aim: To realize binary to gray combinational Block using HDL Description. Block Diagram
Truth Table: b(3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

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b(2) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
b(1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
b(0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
g(3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
g(2) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
g(1) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
g(0) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
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VHDL Description: entity bin is Port ( b : in STD_LOGIC_VECTOR (3 downto 0); g : out STD_LOGIC_VECTOR (3 downto 0)); end bin; architecture Behavioral of bin is begin g(3)<=b(3); g(2)<=b(3)xor b(2); g(1)<=b(2)xor b(1); g(0)<=b(1)xor b(0); end Behavioral; Verilog Description: module bin_veri(b, g); input [3:0] b; output [3:0] g; assign g[3]=b[3]; assign g[2]=b[3] ^ b[2]; assign g[1]=b[2] ^ b[1]; assign g[0]=b[1] ^ b[0]; endmodule Output Graph:
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Lab coordinator : ______________________ Lab coordinator: _______________________
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3.3-Bit comparator Aim: To realize 3-Bit comparator combinational Block using HDL Description. Block Diagram:
x=a<b
a(2),a(1),a(0)
3-bit comparator
b(2),b(1),b(0)
y=a>b
z=(a=b)
Truth Table: x a(2) 0 0 1 1 a(1) 0 0 1 0 a(0) 0 1 0 1 b(2) 0 0 1 1 b(1) 0 0 1 0 b(0) 0 0 1 1 a<b 0 0 1 0 y a>b 0 1 0 0 z a=b 1 0 0 1
VHDL Description: entity Comp is Port ( a,b : in STD_LOGIC_VECTOR (2 downto 0); x,y,z : out STD_LOGIC); end Comp; architecture Behavioral of Comp is begin process(a,b) begin x<='0'; y<='0';z<='0'; if(a>b) then y<='1'; elsif(a<b) then x<='1'; else z<='1'; end if; end process; end Behavioral;
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Verilog Description: module comp_3(a,b, x,y,z); input [2:0] a,b; output x,y,z; regx,y,z; always @ (a or b) begin x=0;y=0;z=0; if(a==b) x=1; else if(a>b) y=1; else z=1; end endmodule Output Graph:
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Date: ____________ Review no: ___
Marks Allotment: Attendance: Conduction: Write up: Viva: Lab coordinator: Lab coordinator:
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4:2 Encoder without priority Aim: To realize 4:2 encoder combinational Block using HDL Description. Block Diagram:
a(3) a(2) a(1) a(0) en 4:2Encoder y(1) y(0)
Truth Table: en 1 1 1 1 1 0 VHDL Description: X X a(3) 0 0 0 1 a(2) 0 0 1 0 Others X X a(1) 0 1 0 0 a(0) 1 0 0 0 y(1) 0 0 1 1 Z X y(0) 0 1 0 1 Z X
entity Encoder is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (1 downto 0); en : in STD_LOGIC); end Encoder; architecture Behavioral of Encoder is begin process(a,en) begin if(en='0') then y<="XX"; else case a is when "0001" => y<="00"; when "0010" => y<="01"; when "0100" => y<="10"; when "1000" => y<="11"; when others => y<="ZZ"; end case; end if; end process;
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end Behavioral; Verilog Description: module encoder(en, a, y); input en; input [3:0] a; output [1:0] y; reg [1:0] y; always@(a,en) begin if(en==0) y=2'bXX; else case(a) 4'b0001:y=2'b00; 4'b0010:y=2'b01; 4'b0100:y=2'b10; 4'b1000:y=2'b11; default y=2'bZZ; endcase end endmodule Output Graph:
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8:3 Encoder with Priority Aim: To realize 8:3encoder combinational Block using HDL Description. Block Diagram: en
x(7),x(6),x(5),..x(0)
8:3Encoder
y(2) y(1) y(0)
Truth Table: en 1 1 1 1 1 1 1 1 1 0 x(7) x(6) x(5) x(4) x(3) x(2) x(1) x(0) y(2) y(1) y(0) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 X 0 0 1 0 0 0 0 0 1 X X 0 1 0 0 0 0 0 1 X X X 0 1 1 0 0 0 1 X X X X 1 0 0 0 0 1 X X X X X 1 0 1 0 1 X X X X X X 1 1 0 1 X X X X X X X 1 1 1 Others Z Z Z X X X X X X X X X X X
VHDL Description: entity PE is Port ( e : in STD_LOGIC; x : in STD_LOGIC_VECTOR (07 downto 0); y : out STD_LOGIC_VECTOR (02 downto 0)); end PE; architecture Behavioral of PE is begin y<="111" when x(7)='1' and e='1' else "110" when x(6)='1' and e='1' else "101" when x(5)='1' and e='1' else "100" when x(4)='1' and e='1' else "011" when x(3)='1' and e='1' else "010" when x(2)='1' and e='1' else "001" when x(1)='1' and e='1' else "000" when x(0)='1' and e='1' else "ZZZ"; end Behavioral;
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Verilog Description: module enc(x, y, en); input [7:0] x; output [2:0] y; input en; reg [2:0] y; always @(x) begin
if (en==1) begin casex (x) 8'b1XXXXXXX : y=3'd7; 8'b01XXXXXX : y=3'd6; 8'b001XXXXX : y=3'd5; 8'b0001XXXX : y=3'd4; 8'b00001XXX : y=3'd3; 8'b000001XX : y=3'd2; 8'b0000001X : y=3'd1; 8'b00000001 : y=3'd0; default: y=3'bZZZ; endcase end else begin y=3'bXXX; end
endmodule
end
Output Graph:
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2-4 Decoder Aim: To realize 2-4 decoder combinational Block using HDL Description. Block Diagram:
a(1),a(0)
2:4 decoder
y(3),y(2),y(1),y(0)
Truth Table: a(1) 0 0 1 1 VHDL Description: entity decoder is Port ( a : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0)); end decoder; architecture Behavioral of decoder is begin process(a) begin case a is when "00"=>y<="0001"; when "01"=>y<="0010"; when "10"=>y<="0100"; when others => y<="1000"; end case; end process; end Behavioral; Verilog Description: module decode(a, y); input [1:0] a; output [3:0] y; reg [3:0]y; always @ (a) begin
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a(0) 0 1 0 1
y(3) 0 0 0 1
y(2) 0 0 1 0
y(1) 0 1 0 0
y(0) 1 0 0 0
HDL LAB MANUAL
case(a) 2'b00: y=4'b0001; 2'b01: y=4'b0010; 2'b10: y=4'b0100; 2'b11: y=4'b1000; default y=4'b0000; endcase end endmodule Output Graph:
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Date: ____________ TEST no: ____ Comments if any:
Marks Allotment:
Conduction: Write up: Viva:
Lab coordinator: Lab coordinator:
Student Sign:
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5. 8:1 Multiplexer Aim: To realize 8:1Multiplexer combinational Circuit using HDL Description. Block Diagram:
3 s(2),s(1),s(0) select lines a(7),a(6),,a(0) input lines 8
8:1 multiplexer
y, output line
Truth Table: s(2) 0 0 0 0 1 1 1 1 VHDL Description: entity Muxx is Port ( a : in STD_LOGIC_VECTOR (7 downto 0); s : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC); end Muxx; architecture Behavioral of Muxx is begin process(a,s) begin case s is when "000" => when "001" => when "010" => when "011" => when "100" => when "101" => when "110" => s(1) 0 0 1 1 0 0 1 1 s(0) 0 1 0 1 0 1 0 1 y a(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7)
y<= y<= y<= y<= y<= y<= y<=
a(0); a(1); a(2); a(3); a(4); a(5); a(6);
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when others => y<= a(7); end case; end process; end Behavioral; Verilog Description: module muxx(a, s, y); input [7:0] a; input [2:0] s; output y; reg y; always @ (a or s) begin case (s) 3'd0:y=a[0]; 3'd1:y=a[1]; 3'd2:y=a[2]; 3'd3:y=a[3]; 3'd4:y=a[4]; 3'd5:y=a[5]; 3'd6:y=a[6]; default:y=a[7]; endcase end endmodule Output Graph:
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Lab coordinator : ______________________ Lab coordinator: _______________________ 6. 1:8 Demultipler Aim: To realize 8:1Multiplexer combinational Block using HDL Description. Block Diagram:
3 s(2),s(1),s(0) select lines
1:8 Demultiplexer
8 y(7),y(6),,y(0) output lines
a, input line
Truth Table: s(2) 0 0 0 0 1 1 1 1 VHDL Description:

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s(1) 0 0 1 1 0 0 1 1
s(0) 0 1 0 1 0 1 0 1
y(7) 0 0 0 0 0 0 0 a
y(6) 0 0 0 0 0 0 a 0
y(5) 0 0 0 0 0 a 0 0
y(4) 0 0 0 0 a 0 0 0
y(3) 0 0 0 a 0 0 0 0
y(2) 0 0 a 0 0 0 0 0
y(1) 0 a 0 0 0 0 0 0
y(0) a 0 0 0 0 0 0 0
HDL LAB MANUAL
entity Demux_8 is Port ( a : in STD_LOGIC; s : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0)); end Demux_8; architecture Behavioral of Demux_8 is begin process(a,s) begin y<="00000000"; case s is when 000 => y(0)<= a when 001 => y(1)<= a; when 010 => y(2)<= a; when 011 => y(3)<= a; when 100 => y(4)<= a; when 101 => y(5)<= a; when 110 => y(6) <= a ; when others => y(7) <= a ; end case; end process; end Behavioral; Verilog Description: module demuxx(a, s, y); input a; input [2:0] s; output [7:0] y; reg [7:0] y; always @ (a or s) begin y=8'b00000000; case (s) 3'd0:y[0] =a; 3'd1:y[1] =a; 3'd2:y[2] =a; 3'd3:y[3] =a; 3'd4:y[4] =a; 3'd5:y[5] =a; 3'd6:y[6] =a; default:y[7] =a; endcase end
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endmodule Outut Graph:
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Lab coordinator : ______________________ Lab coordinator: _______________________ ARITHMETIC LOGIC UNIT Aim: To realize an ALU using HDL Description. Block Diagram:
4 a(3)a(0)
en
b(3)..b(0) 4
4-bit ALU
y,output y(0),y(1),y(2),y(3)
4
opcode o(3),o(2),o(1),o(0)
4
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Truth Table: en 0 1 1 1 1 1 1 1 1 1 VHDL Description: entity alu1 is Port ( a,b,op : in std_logic_vector(3 downto 0); en : in std_logic; y : out std_logic_vector(3 downto 0)); end alu1; architecture Behavioral of alu1 is begin process(a,b,en,op) begin if(en='0') then y<="ZZZZ"; else case op is when"0001"=>y<=(a+b); when"0010"=>y<=(a-b); when"0011"=>y<=not a; when"0100"=>y<=(a(1 downto 0) * b(1 downto 0)); when"0101"=>y<=(a and b); when"0110"=>y<=(a or b); when"0111"=>y<=(a nand b); when"1000"=>y<=(a xor b); when others=>y<="XXXX"; end case; end if; end process; end Behavioral; Verilog Description:
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opcode XXXX 0001 0010 0011 0100 0101 0110 0111 1000 1001-1111
y ZZZZ a+b a-b not a {a(1),a(0)} * {b(1),b(0)} a and b a or b a nand b; a xor b XXXX
HDL LAB MANUAL
module alu1(a, b, en,opcode,result); input [3:0] a; input [3:0] b; input en; output [3:0] result; input [3:0] opcode; reg [3:0]result; always@(a or b or en or opcode) begin if (en == 0) result=4'bZZZZ; else case(opcode) 4'b0001:result=a+b; 4'b0010:result=a-b; 4'b0011:result=~a; 4'b0100:result=a[1:0]*b[1:0]; 4'b0101:result=a&b; 4'b0110:result=a|b; 4'b0111:result=~(a & b); 4'b1000:result=a^b; default:result=4'XXXX; endcase end endmodule
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Output Graph:
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Lab coordinator : ______________________ Lab coordinator: _______________________ Date: ____________ Review no: ___
Marks Allotment: Attendance: Conduction: Write up: Viva:

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FULL ADDER Aim: To write a HDL code to describe the functions of a Full Adder Using three modeling styles. Logic Diagram:
a b cin
a b a cin b cin C
Block Diagram:
a b cin
Full Adder
carry sum
Truth Table: a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 i) VHDL Description: entity fa1 is Port (a,b,cin : in STD_LOGIC;

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cin 0 1 0 1 0 1 0 1
sum 0 1 1 0 1 0 0 1
carry 0 0 0 1 0 1 1 1
Data flow Model
HDL LAB MANUAL
s,cout : out STD_LOGIC); end fa1; architecture Behavioral of fa1 is begin s<= a xor b xorcin; cout<=(a and b) or (a and cin) or (b and cin); end Behavioral; Verilog Description: module adder(a,b,cin,s,c); input a,b,cin; output s,c; assign s=a^b^cin; assign c=(a&b)|(b&cin)|(cin&a); endmodule ii) VHDL Description: entity threemodel is Port ( a,b,cin : in std_logic; s,c : out std_logic); end threemodel; architecture Behavioral of threemodel is begin process(a,b,cin) begin if(a='0'and b='0'and cin='0')then s <='0'; c <='0'; elsif(a='0'and b='0'and cin='1')then s<='1';c<='0'; elsif(a='0'and b='1'and cin='0')then s<='1';c<='0'; elsif(a='0'and b='1'and cin='1')then s<='0';c<='1'; elsif(a='1'and b='0'and cin='0')then s<='1';c<='0'; elsif(a='1'and b='0'and cin='1')then s<='0';c<='1'; elsif(a='1'and b='1'and cin='0')then s<='0';c<='1'; else s<='1';c<='1'; end if; end process; end Behavioral; Verilog Description: module behvmdle(a,b,cin,s,c); input a; input b; input cin; output s; output c;
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Behavioral Model
HDL LAB MANUAL
regs,c; always @(a or b or cin) begin case({a,b,cin}) 3'b000:{s,c}= 2'b00; 3'b001:{s,c}= 2'b10; 3'b010:{s,c}= 2'b10; 3'b011:{s,c}= 2'b01; 3'b100:{s,c}= 2'b10; 3'b101:{s,c}= 2'b01; 3'b110:{s,c}= 2'b01; 3'b111:{s,c}= 2'b11; endcase end endmodule iii) VHDL Description: entity fullstru is Port ( a,b,cin : in std_logic; sum,carry : out std_logic); end fullstru; architecture mixdmod of fullstru is signal c1,c2,c3:std_logic; component xor_3 is port(x,y,z:instd_logic; u:out std_logic); end component; component and_2 is port(l,m:instd_logic; n:out std_logic); end component; component or_3 is port(p,q,r:instd_logic; s:out std_logic); end component; begin X1: xor_3 port map ( a, b,cin,sum); A1: and_2 port map (a, b,c1); A2: and_2 port map (b,cin,c2); A3: and_2 port map (a,cin,c3); O1: or_3 port map (c1,c2,c3,carry); end mixdmod;
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Mixed Model
HDL LAB MANUAL
module xor_3(x,y,z, u); input x,y,z; output u; assign u= x^y^z; endmodule module and_2(l,m,n); input l,m; output n; and (n,l,m); endmodule module or_3(p,q,r,s); input p,q,r; output s; or(s,p,q,r); endmodule Output Graph:
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COUNTERS
Aim: To write a HDL code to describe the functions of Different types of Counters. Truth Table: Res X 0 0 0 0 0 0 0 0 0 1 X clk Q Binary Counter 0 Asyn Syn 0000 0001 0010 0011 0100 0101 . . 1111 0000 X clk Q Mod N Counter 0 Asyn Syn 0000 0001 0010 0011 0100 0101 . . N-1 0000 X clk Q BCD counter 0 Asyn Syn 0000 0001 0010 0011 0100 0101 . . 1001 0000
For UP counters take *** as x:=x+'1'; and ** as x=stp or x<strt Any Sequence Parameters BCD Counter Binary Counter Counter [N>M] Strt 0000 0000 M Stp Variable/ reg
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1010 0000
0000 0000
N+1 M
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Initialisation For DOWN counters take *** as x:=x-'1'; and ** as x=stp or x>strt Any Sequence Parameters BCD Counter Binary Counter Counter [N>M] 1001 1111 N Strt Stp Variable/ reg Initialisation 1111 1000 1111 0000 M-1 N
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Synchronous Counter VHDL Description: entity cntr is Port ( clk,rst : in STD_LOGIC; strt,stp : in STD_LOGIC_VECTOR (3 downto 0); q : out STD_LOGIC_VECTOR (3 downto 0)); end cntr; architecture Behavioral of cntr is begin process(clk,rst) variable x:std_logic_vector(3 downto 0):="1110"; begin if (rising_edge(clk)) then if (rst='1')then x:="0000"; else x:= x+'1'; ---------*** if (x=stp or x<strt) then --------** x:= strt; end if; end if; end if; q<=x; end process; end Behavioral;
Verilog Description: module cntr(clk,rst, strt,stp, q); input clk,rst; input [3:0] strt,stp; output [3:0] q; reg q=4'b1100; always @(posedge clk) begin if (rst==1) q=4'd0; else begin q=q+1;//-----------------*** if(q==stp | q<strt) q=strt; // --------** end end
endmodule
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Asynchronous Counter VHDL Description: entity cntr is Port ( clk,rst : in STD_LOGIC; strt,stp : in STD_LOGIC_VECTOR (3 downto 0); q : out STD_LOGIC_VECTOR (3 downto 0)); end cntr; architecture Behavioral of cntr is begin process(clk,rst) variable x:std_logic_vector(3 downto 0):="1110"; begin if (rst='1')then x:="0000"; elsif (rising_edge(clk)) then x:= x+'1'; ---------*** if (x=stp or x<strt) then --------** end if; end if; q<=x; end process; end Behavioral; Verilog Description: module cntr(clk,rst, strt,stp, q); input clk,rst; input [3:0] strt,stp; output [3:0] q; reg q=4'b1100; always @(posedge clk,posedge rst) begin if (rst==1) q=4'd0; else begin q=q+1;//-----------------*** if(q==stp | q<strt) q=strt; // --------** end end endmodule
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Output Graph:
Reset is synchronous with clk
Reset is Asynchronous with clk
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Lab coordinator : ______________________ Lab coordinator: _______________________ FLIP FLOPS T FLIP FLOP with Synchronous Reset-Preset Aim:Towrite a HDL code to describe the functions of a T Flip flop. Truth Table:
clk 0 Res X 1 0 0 0 Pre X X 1 0 0 T X X X 0 1 Q 0 1 0 Toggle Qb 1 0 1
Previous
VHDL Description: entity tff is Port ( clk,t,res,pre : in STD_LOGIC; q,qb : out STD_LOGIC); end tff; architecture Behavioral of tff is begin process(clk) variable qv:STD_LOGIC:='0'; begin if(rising_edge(clk)) then if(res='1') then qv:='0'; elsif(pre='1') then qv:='1'; elsif(t='1') then qv:=not qv; end if; end if; q<=qv; qb<=not qv;
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end process; end Behavioral; Verilog Description: module tff(t,clk,res,pre,q,qb); input t,clk,res,pre; output q,qb; reg q; initial q=1'b0; always@(posedge (clk)) begin if(res==1) q=1'b0; else if(pre==1) q=1'b1; else if(t==0) q=t; else q=~q; end assign qb=~q; endmodule
Output Graph:
T FLIP FLOP with Asynchronous Reset-Preset Aim:Towrite a HDL code to describe the functions of a T Flip flop. Truth Table:
clk 0 X X Res 0 1 0 0 0 Pre 0 X 1 0 0 T X X X 0 1 Q 0 1 0 Toggle Qb 1 0 1
Previous
VHDL Description:
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entity tff_asy is Port ( t,res,pre,clk : in std_logic; q, qb : out std_logic); end tff_asy; architecture Behavioral of tff_asy is begin process(res,pre,clk) variableqv:std_logic:='0'; begin if (res='1')then qv:='0'; elsif(pre='1') then qv:='1'; elsif(rising_edge(clk))then if(t='0') then qv:=qv; else qv:= not qv; end if; end if; q<=qv; qb<=not qv; end process; end Behavioral;
Verilog Description:
module tff(t,clk,res,pre,q,qb); input t,clk,res,pre; output q,qb; reg q; initial q=1'b0; always@(posedge res,posedge pre,posedge (clk)) begin if(res==1) q=1'b0; else if(pre==1) q=1'b1; else if(t==0) q=t; else q=~q; end assign qb= ~q; endmodule
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Lab coordinator : ______________________ Lab coordinator: _______________________ D FLIP FLOP with Synchronous Reset-Preset Aim: To write a HDL code to describe the functions of a D Flip flop. Truth Table:
clk 0 Res X 1 0 0 0 Pre X X 1 0 0 D X X X 0 1 Q 0 1 0 1 Qb 1 0 1 0
Previous
VHDL Description: entity dff is Port ( clk,res,pre,d : in std_logic; q,qb : out std_logic); end dff;
architecture Behavioral of dff is begin process(clk) variableqv: std_logic:='0'; begin if(rising_edge(clk)) then if(res='1') then qv:='0'; elsif(pre='1') then qv:='1'; else qv:=d; end if; end if; qb<=not qv;
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q<= qv; end process; end Behavioral; Verilog Description: module df(d,clk,res,pre,q,qb); input d,clk,res,pre; output q,qb; reg q; initial q=1'b0; always@(posedge (clk)) begin if(res==1) q=1'b0; else if(pre==1) q=1'b1; else q=d; end assign qb=~q; endmodule
Output Graph:
D FLIP FLOP with Asynchronous Reset-Preset Aim:Towrite a HDL code to describe the functions of a D Flip flop. Truth Table:
clk 0 X X Res 0 1 0 0 Pre 0 X 1 0 D X X X 0 Q 0 1 0 Qb 1 0 1
Previous
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VHDL Description: entity dff is Port ( clk,res,pre,d : in std_logic; q,qb : out std_logic); end dff; architecture Behavioral of dff is begin process(clk,res,pre) variableqs:std_logic:='0'; begin if(res='1') then qs:='0'; elsif(pre='1') then qs:='1'; elsif(rising_edge(clk)) then qs:=d; end if; q<=qs; qb<=not qs; end process; end Behavioral; Verilog Description: module df(d,clk,res,pre,q,qb); input d,clk,res,pre; output q,qb; reg q; initial q=1'b0; always@(posedge (clk),posedge res,posedge pre) begin if(res==1) q=1'b0; else if(pre==1) q=1'b1; else if(clk==1) q=d; end assign qb=~q; endmodule
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Lab coordinator : ______________________ Lab coordinator: _______________________ JK flip flops with Synchronous Reset-Preset Aim:Towrite a HDL code to describe the functions of a SR Flip flop. Truth Table:
clk 0 Res 0 1 0 0 0 0 0 Pre 0 X 1 0 0 0 0 J X X X 0 0 1 1 K X X X 0 1 0 1 Q 0 1 Qb 1 0
Previous
Previous 0 1 Toggle 1 0
VHDL Description: entity jksyff is Port ( clk,res,pre,j,k : in std_logic; q,qb : out std_logic); end jksyff; architecture Behavioral of jksyff is begin process(clk) variableqs:std_logic:='0'; begin if(rising_edge(clk)) then if(res='1') then qs:='0'; elsif(pre='1') then qs:='1'; elsif(j='0' and k='1')then qs:='0';
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elsif(j='1' and k='0')then qs:='1'; elsif(j='1' and k='1')then qs:=not qs; else qs:=qs; end if; end if; q<=qs; qb<= not qs; end process; end Behavioral;
Verilog Description: module gjkff(j,k,clk,res,pre,q,qb); input j,k,clk,res,pre; output q,qb; reg q; initial q=1'b0; always@(posedge (clk)) begin if(res==1) q=1'b0; else if(pre==1)q=1'b1; else if(j==0 & k==1)q=1'b0; else if (j==1 & k==0)q=1'b1; else if (j==1 & k==1)q=~q; else q=q; end assign qb=~q; endmodule Output Graph:
JK flip flops with asynchronous Reset-Preset
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Aim:Towrite a HDL code to describe the functions of a SR Flip flop. Truth Table:
clk 0 X X Res 0 1 0 0 0 0 0 Pre 0 X 1 0 0 0 0 J X X X 0 0 1 1 K X X X 0 1 0 1 Q 0 1 Qb 1 0
Previous
Previous 0 1 Toggle 1 0
VHDL Description: entity jkasyff is Port ( clk,res,pre,j,k : in std_logic; q,qb : out std_logic); end jkasyff; architecture Behavioral of jkasyff is begin process(clk,res,pre) variableqs:std_logic:='0'; begin if (res='1')then qs:='0'; elsif(pre='1') then qs:='1'; elsif(rising_edge(clk))then if(j='0' and k='1')then qs:='0'; elsif(j='1' and k='0')then qs:='1'; elsif(j='1' and k='1')then qs:= not qs; end if; end if; q<=qs; qb<= not qs; end process; end Behavioral; Verilog Description: module asjkff(j,k,clk,res,pre,q,qb); input j,k,clk,res,pre; output q,qb; reg q; initial q=1'b0;
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always@(posedge (clk), posedge pre,posedge res) begin if(res==1) q=1'b0; else if(pre==1)q=1'b1; else if(j==0 & k==1)q=1'b0; else if (j==1 & k==0)q=1'b1; else if (j==1 & k==1)q=~q; else q=q; end assign qb=~q; endmodule
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Lab coordinator : ______________________ Lab coordinator: _______________________ SR flip flops with Synchronous Reset-Preset Aim:Towrite a HDL code to describe the functions of a SR Flip flop. Truth Table:
clk 0 Res X 1 0 0 0 0 0 Pre X X 1 0 0 0 0 S X X X 0 0 1 1 R X X X 0 1 0 1 Q 0 1 Qb
Previous 1 0
Previous 0 1 1 0
Undetermined
VHDL Description: entity sr_flipflop is Port ( clk,res,pre,s,r : in std_logic; q,qb : out std_logic); end sr_flipflop; architecture Behavioral of sr_flipflop is begin process(clk) variableqs,qbs:std_logic:='0'; begin if(rising_edge(clk)) then if(res='1') then qs:='0';qbs:= '1'; elsif(pre='1') then qs:='1';qbs:= '0';
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elsif(s='0' and r='0')then qs:=qs;qbs:=qbs; elsif(s='0' and r='1')then qs:='0';qbs:= '1'; elsif(s='1' and r='0')then qs:='1';qbs:= '0'; else qs:='1';qbs:='1'; end if; end if; q<=qs; qb<=qbs; end process; end Behavioral; Verilog Description: module srff(s,r,clk,res,pre,q,qb); input s,r,clk,res,pre; output q,qb; regq,qb; initial q=1'b0; always@(posedge clk) begin if(res==1) begin q=1'b0;qb=~q; end else if(pre==1) begin q=1'b1;qb=~q; end else if(s==0 & r==0) begin q=q;qb=~q; end else if (s==0 & r==1) begin q=1'b0;qb=~q; end else if (s==1 && r==0) begin q=1'b1;qb=~q; end else begin q=1'b1;qb=1'b1; end end endmodule
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Output Graph:
SR flip flops with Asynchronous Reset-Preset Aim:Towrite a HDL code to describe the functions of a SR Flip flop. Truth Table:
clk 0 X X Res 0 1 0 0 0 0 0 Pre 0 X 1 0 0 0 0 S X X X 0 0 1 1 R X X X 0 1 0 1 Q 0 1 Qb
Previous 1 0
Previous 0 1 1 0
Undetermined
VHDL Description: entity sr_flipflop is Port ( clk,res,pre,s,r : in std_logic; q,qb : out std_logic); end sr_flipflop; architecture Behavioral of sr_flipflop is begin process(res,pre,clk) signal qs,qbs:std_logic:='0'; begin if (res='1')then qs:='0'; qbs:='1';
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elsif(pre='1') then qs:='1'; qbs:='0'; elsif(rising_edge(clk))then if(s='0' and r='0')then qs:=qs; qbs:=qbs; elsif(s='0' and r='1')then qs:='0'; qbs:='1'; elsif(s='1' and r='1')then qs:= '1';qbs:='1'; end if; end if; q<=qs; qb<=qbs; end process; end Behavioral;
Verilog Description: module srff(s,r,clk,res,pre,q,qb); input s,r,clk,res,pre; output q,qb; regq,qb; initial q=1'b0; always@(posedge clk,posedge pre,posedge res) begin if(res==1) begin q=1'b0;qb=~q; end else if(pre==1) begin q=1'b1;qb=~q; end else if(s==0 & r==0) begin q=q;qb=~q; end else if (s==0 & r==1) begin q=1'b0;qb=~q; end else if (s==1 && r==0) begin q=1'b1;qb=~q; end else begin q=1'b1;qb=1'b1; end end endmodule
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Lab coordinator : ______________________ Lab coordinator: _______________________ Delay program for Flip-flop and Counters
VHDL
entity tff is Port (clk,res,pre,t : in std_logic; q : inoutstd_logic; qb : out std_logic); end tff; architecture Behavioral of tff is
signal div:std_logic_vector(21 downto 0):= 0000000000000000000000; signal clkd: std_logic;

begin
process(clk) begin if(raising_edge(clk)) then div<=div+'1'; end if; end process; clkd<=div(21);
process(clkd) begin if(raising_edge(clkd)) then . end Behavioral;
Verilog
module tff(t,clk,res,pre,q,qb); input t,clk,res,pre; output q,qb;
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reg q=0;
wire clkd; reg [21:0] div; initial div = 22 d0; always @(posedge(clk)) begin div= div+1; end assign clkd<=div[21];
always@(posedge (clkd)) begin if(res==1) q=1'b0; .. ... endmodule Date: ____________ Review no: ___
Marks Allotment: Attendance: Conduction:
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Write up: Viva:
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Date: ____________ TEST no: ____ Comments if any:
Marks Allotment:
Student Sign:
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PART-B
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DC MOTOR Aim:To run DC motor using VHDL code. VHDL Description: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dcmotor is Port ( str,dir,clk : in std_logic; fx : out std_logic; out1 : out std_logic_vector(1 downto 0)); end dcmotor; architecture Behavioral of dcmotor is begin process(clk) begin if(rising_edge (clk))then if (str='0')then out1<="00"; elsif(str='1'and dir='1')then out1<="10"; fx<='1'; elsif(str='1'and dir='0')then out1<="01"; fx<='1'; end if; end if; end process; end Behavioral;
NET LIST: NET NET NET NET NET NET "dir" LOC = "p43" ; "fx" LOC = "p50" ; "out1<0>" LOC = "p54"; "out1<1>" LOC = "p56"; "str" LOC = "p44" ; "clk" LOC = "p18" ;
RELAY Aim:To run a relay using VHDL code. VHDL Description: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity relay is Port ( sw : in std_logic; r1 : out std_logic); end relay; architecture Behavioral of relay is begin r1<=sw;
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NET LIST: NET "r1" LOC = "p120" ; NET "sw" LOC = "p86" ;
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end Behavioral; STEPPER MOTOR Aim:To run Stepper motor using VHDL code. VHDL Description:
entity stepper is Port ( clk,res,dir : in std_logic; out_abcd : out std_logic_vector(3 downto 0)); end stepper; architecture Behavioral of stepper is signal div:std_logic_vector(21 downto 0); type state_type is (s0,s1,s2,s3); signal state: state_type; signal clka: std_logic; begin process(clk,res) begin if(res='1') then div<="0000000000000000000000"; elsif (clk'event and clk='1') then div<=div+'1'; end if; end process; clka<=div(21); process (clka,res) begin if(res='1') then state<=s0; elsif(clka 'event and clka='1') then if(dir='0') then case state is when s0=> state<=s1; when s1=> state<=s2; when s2=> state<=s3; when s3=> state<=s0; when others => null; end case; elsif(dir='1')then case state is when s3=> state<=s2; when s2=> state<=s1; when s1=> state<=s0; when s0=> state<=s3; when others => null; end case; end if; end if; end process; with state select out_abcd<="0110" when s0, "1010" when s1, "1001" when s2, "0101" when s3;
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NET LIST: NET NET NET NET NET NET NET "dir" LOC = "p43" ; "out_abcd<0>" LOC "out_abcd<1>" LOC "out_abcd<2>" LOC "out_abcd<3>" LOC "res" LOC = "p86" ; "clk" LOC = "p18" ; = = = = "p62" "p65" "p60" "p64" ; ; ; ;
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end Behavioral;
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Date: ____________ Review no: ___
Marks Allotment: Attendance: Conduction: Write up:
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Viva:
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DAC Aim: To Write HDL Code To Generate different waveforms (Square, Triangle, Ramp etc.,) using DAC change the frequency and amplitude. VHDL Description To Generate SQUARE WAVE: entity squarewg is Port ( clk,rst : in std_logic; dac : out std_logic_vector(7 downto 0)); end squarewg; architecture Behavioral of squarewg is signal clkd:std_logic_vector(3 downto0); signal cnt:std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd+'1'; end if; end process; process(clkd(3),rst) begin if rst='1' then dac<="00000000"; elsifrising_edge (clkd(3)) then cnt<=cnt+1; if cnt< 128 then dac<="00000000"; else dac<="11111111"; end if; end if; end process; end Behavioral; Wave form:
Frequency, F= _________ Hz Voltage V=______ V
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VHDL Description to generate TRIANGULAR WAVE entity triwve is Port ( clk,rst : in std_logic; dac : out std_logic_vector(7 downto 0)); end triwve; architecture Behavioral of triwve is signal clkd:std_logic_vector(3 downto0); signal cnt:std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd+'1'; end if; end process; process(clkd(3),rst) begin if rst='1' then dac<="00000000"; elsifrising_edge (clkd(3)) then cnt<=cnt+1; if cnt< 128 then dac<= cnt else dac<= not cnt; end if; end if; end process; end Behavioral; Wave form:
Frequency, F= _________ Hz Voltage V=______ V VHDL Description To GenerateNEGATIVE RAMP: entity negrmp is Port ( clk,rst : in std_logic; dac : out std_logic_vector(7 downto 0)); end negrmp; architecture Behavioral of negrmp is signal clkd:std_logic_vector(3 downto0);
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signal cnt:std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd+'1'; end if; end process; process(clkd(3),rst) begin if rst='1' then dac<="00000000"; elsifrising_edge (clkd(3)) then cnt<=cnt+1; dac<= not cnt end if; end process; end Behavioral; Wave form:
Frequency, F= _________ Hz Voltage V=______ V VHDL Description to generate POSITIVE RAMP: entity posrmp is Port ( clk,rst : in std_logic; dac : out std_logic_vector(7 downto 0)); end posrmp; architecture Behavioral of posrmp is signal clkd:std_logic_vector(3 downto0); signal cnt:std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd+'1'; end if; end process; process(clkd(3),rst) begin if rst='1' then dac<="00000000"; elsifrising_edge (clkd(3)) then cnt<=cnt+1; dac<= cnt
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end process; end Behavioral; Wave form:
end if;
Frequency, F= _________ Hz Voltage V=______ V
NET LIST FOR ALL DAC PGMS: NET NET NET NET NET NET NET NET NET NET "dac<0>" LOC = "p38" "dac<1>" LOC = "p40" "dac<2>" LOC = "p41" "dac<3>" LOC = "p42" "dac<4>" LOC = "p43" "dac<5>" LOC = "p44" "dac<6>" LOC = "p46" "dac<7>" LOC = "p47" "rst" LOC = "p86" ; "clk" LOC = "p18 ; ; ; ; ; ; ; ;
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Lab coordinator : ______________________ Lab coordinator: _______________________ SEVEN SEGMENT DISPLAY Aim:ToWrite HDL code to display messages on the given seven segment display and LCD and accepting Hex key pad input data. VHDL Description: entity sev is Port ( clk,rst : in std_logic; row : out std_logic_vector(3 downto 0); col : in std_logic_vector(3 downto 0); en1 : out std_logic; en2 : out std_logic; en3 : out std_logic; en4 : out std_logic; en5 : out std_logic; en6 : out std_logic; seg_dis : out std_logic_vector(6 downto 0)); end sev; architecture Behavioral of sev is type state is (s0,s1,s2,s3); signal st:state:=s0; signal clkdiv:std_logic; signal col1,col2:std_logic_vector(3 downto 0); signal clk_div:std_logic_vector(15 downto 0); begin en1<='0';en2<='0';en3<='0'; en4<='0';en5<='0';en6<='0'; clkdiv<=clk_div(15); process(clk,rst) begin if rst<='0' then if(clk'event and clk='1') then clk_div<=clk_div+'1'; else
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null; end if; end if; end process; process(clkdiv) begin if(clkdiv'event and clkdiv='1') then --col1<=col; --col2<=col1; case st is when s0=>row<="1110" ; case col is when "1110"=>seg_dis<="0111111"; when "1101"=>seg_dis<="0000110"; when "1011"=>seg_dis<="1011011"; when "0111"=>seg_dis<="1001111"; when "1111"=>st<=s1; when others=> null; end case; when s1=>row<="1101"; case col is when "1110"=>seg_dis<="1100110"; when "1101"=>seg_dis<="1101101"; when "1011"=>seg_dis<="1111101"; when "0111"=>seg_dis<="0000111"; when "1111"=>st<=s2; when others=> null; end case; when s2=>row<="1011"; case col is when "1110"=>seg_dis<="1111111"; when "1101"=>seg_dis<="1101111"; when "1011"=>seg_dis<="1110111"; when "0111"=>seg_dis<="1111100"; when "1111"=>st<=s3; when others=> null; end case; when s3=> row<="0111"; case col is when "1110"=>seg_dis<="0111001"; when "1101"=>seg_dis<="1011110"; when "1011"=>seg_dis<="1111001"; when "0111"=>seg_dis<="1110001"; when "1111"=>st<=s0; when others=> null; end case; end case; end if; end process; end Behavioral;
NET LIST: NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "clk" LOC = "p18" ; "col<0>" LOC = "p43" ; "col<1>" LOC = "p44" ; "col<2>" LOC = "p41" ; "col<3>" LOC = "p42" ; "en1" LOC = "p56" ; "en2" LOC = "p54" ; "en3" LOC = "p51" ; "en4" LOC = "p50" ; "en5" LOC = "p40" ; "en6" LOC = "p49" ; "row<0>" LOC = "p30" ; "row<1>" LOC = "p39" ; "row<2>" LOC = "p28" ; "row<3>" LOC = "p31" ; "rst" LOC = "p86" ; "seg_dis<0>" LOC = "p62" "seg_dis<1>" LOC = "p65" "seg_dis<2>" LOC = "p60" "seg_dis<3>" LOC = "p64" "seg_dis<4>" LOC = "p59" "seg_dis<5>" LOC = "p63" "seg_dis<6>" LOC = "p57"
; ; ; ; ; ; ;
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Date: ____________ Final Internal Assessment Examination
Comments if any:
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Marks Allotment:
Student Sign:
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HDL Lab Manual For VTU

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PROCEDURE FOR EXECUTION OF HDL CODE IN XILINX 9.2i

02. To close the Existing Project. File Close Project

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Select the Test Bench Waveform

Click on NextNext Finish

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11. Double Click on Simulate behavioral model in the Process Window.

Select the first option (XST Default) and click OK.

14. Check the output using GPIO kit.

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AND Truth Table:

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endmodule Output Graph:

Date: ____________ Observation

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Truth Table: b(3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

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Date: ____________ Observation

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Lab coordinator : ______________________ Lab coordinator: _______________________

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Date: ____________ Observation

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Lab coordinator : ______________________ Lab coordinator: _______________________

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Date: ____________ Review no: ___

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a(3) a(2) a(1) a(0) en 4:2Encoder y(1) y(0)

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Date: ____________ Observation

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Lab coordinator : ______________________ Lab coordinator: _______________________

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y(2) y(1) y(0)

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Date: ____________ Observation

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Lab coordinator : ______________________ Lab coordinator: _______________________

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Date: ____________ Observation

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Lab coordinator : ______________________ Lab coordinator: _______________________

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Date: ____________ TEST no: ____ Comments if any:

Conduction: Write up: Viva:

Lab coordinator: Lab coordinator:

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3 s(2),s(1),s(0) select lines a(7),a(6),,a(0) input lines 8

y<= y<= y<= y<= y<= y<= y<=

a(0); a(1); a(2); a(3); a(4); a(5); a(6);

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Date: ____________ Observation

Lab coordinator : Lab coordinator: _

Lab coordinator : Lab coordinator: _

Date: __________ Review no: _

Lab coordinator : Lab coordinator: _

Lab coordinator : Lab coordinator: _

Lab coordinator : Lab coordinator: _

Date: ________ TEST no: Comments if any:

Lab coordinator : Lab coordinator: _

Lab coordinator : Lab coordinator: _