A Current Control Implementation Based on a Clamping One-cycle Control Strategy

Alberto Soto-Lock, Edison R. da Silva, C. B. Jacobina

Electrical Engineering Dept. Universidade Federal de Campina Grande - LEIAM Campina Grande, Brazil alberto.lock@ee.ufcg.edu.br, edison@dee.ufcg.edu.br Abstract Application of One-cycle Control (OCC) technique for power factor control in three phase boost rectifiers has been successful. This includes operation with
one phase of the converter clamped reducing switching losses. It features great simplicity, high performance, and excellent stability. In addition, the Hybrid PWM (HPWM) technique

Malik E. Elbuluk
Electrical Engineering Dept. University of Akron Akron, USA melbuluk@uakron.edu the use of an injected zero-sequence signal in triangle comparison PWM initiated the research on Discontinuous PWM, DPWM. Different zero-sequence signals (VNO in Fig. 1) [5], [6] lead to different discontinuous PWM modulators. The addition of adequate discontinuous zero-sequence signals made possible not only to increase in 15,5% the fundamental of the line-to-line but also clamping each pole voltage during 60 degrees. The use of this technique was applied to Space Vector Modulation, SVPWM, but this involves a number of mathematical and analytical operations [7]. Correlation between SVPWM and triangle comparison PWM gave rise to a new algorithm suitable for analog and digital implementation, that is, the Hybrid PWM, HPWM [8] that keeps the features of both techniques. The proposed work relates HPWM with an OCC clamping technique, already considered as a generalized PWM method [9], combining simplicity of both of these PWM methods. Moreover, proposed OCC technique utilizes a lead lag compensator instead of conventional LPF as well as an input resistance controller [10] to improve dynamic response. Voltage grid sensors are not longer required with this method. A relationship between the proposed and the hysteresis with clamping techniques [3] is established. Simulation and DSP based experimental results validate the theoretical studies.

establishes a simple algebraic approach to generate Discontinuous PWM, DPWM, resulting in phase clamping. In previous works Clamping OCC is based on low pass filters (LPF) and utilizes a multiplexer circuit to clamp the phase currents. This paper combines the simplicity of both methods, introducing an OCC clamping technique with the help of the HPWM technique. Moreover, the proposed OCC technique utilizes a lead-lag compensator instead of conventional LPF as well as an input resistance controller to improve dynamic response. It also establishes a relationship between the proposed technique and a hysteresis current controller with clamping technique. Simulation and DSP based experimental results confirm the proposed approach. I. INTRODUCTION As it was pointed out in previous technical reports [1], [2] hysteresis current controllers give fast response, good accuracy and a kind of load parameters independence; however its very-wide operation-frequency and phaseswitching-interference random behavior are its two main drawbacks. One way to avoid these drawbacks was proposed by Malesani [3]. This method consists in alternate clamping of the converter phases during 60 degrees while the remaining currents are controlled with the help of a PLL which is used to synchronize phase currents. This reduces the number of times the switches are turned on and off. Although the method was originally designed for inverters, the method can be easily applied to a rectifier as that in Fig. 1. It will be here referred as hysteresis with clamping technique. On the other hand, One-cycle control (OCC) power-factor correction with clamping operation is a promising approach to eliminate harmonics, to improve the power factor and to reduce switching losses [4]. In addition,

Fig. 1. Power rectifier.

II. CONTROL SYSTEM DESCRIPTION The controller scheme proposed is shown in Fig. 2. Reference currents are modified by a simplified lead-lag

978-1-4244-8083-8/11/$26.00 2011 IEEE

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compensator. Aforementioned currents are built from normalized phase currents (via its peak amplitude) plus a zero sequence term which is generated by the upper block in Fig. 2, the Region selection and zero sequence signal Generator to be described in Section V. A bipolar triangular carrier A and an output resistance controller are utilized. So, a variable carrier amplitude is realized dividing A by output controller (A=V0, V0=VC1+VC2 in Fig.1). The objective of above compensator in this scheme is provoking small current delays, but keeping input current and voltage in phase. As the control goal of a controlled rectifier with Power Factor Correction is to achieve unity power factor, the impedance seen from the utility grid is a resistance. Then a dc link voltage controller (Re) is added to control the input resistance, that is, V0 (1)
I gs = Re D (t )

Fig.3. Two level controlled rectifier

Since in a controlled rectifier with unity power factor the phase currents should follow the phase voltages, the three-phase rectifier impedance seen from the grid side should be resistive [8] a resistance Re is emulated so then [vg ] = Re [igs ] . Then
(1 dan / K1 ) (1 2d a ) Vm V (1 dbn / K1 ) = 0 (1 2db ) R RS e (1 dcn / K1 ) (1 2dc )

(2)

Note that I gs is the input compensated current-vector (composed by the currents compensated by the lead-lag compensator) and D (t ) is the duty cycle vector. To generate the rectifier gating signals, the compensated input current must be compared to the right side of (1). Therefore, this side of the equation can be seen as the variable amplitude of the carrier. Although this controller has the same function as the conventional dc link controller [11], [12], the addition of the lead-lag compensator improves the system dynamic response, similarly to ZACE (zero average current error) control [10], [13]. III. CONTROL SYSTEM ANALYSIS BY OCC. Figure 3 shows an average model of the One Cycle Control for the controlled rectifier shown in Fig.1 [7].

since,
Vm = V0 RS K1 Re

(3)

In these equations, va, vb, vc are average phase voltages, ia, ib, ic are average phase currents, RS is the equivalent currentsensing resistor, K1 is a constant. Note that in (2), dan=2da, dbn=2db, dcn=2dc (see Fig.2) and K1 = 1. A three phase PFC controlled by OCC must satisfy (2) [11]. Since OCC technique uses the average value of the input grid voltage and phase currents [11], previous reported OCC works utilize low pass filters, LPF, to obtain them. Eventually they use a peak detector [11], [12]. In order to attenuate the delay the LPF would cause, a Lead-Lag compensator, F(s), has been added so that I g F (s) = I gs with (1 + s1 ) (4.a) F ( s) = G
(1 + s 2 ) (1 + s1 ) I gs = I g G (1 + s 2 )
(1 2d a ) V0 (1 2db ) Re (1 2d c )

(4.b)

Then, from (2) and (4)

igs =

(5)

where igs = L1 I gs , L1 is the inverse Laplace operator. Former equation which corresponds to (1) shows that, if compensated currents and duty cycle switches are given by vectors, driving pulses are generated when the compensated current equals the value of a triangular waveform with variable amplitude, accomplishing One Cycle Control. IV. HPWM ANALYTICAL EXPRESSIONS
Fig. 2. Proposed control scheme

{ }

According to [3] a zero sequence voltage must be added to modulating signals to generate non continuous reference signals given by

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va * = Van + vh vb * = Vbn + vh vc * = Vcn + vh

p = p S ; q = q S

(13)

(6)

vh is the zero sequence voltage

v h ( ) = [(1 2 ) + v max + (1 )v min ]

(7)

vmax = max{ Van ,Vbn ,Vcn }, vmin = min{Van ,Vbn ,Vcn }, Van, Vbn, Vcn are

normalized voltages, is a factor 0 1. To generate the discontinuous modulating waves, factor can be defined also as a square waveform varying from 0 to 1 for every Sn Sector shown in Fig.4 [8]. Particularly and 2 waveforms show in Fig.4 will be used in next section. Above mentioned sectors are defined as
n (n 1) 1, if < Sn = 6 6 0, otherwise

where , I , I * are the current error, the phase current, and the reference current, respectively; p and q are the non clamped phases, s the clamped one, (=d/dt); up, uq are the pole voltages, p, q are the line current errors, up*, uq* are the pole voltage references, us is the clamped pole voltage (us=V0/2, according to sector S), and 1 is a unity vector. This way, line current errors p, q must follow pole voltage references up*, uq*, see Fig. 4 (c). A simple solution to system above can be achieved by noting from general equation (11) that (r + L)( p s ) = u ps u * ps (14)
* (r + L)( q s ) = uqs uqs

where uAB = uA uB. From (12),

* u* p =u ps+ us;

(15)

(8)

* uq =u * qs+ us

where n=1,, 12; is the electrical angle (rad/s) synchronized to normalized voltage Van. From equations (7), (8) and Fig.4, the function vh can be written as 1 vmin , if = 0 (9) v h ( ) = = v if 1 , 1 max Notice that although simple former equation plays an important role to express hysteresis with clamping technique [3] equations as a function of the DPWM equations.

The solution given by (15) recursively means that the pole voltage references depend on the line voltage references plus a dc variable quantity (clamping of phase us), i.e. for S4-S9 (see Figs. 4b and 5a) the pole voltage references are given by the following equations (S4+S5):
* ua = V0 / 2 * * ub = u ba + V0 / 2 * * uc = u ca + V0 / 2

(16.a)

(S6+S7):
* * ua = uac V0 / 2 * * ub = ubc V0 / 2 * uc = V0 / 2

(16.b)

(S8+S9):
* * ua = u ab + V0 / 2 * ub = V0 / 2

(16.c)

Fig. 4. Definition of (a) 1 (b) 2 c) Normalized voltages Van, Vbn, Vcn and Sectors S1,..,S12

* * uc = u ab + V0 / 2

V. HYSTERESIS CURRENT CLAMPED SYSTEM DESCRIPTION The hysteresis with clamping technique system defined by Malesani consider equations (10) = I I *
* (r + L) = u u * (uO uO )1

Note from equation (16) that the provoked clamping is alternately positive and negative. Note also from this equation that pole voltage references do not depend on load parameters, as it was previously established [3]. A. Approximate Solution to Hysteresis with Clamping Technique Equations Pole voltage references can be approximately reproduced by using HPWM (see Fig. 5). In fact, if, as an example, the normalized voltage Van is added the function vh for =1/2, see (7), a modulating voltage v*0a is obtained:

(11) (12)

* up u* p = r p + L p ; uq uq = r q + L q

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V an + V bn + V

cn

= 0

(22)

(15) can be written as

u* p = Vps 1
* uq = Vqs 1

(23)

where Vp corresponds to

* u* p , Vq corresponds to u q . If VAB

=VA-VB , A, B = an, bn, cn or p, q, s, and considering (22),

u* p = V p Vs 1; u = Vq Vs 1
* q

(24)

If us (Vs) corresponds to umax (vmax), (24) takes the form (see Fig. 6a)
Fig. 5. (a) Van and 3 harmonic injection(b)Original method.(c)Approximate solution.
* v0 a = V an + v h ( ) = 0 , 5

(17)

Considering the digital representation of sectors defined in (8), the voltage vx0 (see Fig. 5a) can be written as
v x0 = (S1 + S (S
2 4

+ S
6

+ S 8 + S 9 + S 12 )
7

(18)

+ S

+ S

+ S

+ S 10 + S 11 )

Based on the fact that there are similarities between pieces of the waves v*0a and ua* in Figs. 5(a) and 5(b), it can be assumed that the new modulating voltage v*a is a linear combination of v*0a and ua*
* * * va (v 0 a , v x 0 ) = x1 v 0 a + x 2 v x 0

(19)

Fig. 6. Pole voltages (a) Original method (b) Solution 1 (c) Solution (2)

Despite the pole voltage reference does not conform a linear system, an approximate solution for (19) can be obtained taking some points on Figs. 5(a) and (b): y0=0, y1=0.5, y2=0.863, y3=0.0723. Then
* * va (0, vx 0 ) = 0.5; va (0.863, vx 0 ) = 0.0723

u* p = Vp Vs + 1
* uq = Vq Vs + 1

(25)

Similarly, if us (Vs) corresponds to umin (vmin), (24) takes the form

u* ; p =Vp Vs 1
* uq = Vq Vs 1

(20)

(26)

Solving the system equations (19), one obtains x1=0.663, x2=0.5. Therefore

v (v , vx 0 ) = 0.663v + 0.5 vx 0
v
* 0g

* g

* 0g

* 0g

(21)

Note from (16) that (25) and (26) are present alternately for each sector of Fig.4. So, there exist two solutions namely 1 and 2: Solution 1: Considering a balanced system that satisfies (22), when us (Vs) corresponds to umax (vmax), (25) can be written as u* p =V p +V p +V q +1 (27) * uq =Vq +Vp +Vq +1

= Vgn + vh ( ) =0 ,5

B. Exact Solutions for Hysteresis with Clamping Technique An exactly way to solve the system of equations above consists in to express the pole voltages as a function of an arbitrary balanced three phase system. Then, if

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Assuming Vq = vmin, Vp= vmid = -(vmax+vmin), and as vh () =0.5 = 0.5vmid (27) becomes
u* p = Vp + vh () =0.5 + vmin + 1 u = Vq + vh () =0.5 + vmin +1
* q

VI. HPWM STRATEGY APPLIED TO OCC HPWM strategy above can be applied to OCC, replacing voltage references vg* by reference currents Ig*, and voltages Vgn by the normalized currents Ign. Then
Ig* = vg * R1 ; I gn = v gn R2

(28)

(35)

Since in a normalized system the maximum amplitude is 1, phase voltages are clamp to this value. In addition, substituting (28) into (9),
u* p =Vp + vh () =0.5 vh () =0 +1
* uq =Vq + vh () =0.5 vh() =0 +1

(29)

R1 and R2 are constants, representing the input resistance in fig. 2. Since the One Cycle Controller does not use any input voltage sensor, a zero current sequence function ih can be defined as [14]
ih ( ) = [(1 2) + imax + (1 )imin ]
(36)

Similarly, when us (Vs) corresponds to umin (vmin), and then from (26), (17), (18) and Fig. 5(b) u* p =V p + vh() =0.5 vh() =1 1 u =Vq + vh() =0.5vh() =1 1
* q
* u* p = v0 p vh ( 2) + vx 0 * * uq = v0 q vh ( 2) + vx 0

where imax = max {I an , I bn , I cn }, imin = min {I an , I bn , I cn } and is a factor 0 1. Then (6) takes the form
I a * = I an + ih Ib * = Ibn + ih I c * = I cn + ih

(30)

(37)

(31)

* 0g

= Vgn + vh ( ) = 0,5

g = p, q, s. Fig. 5(b) illustrates this equation, using a scale 1:0.625 to show it as a normalized voltage. Solution 2: Note that (25), when us (Vs) corresponds to umax (vmax), and considering (9), can be expressed as
u* p =Vp + vh () =1 +1
* uq =Vq + vh() =1 +1

The Region selection and zero sequence signal generator block in Figs. 2 and 7, generates the normalized input phase currents, selects the Sn sectors (n=1,..,12) according to (8), synchronizing with the normalized current Ian , generates the factor according to (36), and the zero current sequence function ih according to (35)-(37). The block for transformation abc/ and /dq includes the following equations:
2 1 I = [ I (I + I )] 3 a 2 b c I = 3 ( Ib I c ) 3

(38.a)

(32)

For (26), when us (Vs) corresponds to umin (vmin), it is obtained likewise

u* p =Vp +vh () =0 1
* uq =Vq +vh() =0 1

= arctn ( )
I d = I Cos I Sin I q = I Sin + I Cos

I I

(38.b) (39)

(33)

Note that substituting (38) into (39) results in

I d = 0 2 2 I q = I + I

Then, from (18) and Fig. 6(a), (32) and (33) can be expressed as
u* p = V p + vh ( 1) + vx 0
* uq = Vq + vh ( 1) + vx 0

(40)

(34)

Fig. 6 illustrates this equation. Note from that figure that the curves match.

From this, as the HPWM original method utilizes normalized magnitudes [8] to generate the modulating waves, the aforementioned currents can be obtained dividing the phase currents by Iq. Moreover, as it can be observed from (35)-(40) neither the homopolar current ih,

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nor the electrical angle depend on the phase voltages, since the HPWM original calculations can now be performed as a function of phase currents. Therefore, any of the direct information on grid voltage is necessary and phase voltage sensors could be neglected. This agrees with the assertion given in Section I, which is not a feature of previous reported works [11], [12].

show the voltage and current waveforms for solution 1 and 2, also discussed in that section. Note, that these experimental results confirm the slightly difference observed in the simulation results for the modulating wave inside Sectors S2 and. Note also, the almost unity power factor obtained in experimental and simulation results.

Fig.8. Current Iq (40), at the top (2A/div), angle (38.b) from the block diagram in Fig. 7 (middle), and current in phase a (bottom, 0.5A/div). Hor: 15ms/div Fig.7. Block diagram Region selection and zero sequence signal generator

VII. SIMULATION AND EXPERIMENTAL RESULTS Simulation results are presented in Figs. 3, 4 and 5 using PSCAD/EMTDC [15][16]. Also, simulation results for the rectifier shown in Fig.1 are presented from Figs. 8 to 11. Fig. 8 shows Iq current and angle for (38), (39) and (40). As angle is synchronized to phase a current, it allows an easy identification of Sn sectors according to (8). Figs. 9 to 11 show the grid voltage, the phase a current, and its corresponding modulating wave for all studied cases. Note that for solutions 1 and 2 (Figs. 9 and 10), the modulating waves are exactly the same while for the approximate solution in Fig. 9 the modulating wave is slightly different inside Sectors S2 and S3. DSP-TMS3020F2812 based experimental results are given from Fig. 12 to Fig. 15, for the converter circuit shown in Fig. 1, in which L=2 mH, C1=C2=2200 uF, f=60 Hz, fS=15 kHz, and DC link voltage 105 V. In the experimental results in Fig. 12 the system was applied to control an induction motor of 1 HP. This figure shows Iq and behavior of angle with respect to phase a current even in noisiy environments. Comparing to corresponding simulation result in Fig. 8, it can be observed that the angle and current behaviors are approximately the same. Figs. 1315 are experimental results comparing the three solutions for the clamping technique investigated. On these figures, part (a) shows the grid voltage and phase a current for each proposed method, obtained directly with an Oscilloscope. Instead part (b) of these figures were obtained by using DSP for control and MATLAB to capture the phase current and the modulating wave internal data. Fig.13 shows the voltage and current waveforms for the approximate solution approach discussed in section IV, while Figs. 14 and 15

Fig.9. Approximate solution: Grid voltage ( 37.5V/div) and phase current(top, 10A/div), at the top; Modulating wave and phase current (50A/div), at the bottom. Hor: 10ms/div).

Fig.10. Solution 1: Grid voltage (37.5V/div) and phase Current (10A/div). at the top; Modulating wave and phase current (50A/div) at the bottom. Hor: 10ms/div.

Fig.11. Solution 2: Grid voltage (37.5V/div) and phase current (10A/div), at the top. Modulating wave and phase current (50A/div), at the bottom. (Hor: 10ms/div).

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(a) Fig.12. Current Iq (21), at the top (2A/div), sinusoidal phase current (1A/div) and angle (19), from block diagram in Fig.5. Hor: 15ms/div

(b) Fig.14. Solution 1: (a) Grid voltage (25V/div) and phase current (10A/div); (b) Modulating wave and phase current (5A/div). Hor: 5ms/div.

(a)

(b) Fig.13. Approximate solution: (a) Grid voltage (25V/div) and phase current (10A/div), (b) Modulating wave and phase current (5A/div). Hor: 5ms/div.

(a)

VIII. CONCLUSIONS This paper relates a clamping One Cycle Control, OCC, strategy and Hybrid PWM, HPWM, resulting in a simple clamping method for three phase rectifier converter, which does not use grid voltage sensors. As an example of the technique, a clamping current hysteresis control is emulated and implemented, giving good results. Mathematical expressions as well as circuital schemes have been investigated and analyzed in this case. Simulation and DSP based experimental results validate the proposed technique. From a theoretical point of view, to implement hysteresis clamping controller using DPWM strategy by means of the proposed technique (OCC is a generalized PWM method) establishes a connection between hysteresis and PWM controllers. Furthermore, as DPWM implementation is also done by SVM method, it was indirectly established a relation between SVM and OCC.

(b) Fig.15. Solution 2: (a) Grid voltage(25V/div) and phase current (10A/div); (b) Modulating wave and phase current (2.5A/div). Hor: 5ms/div.

IX. AKNOWLEGMENTS The authors gratefully acknowledge the financial support of the Coordenao de Aperfeioamento de Pessoal de Nvel Superior (CAPES), the Conselho Nacional de Desenvolvimento Cientfico e Tecnolgico (CNPq), and the Fundao de Apoio Pesquisa da Paraba (FAPESQ) X. REFERENCES
[1] L. Malesani and P. Tomasin, PWM current control techniques of voltage source convertersA survey, in Proc. 1993 IEEE Industrial Electronics Conference, IECON93, pp. 670675. [2] M. P. Kazmierkowski and L. Malesani, Current control techniques for three-phase voltage-source PWM converters: a

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[3]

[4]

[5]

[6]

[7] [8] [9]

Survey, IEEE Trans on Industrial. Electronics, vol. 45, pp. 691703, Oct. 1998. Malesani L; Tenti P; Gaio E; Piovan R. Improved current control technique of VSI PWM inverters with constant modulation frequency and extended voltage range. IEEE Trans on Industrial Applications. Vol. 27, pp. 365369, 1991. G. Chen, and K. M. Smedley. Steady-State and Dynamic Study of One-Cycle-Controlled Three-Phase Power-Factor Correction, IEEE Transaction on Industrial Electronics, Vol. 52, No. 2, April2005, pp. 355-362. S. Ogasawara, H. Akagi, and A. Nabae, A novel PWM scheme of voltage source inverter based on space vector theory, in European Power Electronics and drives. EPE Conf. Rec., 1989, pp. 11971202. H. W. Van Der Broeck, Analysis of the harmonics in voltage fed inverter drives caused by PWM schemes with discontinuous switching operation, in European Power Electronics and drives EPE Conf. Rec., 1991, pp. 261266. J. Holtz, Pulsewidth modulation for electronic power converters, Proc.IEEE, vol. 82, no. 8, pp. 11941214, 1994. V. Blasko, Analysis of a hybrid PWM based on modified space vector and triangle comparison methods, IEEE Trans on Industrial Applications, vol. 33, pp. 756764, 1997. Z. Lai and K. M. Smedley. A General Constant-Frequency Pulsewidth Modulator and its Applications IEEE Trans. on Circuits and SystemsI: Fundamental Theory and Applications, Vol. 45, No. 4, 1998.

[10] [11]

[12]

[13] [14] [15]

[16]

A. S. Lock; E da Silva,; M. Elbuluk,; D. Fernandes A Hybrid Current Control for a Controlled Rectifier IEEE Energy Conversion Congress, ECCE 2010, Atlanta Georgia. C. Qiao and K. Smedley. Unified constant-frequency integration control of three-phase standard bridge boost rectifiers with power-factor correction IEEE Trans. on Industrial Electronics. Vol. 50, pp. 100- 107, Feb. 2003. Qiao, C. and Smedley, K.M. A General Three-phase PFC Controller for rectifiers with a Parallel-connected Dual Boost Topology. IEEE Trans. on Power Electronics, Vol. 17, No. 6, Nov. 2002 L. J. Borle and C. V. Nayar, Ramptime Current Control, IEEE Applied Power Electronics Conference, 1996, APEC96, pp. 828-834. A. M. Bento, E. R. da Silva. One Cycle Control Strategy of Three-phase Inverters Proc of CBA08 - Congresso Brasileiro de Automatica, 2008. CDROM. A. Hernandez, K. E. Chong, G. Gallegos, and E. Acha, The implementation of a solid state voltage source in PSCAD/EMTDC, IEEE Power Eng. Rev., pp. 6162, Dec. 1998. K.Rajendiran, W. W. Keerthipala, C. V. Nayar, PSCAD/ EMTDC based simulation of a wind-diesel conversion scheme, in Proc. 2000 IEEE PES Winter Meeting, pp. 505 510 Vol.1.

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