VHDL Tutorial Open Xilinx Project Navigator.

From File select New Project Name the project and do the adjustments just as in the first lab and as in the below figure.

You continue on by pushing Next button until the front window dissappears just as in the first lab. Then right click as in the below figure and select New Source just the same as the first lab.

From now on there is a difference as you will design your circuit by VHDL instead of schematics. Therefore select VHDL module from the New Source window. Then give a name to your project and click to Next until this window disappears.

Now you can see the VHDL code design environment as below. Here in the left half of the window, you will define your circuit by writing the VHDL code instead of drawing its schematic in schematic editor.

The best way to learn about VHDL is to look at a tutorial from the web if you want to design your circuit by VHDL. But here as a beginning for you, we will give the VHDL codes of the circuits from the first lab. For instance you should write the below code in order to implement D=A.B + C circuit in VHDL language :

entity dene_vhdl is port ( A : in std_logic; B : in std_logic; C : in std_logic; D : out std_logic ); end dene_vhdl; architecture Behavioral of dene_vhdl is signal AB signal CN begin : : std_logic; std_logic;

AB <= A and B; CN <= not C; D <= AB or CN; End Behavioral;

The resultant scene becomes as below:

Now after saving this file, you can make the simulation by right clicking to the VHDL file and selecting Testbench Waveform as in the first lab. And the other parts are all same as in the first lab. Look at below figure:

Here the most important thing is to understand the syntax of VHDL, meaning how the inputs, gates and relation between them are specified. For further information there is more than enough source about VHDL on the web. For now and for you to learn some more about VHDL, we add some more examples including the second circuit of first lab.

Lab 1- 2nd design --file named lab1_2.vhd

library IEEE; use IEEE.std_logic_1164.all; library WORK; package lab1_2 is component my_xor port ( X : in std_logic; Y : in std_logic; Z : out std_logic ); end component; component my_xor4 port ( X : in std_logic_vector(3 downto 0); Y : in std_logic_vector(3 downto 0); Z : out std_logic_vector(3 downto 0) ); end component; end lab1_2; ------------------------------------

------1bit xor gate----library IEEE; use IEEE.std_logic_1164.all; library WORK; use work.lab1_2.all; entity my_xor is port ( X : in std_logic; Y : in std_logic; Z : out std_logic ); end my_xor; architecture structure of my_xor is signal xn signal yn signal xny signal ynx begin xn <= not x; yn <= not y; xny <= xn and y; ynx <= yn and x; Z <= xny or ynx; end; : : : : std_logic; std_logic; std_logic; std_logic;

------4bit xor gate-----library IEEE; use IEEE.std_logic_1164.all; library WORK; use work.lab1_2.all; entity my_xor4 is port ( X : in std_logic_vector(3 downto 0); Y : in std_logic_vector(3 downto 0); Z : out std_logic_vector(3 downto 0) ); end my_xor4; architecture structure of my_xor4 is begin XOR_01 XOR_02 XOR_03 XOR_04 : : : : my_xor my_xor my_xor my_xor port port port port map map map map (X(0), (X(1), (X(2), (X(3), Y(0), Y(1), Y(2), Y(3), Z(0)); Z(1)); Z(2)); Z(3));

end; -----end of file-----