Ii.

MicheI ROLRT Iogique piogiannalIe

|cgiquc prcgrannao|c
|cgiquc prcgrannao|c
Partle 1
Rae|s : memolres(rlncles, techno|ogles)
1- PRINCIPE5 ct CLA55IFICATION
2- TECHNOLOGIE5
3- ARCHITECTURE5 ET CIRCUIT5
4- CONCEPTION
Par|ic 2
5- AIILICATIONS
2004

Circuit Spcifique vs Circuit Stundurd

SiIicon
Foundry
Chip
Pockoging
Tesf
IC
"Specificutions"
"Loyouf"
Design
HW
SW
Munufucturing
Euros /
mm
Z
Standard Memoire, FPGA, C, .
Mcncrq Arcni|cc|urc. Dcccdcrs
Mcncrq Arcni|cc|urc. Dcccdcrs
Word 0
Word 1
Word 2
Word N
2
2
Word N
2
1
Storage
cell
M bits M bits
N
w o r d s
S
0
S
1
S
2
S
N
2
2
A
0
A
1
A
K
2
1
K
5
log
2
N
S
N
2
1
Word 0
Word 1
Word 2
Word N
2
2
Word N
2
1
Storage
cell
S
0
Input-Output
(M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
K log
2
A
Decoder reduces the number of select signals
Input-Output
(M bits)
D e c o d e r
PRINCIPE5 : rappc!s sur !cs mmnIrcs ROM - RAM
Non vo1o11111g Non vo1o11111g
Do1o 1s s1ored even 1] vo11oge 1s su11oed o]] Do1o 1s s1ored even 1] vo11oge 1s su11oed o]]
BI BI- -dImensIonaI array oI IInes (Word LIne) and coIumns (BIt LIne) dImensIonaI array oI IInes (Word LIne) and coIumns (BIt LIne)
One memory ceII at eacb IntersectIon (1 bIt) One memory ceII at eacb IntersectIon (1 bIt)
SeIectIon oI a IIne and a coIumn Ior wrItIng data SeIectIon oI a IIne and a coIumn Ior wrItIng data
"0" "0"
"1" "1"
MmoIre : prIncIpe
M M moIre moIre : : prIncIpe prIncIpe
Rcad
Rcad
-
-
On|q Mcncrq Cc||s
On|q Mcncrq Cc||s
WL
BL
WL
BL
1
WL
BL
WL
BL
WL
BL
0
V
DD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
MOS OR ROM
MOS OR ROM
WL [0]
V
DD
BL [0]
WL [1]
WL [2]
WL [3]
V
bias
BL[1]
Pull-down loads
BL [2] BL [3]
V
DD
MOS NOR ROM
MOS NOR ROM
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
V
DD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
MOS NOR ROM |aqcu|
MOS NOR ROM |aqcu|
Programmming using the
Active Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5 x 7)
MOS NOR ROM |aqcu|
MOS NOR ROM |aqcu|
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11 x 7)
Programmming using
the Contact Layer Only
Electrically Erasable Programmable Read-Only Memory
Gate
floating gate
The application of a potential on the upper gate
causes the transfer of charges from the channel
trough the thin oxyde layer, which charges the
floating gate.
Oxyde layer
S D
G
N+
Silicon oxyde
Polysilicon
level 1
Vcc
G
Floating gate
Bit output
Word selection
Polysilicon
level 2
P|A .
P|A .
principc
principc
x
0
x
1
x
2
AND
plane
x
0
x
1
x
2
Product terms
OR
plane
f
0
f
1
Tuc
Tuc
-
-
|ctc| |cgic
|ctc| |cgic
Inverting format (NOR-
NOR) more effective
Every logic function can be
expressed in sum-of-products
format (AND-OR)
minterm
Arcni|cc|urc d
Arcni|cc|urc d

un P|D cu P|A . principcs

un P|D cu P|A . principcs
A B C
F
2
F
1
F
0
F ABC
F ABC AB
F ABC BC AC
0
1
2
=
= +
= + +
ABC
A B
BC
AC
A
B
A
B
B

Arraq
Arraq
-
-
8ascd Prcgrannao|c |cgic
8ascd Prcgrannao|c |cgic
PLA PROM PAL
I
5
I
4
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Programmable AND array
Programmable
OR array
I
5
I
4
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Programmable AND array
Fixed OR array
Indicates programmable connection
Indicates fixed connection
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Fixed AND array
Programmable
OR array
Prcgranning a PROM
Prcgranning a PROM
f
0
1 X
2
X
1
X
0
f
1
NA NA
: programmed node
P|A tcrsus ROM
P|A tcrsus ROM
Programmable Logic Array
structured approach to random logic
two level logic implementation
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLAs has drastically reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
Prcgrannao|c |cgic Arraq
Prcgrannao|c |cgic Arraq
GND GND GND GND
GND
GND
GND
J
DD
J
DD
X
0
X
0
X
1
f
0
f
1
X
1
X
2
X
2
AND-plane OR-plane
Pseudo-NMOS PLA
P|A |aqcu|
P|A |aqcu|
V
DD
GND

And-Plane Or-Plane
f
0
f
1
x
0
x
0
x
1
x
1
x
2
x
2
Pull-up devices Pull-up devices
1 - ClRCUlTS LOGlQUES PROGRAMMABLES : PRlNClPES
1 1 - - ClRCUlTS LOGlQUES PROGRAMMABLES : ClRCUlTS LOGlQUES PROGRAMMABLES : PRlNClPES PRlNClPES
COMPOSANTS STANDARDS PROGRAMMABLES
ELECTRIQUEMENT UNE SEULE FOIS (FUSIBLES) OU
RE-PROGRAMMABLES (RECONFIGURATION)
PRINCIPES DES ARCHITECTURES: Ensemble de
ressources logiques (portes, bascules, .etc) qui peuvent tre
interconnectees de diIIerentes Iaons. REALISATION DE
FONCTIONS BOOLEENNES SOUS FORME D`UNE SOMME
LIMITEE DE MONOMES (PAL, PLD, EPLD,...) OU D`UN
RESEAU DE CELLULES (FPGA)
TECHNOLOGIES DE PROGRAMMATION : FUSIBLES
(METAL), ANTIFUSIBLES (CAPACITE MOS),
TRANSISTOR MOS A GRILLE FLOTANTE (EPLD), RAM
STATIQUE (FPGA-SRAM),...
OUTILS DL CAO SILCIIIQULS
1 1- - C|RCU|TS PROGRAMMA8||S . c|assifica|icn C|RCU|TS PROGRAMMA8||S . c|assifica|icn
Ciicuils eIenenlaiies PLD , IAL,,...
AnaIogie avec Ies nenoiies IROM, ncn rcprcgrannao|cs
(fusio|cs)
Iienieis ciicuils piogiannalIes ieaIises en lechnoIogie
lipoIaiie
CPLD ConpIex IiogiannalIe Logic Device: LILD,
LLILD
AnaIogie avec Ies nenoiies LIROM, LLIROM, ILASH
rcprcgrannao|cs
Sliucluies ieguIiies ieaIisees en lechnoIogie MOS
Ieifoinances piediclilIes (ielaids)
FPGA IieId piogiannalIe Cale Aiiay:
naliice de lIocs Iogiques el ieseau dinleiconnexion
- FPGA-5RAM (AnaIogie avec Ies nenoiies RAM) rcprcgrannao|cs
- IICA ncn rcprcgrannao|cs (an|i-fusio|cs)
- Ieifoinances dependanles de IappIicalion
Programmable
Programmable
Logic
Logic
Device
Device
Families
Families
Source: Dataquest
Logic
Standard
Logic
ASIC
Programmable
Logic Devices
(PLDs)
Gate
Arrays
Cell-Based
ICs
Full Custom
ICs
CPLDs
SPLDs
(PALs)
FPGAs
Acronyms
SPLD = Simple Prog. Logic Device
PAL = Prog. Array of Logic
CPLD = Complex PLD
FPGA = Field Prog. Gate Array
Common Resources
Configurable Logic Blocks (CLB)
Memory Look-Up Table
AND-OR planes
Simple gates
Input / Output Blocks (IOB)
Bidirectional, latches, inverters
L'ufiIisofeur de circuifs progrommobIes s'equipe ovec :
Pour Iu ruIisution d'un circuit :
^ un oufiI IogicieI de CAO (sur PC principoIemenf)
^ des circuifs progrommobIes vierges (non progrommes)
Conception de Circuits progrummubIes : principes
^ une pIofine de progrommofion (Iivree ovec Ie IogicieI)
- L'ufiIisofeur reoIise son design (schemofique ou
HDL) ef Ie progromme sur Ie supporf de son
choix (CPLD ou FP0A)
- Une fois Ie circuif progromme, iI devienf
operofionneI ef peuf fre pIoce sur son supporf
d'ufiIisofion (corfe)
FPGA Design Flow :
FPGA Design Flow :
Example
Example
XC4000 XC4000 XC4000
Design entry and synthesis in schematic
and/or text.
Download directly to the hardware device(s)
with unlimited reconfigurations
1
Implementation includes Map, Place, Route, and
bitstream generation using Xilinx software. Also,
analyze timing, view layout, and more.
2
3
Simplicity
|PGA
|PGA
AVANTAGE5
AIIRLNTISSACL DLS OUTILS
DLLAI DL CONCLITION
Reconfiguialion en Iigne (IICA-SRAM)
IROTOTYIACL RAIIDL
DLLAI DL IARICATION DL ILTITLS SLRILS
MODIIICATIONS RAIIDLS
COMIOSANT TLSTL AU IRLALALL
IossiliIile de nigiei veis un ASIC
INCONVENIENT5
IRIX UNITAIRL IOUR DL CRANDLS SLRILS
ILRIORMANCLS LLLCTRIQULS, COMILLXITL
TAUX D UTILISATION DU CIRCUIT
SLNSIILITL AUX CONDITIONS D UTILISATION
IROTLCTION DU SAVOIR IAIRL
CIRCUITS MIXTLS
Programming technologies
One time programming
Bit
Fuse
Vcc
Mtal 1
Mtal 2
Dielectric
Z- TechnoIogies
TechnoIogie comporobIe ceIIe des PPOMs
reseoux de porfes ovec connexions progrommobIes
progrommofion por fusibIes (comme Ies PPOMs)
non reprogrommobIes
foncfions Iogiques simpIes (sfrucfures de fype Sum-of-Producfs)
cof unifoire eIeve (foibIes series, profofypes, ,)
it Word Iine
Historique (prhistoire : il y a 25 ans) : PLD Bipolaires
PLD {ProgrummubIe Logic devices}
Bit
Vcc
Z- TechnoIogies : EPLD
griIIe
0riIIe fIoffonfe
source
droin
fronsisfor griIIe fIoffonfe
L 'oppIicofion d 'un pofenfieI sur Io griIIe superieure
provoque Ie possoge d 'une porfie des eIecfrons du
conoI frovers Io mince couche d 'oxyde, ce qui chorge
Io griIIe fIoffonfe. Lors de Io Iecfure, une fension
oppIiquee sur Io griIIe superieure esf compIfemenf
mosquee por Io chorge negofive emmogosinee sur Io
griIIe fIoffonfe. CeIo equivouf un fronsisfor foujours
bIoque.
- mme technologie que celle des memoires EPROM
- transistor a double grille
- reprogrammable (eIIacement par UV ou electriquement)
G
S
D
||ca|ing ga|c |ccnnc|cgq
||ca|ing ga|c |ccnnc|cgq
N

Polysilicon floating gate

Polysilicon control gate
Silicon dioxide
P
J
D
J
C
J
S
D
r
a
i
n

c
u
r
r
e
n
t
Select gate
voltage
VTH VTL
S
e
n
s
e

t
h
r
e
s
h
o
l
d
V
T
adjusted by the amount oI charge in the Iloating gate
Can be programmed in an analog way
D S
Floating gate
Source
Substrate
Gate
Drain
n
+
n
+_
p
t
ox
t
ox
Device cross-section
2
2
-
-
Tccnnc|cgic
Tccnnc|cgic

An|i
An|i
-
-
fusio|c
fusio|c

Anli fusilIe = condensaleui

Ac|c|
Ciealion dun couil ciicuil enlie
deux Iignes de nelaI: cIaquage
Iiogiannalion definilive
Tis peu de pIace occupee sui Ie ciicuil, nais elapes de
faliicalion suppIenenlaiies
peifoinances eIecliiques supeiieuies a Ia lechnoIogie
SRAM (nininisalion de Ia suiface el des effels RC)
Mtal 1
Mtal 2
Dielectric
|usc
|usc
-
-
8ascd |PGA
8ascd |PGA
antifuse polysilicon ONO dielectric
n
+
antifuse diffusion
2 l
From Smith97
Open by default, closed by applying current pulse
- Tcchnn!ngIc CMO5 standard
- Ioiles de liansnission ou nuIlipIexeuis connandes
pai des ceIIuIes SRAM
- Les nenoiies SRAM peinellenl de configuiei Ies
inleiconnexions el de piogiannei Ies ceIIuIes
- Ie IICA doil lie configuie a chaque nise sous lension
a pailii dune nenoiie exleine (LIROM)
EPROM
FPGA-SRAM
FPGA
EPROM1
FPGA
EPROM2
EPROM3
FPGA
2
2
-
-
Techno|ogle
Techno|ogle

FP0A FP0A- -SPAM SPAM

|cgiquc
|cgiquc
a
a
pcr|cs dc |ransnissicn
pcr|cs dc |ransnissicn
reseau
d`interrupteurs
S
S
B
A
S
V
DD
A
B
C
A B
C
V
DD
C
Porte de
transmission
V
DD
V
DD
V
DD
Rcgis|rc Rcgis|rc a a d dc cca|agc ca|agc
2
2
-
-
inpu|
inpu|
nux
nux
as prcgrannao|c |cgic o|cc|
as prcgrannao|c |cgic o|cc|
F
A 0
B
S
1
Configuration
A B S F=
0 0 0 0
0 X 1 X
0 Y 1 Y
0 Y X XY
X 0 Y
Y 0 X
Y 1 X X
+
Y
1 0 X
1 0 Y
1 1 1 1
XY
XY
X
Y
|xcrciccs . |cgiquc |xcrciccs . |cgiquc a a nu||ip|cxcurs nu||ip|cxcurs
A
B
S
C
SA.B
SAB
S !C !A.B
A
S
B
A
S
B
C
!C
Rappc|s |ccnnc|cgiqucs . MOS
Rappc|s |ccnnc|cgiqucs . MOS
SiO
2
p
n n
substrat p
Grille
Source Drain
Point memoire
CK
D Q
Q
SRAM
SRAM
6
6
-
-
|ransis|cr CMOS SRAM Cc||
|ransis|cr CMOS SRAM Cc||
WL
BL
V
DD
M
5
M
6
M
4
M
1
M
2
M
3
BL
Q
Q
6T
6T
-
-
SRAM
SRAM

|aqcu|
|aqcu|
V
DD
GND
Q
Q
WL
BL BL
M1 M3
M4 M2
M5 M6
Programming technologies : SRAM (FPGAs)
Word line
B
i
t

l
i
n
eVcc Vcc
SRAM
Programming must be done at each power-up
FPGA-SRAM
A B C
S
0
1
1
1
0
1
0
1
MUX
SRAM cells
A
B
S
C
A
S
B
C
!C
SA.B ?
Mu||ip|cxcur/D
Mu||ip|cxcur/D
c
c
nu||ip|cxcur 8 tcrs 1
nu||ip|cxcur 8 tcrs 1
S1 S2 S3
Rappc| . R Rappc| . Rc ca|isa|icn dc fcnc|icns |cgiqucs atcc dcs nu||ip|cxcurs MOS a|isa|icn dc fcnc|icns |cgiqucs atcc dcs nu||ip|cxcurs MOS
A
B
S
C
A
S
B
C
!C
LUT 3
A 8 C Z
0 0 0 I
0 0 I 0
0 I 0 I
0 I I I
I 0 0 I
I 0 I I
I I 0 I
I I I 0
Look Up TobIe
C

A
Z
1
0
1
1
1
1
1
0
Si C0, alors SA
Si C1, alors SB
Tronsisfor MMOS ~ commufofeur
Droin
Source
0riIIe
0 ~ I
0 ~ 0
Exemples.
SX.Y si C X, A 0, B Y
SXY si C !X, A 1, B X
0000 0
0001 0
0010 1
0011 1
0100 1
0101 0
0110 0
0111 0
1000 0
1001 1
1010 0
1011 0
1100 1
1101 0
1110 0
1111 0
0
1
1
0
Inputs
0 Output
Lookup table principle (LUT)
A four-input lookup table: LUT 4
Memory adresses Memory Bits
2
n
possible combinational functions
Lookup table principle (LUT)
LUT realization : Tree of Muxes
A B C
S
0
0
1
0
0
0
0
0
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
A B C
S
0
0
1
0
0
0
0
0
A B C
S
0
1
1
1
0
1
0
1
MUX
1 1 1 1
1 O 1 1
1 1 O 1
O O O 1
1 1 1 O
O O 1 O
1 1 O O
O O O O
5 C B A
Mu!tIp!cxcrs
S = A.+C
SRAM cells
Lookup table principle (LUT)
LUT realization example
3
3
-
-
Arcni|cc|urcs c| circui|s
Arcni|cc|urcs c| circui|s
Reseaux de poiles : ILD, CILD
Reseaux de ceIIuIes : IICA a giain
vaiialIe
- Look-up TalIe el CL (Xi|inx)
- nuIlipIexeuis associes a des poinls nenoiie
- MuIlipIexeuis (Ac|c|)
Reseaux de poiles el de ceIIuIes
AssenlIage de lIocs conpIexes
3
3
-
-
Arcni|cc|urc d
Arcni|cc|urc d

un P|D
un P|D
A B C
F
2
F
1
F
0
F ABC
F ABC AB
F ABC BC AC
0
1
2
=
= +
= + +
ABC
A B
BC
AC
3
3
-
-
|PGA
|PGA
-
-
SRAM
SRAM
. Arcni|cc|urc
. Arcni|cc|urc
UN ILAN DL MLMOIRLS DL CONIICURATION ASSOCIL A UN ILAN DL
CALCUL COMIOSL DL CL + UN RLSLAU d INTLRCONNLXION
CL = LOC LOCIQUL CONIICURALL ("CnnfIgurab!c LngIc B!nck"),
consliuil a pailii dun ou de pIusieuis geneialeuis de fonclions (LUT = Look
Up TalIe). Un LUT coiiespond a un ailie de nuIlipIexeuis connecle a des
poinls nenoiies (SRAM).
LL CONTLNU DLS MLMOIRLS LST STOCKL DANS UN COMIOSANT
LXTLRNL (LIROM,...) : LA CONIICURATION LST CHARCLL A CHAQUL
MISL SOUS TLNSION
SRAM
CLB CLB
CLB CLB
CLB
CLB
Switch matrix
Processing element
Switchbox
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Reconf. block I/O block
Arrays of reconfigurable blocks (CLB) connected by
Programmables interconnections (switch matrix)
The block architecture differs from vendors,
but is always LUT-based.
FPGAs : Field Programmable Gate Arrays
Basic idea: two-dimensional array of logic blocks and flip-flops with a means
for the user to configure:
1. the interconnection between the logic blocks,
2. the function of each block.
Reconfigurable technology : FPGAs
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
FPGAs : Reconfigurability
Switch Matrix
Basic idea: two-dimensional array of logic blocks and flip-flops with a means
for the user to configure:
1. the interconnection between the logic blocks,
2. the function of each block.
Reconfigurable technology : FPGAs
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
FPGAs : Reconfigurability
4-LUT FF
1
0
latch
Logic Block
set by configuration
bit-stream
4-input "look up table"
OUTPUT
INPUTS
Programmable
logic blocks
Programmable
interconnect
bif- IeveI reconfigurobIe
CLB CLB CLB CLB CLB
CLB
CLB CLB
CLB CLB
CLB
CLB CLB
CLB CLB
CLB
CLB
CLB
CLB CLB
Principe de Principe de I I' 'urchitecture urchitecture d d' 'un circuit FPSA un circuit FPSA- -SRAM : CL LUT,,, SRAM : CL LUT,,,
S
Q
D
R
LUT
CL8 ~ 8LOC LO0IQUE COMFI0UPA8LE ("ConfigurobIe Logic 8Iock"), consfruif porfir d'un
generofeur de foncfions LUT : Look Up TobIe ). PeoIisofion de bIocs combinofoires ou
sequenfieIs
CL
LUT 3
Multiplexeur 2:1
Structure d'un FPSA-SRAM : ceIIuIes et conneions
CeIIuIe
Logique
CL
CeIIuIe
d'interconneion
gIobuIe
CeIIuIe
d'interconneion
IocuIe
CeIIuIe
Mmoire
SRAM
CONF
{b} Phuse de configurution {c} Phuse d'oprution
E
S
Fonctionnement d'un FPSA-SRAM
Entree CONF active . chargement
des SRAM (en chaine)
Entree CONF desactivee
Ionctionnement normal du circuit conIigure
CONF
Vcc
Gnd
{u} Mise sous tension
Vcc
Gnd
SRAM SRAM SRAM
SRAM SRAM SRAM
SRAM SRAM SRAM
Couche OPERATIVE Couche OPERATIVE
Couche de CONFIGURATION Couche de CONFIGURATION
Reconfiguration de FPGA-SRAM
CONF
CONF
Phuse de configurution
Phuse d'oprution:
E
S
conf1
conf2
conf3
conf4
SRAM SRAM SRAM
SRAM SRAM SRAM
SRAM SRAM SRAM
Couche OPERATIVE Couche OPERATIVE
Couche de CONFIGURATION Couche de CONFIGURATION
Reconfiguration de FPGA-SRAM
RECONF!GURAT!ON STATIQUE
Chargement squentiel de plusieurs architectures
Une architecture par application
RECONF!GURAT!ON PSEUDO-DYNAN!QUE
Chargement squentiel de plusieurs architectures
Plusieurs architectures par application
RECONF!GURAT!ON DYNAN!QUE
Chargement continu
Larchitecture volue en cours de traitement
CONF
CONF
Phuse de configurution
Phuse d'oprution:
E
S
Arraq
Arraq
-
-
8ascd Prcgrannao|c liring
8ascd Prcgrannao|c liring
Input/output pin Programmed interconnection
Interconnect
Point
Horizontal
tracks
Vertical tracks
Cell
M
Mcsn
Mcsn
-
-
oascd |n|crccnncc| Nc|ucr|
oascd |n|crccnncc| Nc|ucr|
Switch Box
Connect Box
Interconnect
Point
Courtesy Dehon and Wawrzyniek
Transis|cr |np|cncn|a|icn cf Mcsn
Transis|cr |np|cncn|a|icn cf Mcsn
Courtesy Dehon and Wawrzyniek
Hicrarcnica| Mcsn Nc|ucr|
Hicrarcnica| Mcsn Nc|ucr|
Use overlayed mesh
to support longer connections
Reduced fanout and reduced
resistance
Courtesy Dehon and Wawrzyniek
Circuits ProgrummubIes : compIeit du systme
d'interconneions
lna|
lna|

s in a sui|cnocx?
s in a sui|cnocx?
One oi noie svilches
Lach Iinking lvo viie
segnenls
Svilchlox size depends
on lhe size and nunlei of
svilches
Topologies dInterconnexion
Global switch
1D array
Bus
Ring
Star
2D array
Torus
3D array
Crossbar
lna|
lna|

s in a sui|cn?
s in a sui|cn?
Menoiy LIenenl
- Snif| rcgis|cr
- RAM cc||
Switch Element
- Buffer
- Pass transistor
lna|
lna|

s in a sui|cn?
s in a sui|cn?
Menoiy LIenenl
- Snif| rcgis|cr
- RAM cc||
Switch Element
- Buffer
- Pass transistor
lna|
lna|

s in a 6
s in a 6
-
-
oi| sui|cn?
oi| sui|cn?
Exemple : XC4000 Architecture
Exemple : XC4000 Architecture
CLB
CLB
CLB
CLB
Switch
Ma trix
Programmable
Interconnect
I/O Blocks (IOBs)
Configurable
Logic Blocks (CLBs)
D Q
Slew
Rate
Control
Passive
Pull-Up,
Pull-Down
Delay
Vcc
Output
Buffer
Input
Buffer
Q D
Pad
D Q
SD
RD
EC
S/R
Control
D Q
SD
RD
EC
S/R
Control
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
H'
H
Func.
Gen.
G
Func.
Gen.
F
Func.
Gen.
G4
G3
G2
G1
F4
F3
F2
F1
C4 C1 C2 C3
K
Y
X
H1 DIN S/R EC
XC4000 Configurable
XC4000 Configurable
Logic
Logic
Blocks
Blocks
D Q
SD
RD
EC
S/R
Control
D Q
SD
RD
EC
S/R
Control
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
H'
H
Func.
Gen.
G
Func.
Gen.
F
Func.
Gen.
G4
G3
G2
G1
F4
F3
F2
F1
C4 C1 C2 C3
K
YQ
Y
XQ
X
H1 DIN S/R EC
2 Four-input function
generators (Look Up
Tables)
2 Registers : Each can be
configured as Flip Flop or
Latch
Look Up Tables (LUT)
Look Up Tables (LUT)
Capacity is limited by number of
inputs, not complexity
Choose to use each function
generator as 4 input logic (LUT) or as
high speed sync.dual port RAM
Combinatorial Logic is stored in 16x1 SRAM Look Up Tables
(LUTs) in a CLB
Example:
A B C D Z
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
. . .
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Look Up Table
Combinatorial Logic
A
B
C
D
Z
4-bit address
G
Func.
Gen.
G4
G3
G2
G1
WE
2
(2 )
4
= 64K !
XC4000E I/O Block
XC4000E I/O Block
Diagram
Diagram
D Q
Slew
Rate
Control
Passive
Pull-Up,
Pull-Down
Delay
Vcc
Output
Buffer
Input
Buffer
Q D
OK (Output
Clock)
IK (Input
Clock)
I
1
2
I
O
T/OE
Pad
CE
Xilinx
Xilinx
FPGA
FPGA
Routing
Routing
Fast Direct Interconnect - CLB to CLB
General Purpose Interconnect - Uses switch matrix
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Switch
Matrix
Switch
Matrix
Long Lines
Segmented across
chip
Global clocks,
lowest skew
2 Tri-states per
CLB for busses
Other routing types in
CPLDs and XC6200
FPGA : LAYOUT
FPGA : LAYOUT
CLB
(Red)
Switch
Matrix
Long Lines
(Purple)
Direct
Interconnect
(Green)
Routed Wires (Blue)
Programmable Interconnect Points, PIPs (White)
Xi|inx 4000 |n|crccnncc| Arcni|cc|urc
Xi|inx 4000 |n|crccnncc| Arcni|cc|urc
2
12
8
4
3
2
3
CLB
8 4 8 4
Quad
Single
Double
Long
Direct
Connect
Direct
Connect
Quad Long Global
Clock
Long Double Single Global
Clock
Carry
Chain
Long
12 4 4
Courtesy Xilinx
FPSA-SRAM
CONF
CONF
Phuse de configurution
Z,10

bits f=0, Mhz {4 s}

Phuse d'oprution:
Z,10
3
bits f=0 Mhz {40 s}
EempIe : XiIin XC40
E
S
RAM
RAM
-
-
oascd |PGA
oascd |PGA
Xilinx XC4000ex
Courtesy Xilinx
|PGA
|PGA

Ac|c|
Ac|c|

I/O blocks
I/O blocks
I
/
O

b
l
o
c
k
s
I
/
O

b
l
o
c
k
s
Programmation par anti-Iusible
- Technologie 'antiIusible
- Architecture a grain Iin
Mtal 1
Mtal 2
Dielectric
|PGA
|PGA

A||cra
A||cra

Programmation EPROM
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
PIA
I/O control block
I/O control block
I
/
O

c
o
n
t
r
o
l

b
l
o
c
k
I
/
O

c
o
n
t
r
o
l

b
l
o
c
k
LAB Logic Array Block
PIA Programmable Interconnect Array
Array oI
Macrocells
Expander
Product Term
Array
P
I
A
LAB
|PGA
|PGA
A||cra
A||cra
MacioceII
- IIan LT dun IAL
- Monnes allaquenl une lascuIe D
avec Sel el Resel.
Lxpandei
- IIan LT dun IAL
- Monnes ieinjecles conne enliees de Ia
MacioceII
Architectures : du grain fin au grain pais
GRAIN PAIS
bit
CLB

ALU + MULT
Reg FILE
mot
DCT
algorithme
Cur
MPEG4
application
Cur
hybride
FPGA
DSP
Cur reconfigurable
Interconnexion ?
Quelle Granularit ?
GRAIN FIN
add
multiply
mux
mux
add
register
Programmable
logic blocks
Programmable
interconnect
Bit - level reconIigurable
Word - level reconIigurable
Ccnccp|icn
Ccnccp|icn
d
d

arcni|cc|urcs
arcni|cc|urcs
rcccnfigurao|cs
rcccnfigurao|cs
Choix el Ciain des eIenenls de caIcuI
Choix el Ciain du ieseau d'inleiconnexion
Tenps el laux de (Re) configuialion
Ioui
Ccnscnna|icn
S|cc|agc dc dcnnccs
|n|crccnncxicn f|cxio|c
Rc-u|i|isa|icn
+
*
SRAM SRAM SRAM
SRAM SRAM SRAM
SRAM SRAM SRAM
OPERATING layer OPERATING layer
CONFIGURATION layer CONFIGURATION layer
CLB, LC
Global
interconnect
Local
interconnect
CLB, LC : bit-level processing unit {Look-Up-Tables)
Ccnccp|icn
Ccnccp|icn
d
d

ARD
ARD
. Grain fin
. Grain fin
Classification d'architectures
Exemple : XC6200
Exemple : XC6200
(abandonn
(abandonn

)
)
1/4
1/4
4x4 Block
User I/Os
16x16 Tile
Address
Data
FastMAP
tm
Interface
U
s
e
r

I
/
O
s
U
s
e
r

I
/
O
s
User I/Os
Control












*Number of tiles varies between devices in family
Function Cell
Conception Grain pais
CAHIER DES CHARGES
Acclration des applications orientes flots de donnes
Extrapolation aise sur de nouvelles technologies
Flexibilit dutilisation maximale
Personnalisation aise
GRAIN EPAIS
Faible surcot
ALU, MULT
Registres
Multiplexeurs
Oprateurs
arithmtiques
Grain fin Grain pais
4. Concetlon d
4. Concetlon d

un clrcult rogrammab|e: rlncles

un clrcult rogrammab|e: rlncles
'compilateur
svnthese ...
... mapping
SPECIFICATION
circuit
Placement - Routage
EDITEUR DE SCHEMA ou
DESCRIPTION (machines d`etat,
equations booleennes,..)
LIBRAIRIE
DE CELLULES
- spcification
- schmas symboles
- modles simulation
simulation
simulation
post-layout
PROGRAMMATION
(Iichier ----~ programmateur)
VeriIications
TEST
(synthese logique,...etc.)
VHDL
CAO SPECIFIQUE FPGA
CAO STANDARD
CAO DE FPGA : EXEMPLES
CAO DE FPGA : EXEMPLES
B
a
t
t
e
r
y
n
o
t

i
n
c
l
u
d
e
d
!
4. Concetlon d
4. Concetlon d

un clrcult rogrammab|e:
un clrcult rogrammab|e:
rototage
rototage
CART| A|T|RA UP
CART| A|T|RA UP
-
-
D|P
D|P
Hardware Boards : example

Plateforme de prototypage : principe
CIRCUITS RECONFIGURABLES
Ii. MicheI ROLRT Iogique piogiannalIe
|cgiquc prcgrannao|c. r
|cgiquc prcgrannao|c. r
c
c
sun
sun
c
c
TECHNOLOGIE5 dc prngrammatInn dc cnnncxInns
ct dc fnnctInns !ngIqucs
- specifiques : fusilIe (anlifusilIe pai capacile de AcleI),
liansisloi a giiIIe fIollanle
- slandaid CMOS : S-RAM
- Cri|crcs dc ccnparaiscn . ccu|s, rcccnfigura|icn, pcrfcrnancc
c|cc|riquc (~ RC)
ARCHITECTURE5 ET CIRCUIT5
Deconposilion dune fonclion Iogique dans une sliucluie de lype ILD ou
dans un ieseau de ceIIuIes
IICA-SRAM : CL oiganise en LUT. LUT = nenoiie + nuIlipIexeui
poui inpIenenlei diieclenenl des lalIes de veiile.
quc| grain ?du gain fin au grain cpais (cnpiriquc)
|c prco|cnc dc |in|crccnncxicn
|cs principcs dc |a rcccnfigura|icn s|a|iquc c| dqnaniquc
|PGA . cc
|PGA . cc
u
u
| dc |a prcgranna|icn
| dc |a prcgranna|icn
1 Millard de Transistors implants
20
200 millions de Transistors exploitables
Impact sur le cot
Impact sur les perIormances (vitesse plus lente qu`un circuit non reconIigurable realise
dans une technologie equivalente)
Circuits progrummubIes : perspectives
C1
Bloc FPGA
- complexite croissante (loi de moore)
- organisation hierarchique : blocs dedies
- bus d`interconnexions ?
- outils de CAO HW & SW ?
DSP
RAM
Hc|crcgcnccus Prcgrannao|c P|a|fcrns
Hc|crcgcnccus Prcgrannao|c P|a|fcrns
Xilinx Vertex-II Pro
Courtesy Xilinx
High-speed I/O
Embedded PowerPc
Embedded memories
Hardwired multipliers
FPGA Fabric
re^ EPXAI0
Moximum Sysfem 0ofes
I,77Z,000
TypicoI 0ofes (IEEE)
I,000,000
LEs 38,400
Embedded Sysfem 8Iocks (ES8s) Io0
Moximum PAM 8ifs 3Z7,o80
Moximum User I/O Pins bZI
SingIe-Porf SPAM Zbo Ibyfes
DuoI-Porf SPAM IZ8 Ibyfes
TofoI Pom 8ifs (PLD + Sfripe) 3,473,408
ARCHITECTURES DES CIRCUITS PROSRAMMALES : ARCHITECTURES DES CIRCUITS PROSRAMMALES : voIutions voIutions
ExempIe : AIfero serie APEX xxxx ExempIe : AIfero serie Sfrofix
EPISIZ0 (Z003)
8Iocs Logiques : II4I40
8Iocs memoires bIZ bifs : III8
8Iocs memoires 4Ibifs : bZ0
8Iocs Mego PAM : IZ
8Iocs DSP (MAC + regisfres +..) : Z8
E/S : I3I0
Architectures multi-processeurs
Ii. MicheI ROLRT Iogique piogiannalIe
|cgiquc prcgrannao|c
|cgiquc prcgrannao|c
Par|ic1
1- IRINCIILS el CLASSIIICATION
2- TLCHNOLOCILS
3- ARCHITLCTURLS LT CIRCUITS
4- CONCLITION
Partle 2
5- APPLICATION5
Ccnp|
Ccnp|
c
c
ncn|s
ncn|s
.
.
Docunenls XiIinx
15
0n
m
/ 2
00m
m
A
S
IC
s
15
0n
m
/ 2
00m
m
A
S
IC
s
|PGA/AS|C Crcssctcr Cnangcs
|PGA/AS|C Crcssctcr Cnangcs
Production Volume
C
o
s
t
90nm / 300mm ASICs
90nm / 300mm ASICs
1
5
0
n
m

/

2
0
0
m
m

F
P
G
A
s
1
5
0
n
m

/

2
0
0
m
m

F
P
G
A
s
9
0
n
m

/

3
0
0
m
m

F
P
G
A
s
9
0
n
m

/

3
0
0
m
m

F
P
G
A
s
FPGA Cost Advantage ASIC Cost Advantage FPGA Cost Advantage ASIC Cost Advantage FPGA Cost Advantage
Source: Current and Emerging Embedded Markets and Opportunities ElectronicMarket Forecasters
Prcgrannao|c |cgic can cffcr
Prcgrannao|c |cgic can cffcr
|nc |cucs| Ccs| Sc|u|icn
|nc |cucs| Ccs| Sc|u|icn
Tota| cost over t|me
D
e
v
e
l
o
p
m
e
n
t

C
o
s
t

+

D
e
v
i
c
e

C
o
s
t
Increasing NRE
18% of projects are cancelled within
5 months
58% are late to market which could
impact total volumes shipped
ASIC cycle is too long for some
market windows
Increasing NRE
18% of projects are cancelled within
5 months
58% are late to market which could
impact total volumes shipped
ASIC cycle is too long for some
market windows
Total Units
Additional ASIC costs: Additional ASIC costs:
0ecreas|ng FPCA un|t cost
push|ng crossover po|nt to
the r|ght
FPCA so|ut|on has
a |ower tota| cost
FPGAs were ultimately the most cost-effective solution, allowing us to provide new services
year after year. With Xilinx, we were able to protect our initial investment.
- Mr. Yoshiko Chika,
Director and Sr. General Manager, DDI Pocket
A8|6 A8|6
Trend Trend
FPCA FPCA
Trend Trend
Prcgrannao|c |cgic |tc|u|icn
Prcgrannao|c |cgic |tc|u|icn
1985
X62000-X63000 X64000, V|rtex
V|rtex-|| Pro
V|rtex-|| Pro X
1992 2000 2002
0
e
v
|
c
e

6
o
m
p
|
e
x
|
t
y
V|rtex-||
2004
FPCA Fabr|c
|ock RAH
8e|ect|0
X6|TE Techno|ogy
06H
Embedded
Hu|t|p||ers
PowerP6
Rocket|0
FPCA Fabr|c FPCA Fabr|c
|ock RAH |ock RAH
8e|ect|0 8e|ect|0
X6|TE Techno|ogy X6|TE Techno|ogy
06H 06H
Embedded Embedded
Hu|t|p||ers Hu|t|p||ers
PowerP6 PowerP6
Rocket|0 Rocket|0
FPCA Fabr|c
|ock RAH
8e|ect|0
X6|TE Techno|ogy
06H
Embedded
Hu|t|p||ers
FPCA Fabr|c FPCA Fabr|c
|ock RAH |ock RAH
8e|ect|0 8e|ect|0
X6|TE Techno|ogy X6|TE Techno|ogy
06H 06H
Embedded Embedded
Hu|t|p||ers Hu|t|p||ers
FPCA Fabr|c
|ock RAH
FPCA Fabr|c FPCA Fabr|c
|ock RAH |ock RAH
FPCA Fabr|c FPCA Fabr|c FPCA Fabr|c
C|ue Log|c
|ock Log|c
8ystem P|atform
P|atform
Xi|inx
Xi|inx
Vir|cx
Vir|cx
-
-
|| Prc |PGA
|| Prc |PGA
Sc||ing |nc S|andard in Prcgrannao|c |cgic
Sc||ing |nc S|andard in Prcgrannao|c |cgic
h|gh performance true
dua|-port RAH
8e|ect|0- U|tra
Techno|ogy
Advanced
FPCA Log|c
Embedded Xtreme08P
Funct|ona||ty
Rocket|0 and Rocket|0 X
h|gh-speed 8er|a| Transce|vers
PowerP6 Processors 400+
Hhz 6|ock Rate
X6|TE 0|g|ta||y
6ontro||ed |mpedance
06H 0|g|ta| 6|ock
Hanagement
Vir|cx
Vir|cx
-
-
|| Prc Mcncrq Hicrarcnq
|| Prc Mcncrq Hicrarcnq
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Distributed RAM
True-Dual Port
Synchronous Block RAM
16k x 1
8k x 2
4k x 4
2k x 8/9
1k x 16/18
512 x 32/36
DRAM
Ultra-High Performance
External Memory Interfaces
00R-80RAH
80R-80RAH
RL0RAH
F6RAH
FPH
E00
SRAM
ZT 8RAH
00R-8RAH
8|gma RAH
8ynchronous
Asynchronous
Vir|cx
Vir|cx
-
-
|| Dcticc |ani|q
|| Dcticc |ani|q
Otcr 1 Mi||icn Otcr 1 Mi||icn Vir|cx Vir|cx- -|| Uni|s Snippcd! || Uni|s Snippcd!
0ver 10 H||||on V|rtex (A|| V|rtex, V|rtex-E, V|rtex-||, V|rtex-|| Pro} 0ev|ces 8h|pped
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Rcccnfigurao|c scniccnduc|cr nar|c| Rcccnfigurao|c scniccnduc|cr nar|c|
Xilinx
42%
Altera
37%
Lattice
15%
Actel
6%
Top 4 PLD Manufacturers 2000
total: $3.7 Bio
[] $7 biIIion by Z003.
PLD vendors' ond fheir oIIionces provide Iibrories of "soff IPs"
fosfesf growing semiconducfor morkef segmenf
FPGA
FPGA
-
-
Gate
Gate
Array
Array
Programmable FPGA Gate Array
Lower unit cost
Custom Product
Months to manufacture
Slow Time to Market
NRE+
Customer specific
User Test Development
Simulation Critical
No In-Circuit verification
Higher unit cost
Standard Product
Off the shelf delivery
Fast Time to Market
No Non-Recurring Eng. Fee
No inventory risk
Fully factory tested
Simulation helpful
In-Circuit verification
(-)
(+)
(+)
(+)
(+)
(+)
(+)
(+)
(+)