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TO-220FP
Extremely high dv/dt capability 100% avalanche tested Gate charge minimized Very low intrinsic capacitances Very good manufacturing repeatibility
TO-247
Description
The SuperMESH series is obtained through an extreme optimization of STs well established stripbased PowerMESH layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh products.
Applications
Switching application
Order codes
Part number STF5NK100Z STP5NK100Z STW5NK100Z Marking F5NK100Z P5NK100Z W5NK100Z Package TO-220FP TO-220 TO-247 Packaging Tube Tube Tube
August 2006
Rev 4
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www.st.com 16
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Protection features of gate-to-source zener diodes . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Electrical characteristics (curves) ............................ 7
3 4 5
Test circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Electrical ratings
Electrical ratings
Table 1.
Symbol
Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC=100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor 3.5 2.2 14 125 1
1000 30
Gate source ESD (HBM-C=100pF, R=1.5) Peak diode recovery voltage slope Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1s; Tc= 25C) Operating junction temperature Storage temperature
-55 to 150
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD 3.5A, di/dt 200A/s, VDD V(BR)DSS, Tj TJMAX.
Table 2.
Symbol
Thermal data
Parameter TO-220 TO-247 Value TO-220FP 4.2 62.5 300 C/W C/W C Unit
Rthj-case Rthj-a Tl
Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose
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Electrical ratings
Table 3.
Symbol IAR EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) Single pulse avalanche energy (starting Tj=25C, Id=Iar, Vdd=50V) Value 3.5 250 Unit A mJ
Table 4.
Symbol BVGSO
1.1
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Electrical characteristics
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Test conditions ID = 1mA, VGS= 0 VDS = Max rating, VDS = Max rating, Tc = 125C Min. 1000 1 50
10
Typ.
Max.
Unit V A A A V
IDSS
Gate body leakage current VGS = 20V (VGS = 0) Gate threshold voltage Static drain-source on resistance VDS = VGS, ID = 100A VGS = 10V, ID = 1.75 A 3 3.75 2.7
4.5 3.7
Table 6.
Symbol gfs (1) Ciss Coss Crss Cosseq(2). td(on) tr td(off) tf Qg Qgs Qgd
Dynamic
Parameter Test conditions Min. Typ. 4 1154 106 21.3 46.8 22.5 7.7 51.5 19 42 7.3 21.7 59 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
Forward transconductance VDS =15V, ID = 1.75A Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Turn-on delay time Rise time Off-voltage rise time Fall time Total gate charge Gate-source charge Gate-drain charge
VGS=0, VDS =0V to 800V VDD=500 V, ID= 1.75 A, RG=4.7, VGS=10V (see Figure 20) VDD=800V, ID = 3.5 A VGS =10V (see Figure 21)
1. Pulsed: pulse duration=300s, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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Electrical characteristics
Table 7.
Symbol ISD ISDM VSD
(1) (2)
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Electrical characteristics
2.1
Figure 1.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
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Figure 9.
Transconductance
Figure 11. Gate charge vs gate-source voltage Figure 12. Capacitance variations
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STP5NK100Z - STF5NK100Z - STW5NK100Z Figure 13. Normalized gate threshold voltage vs temperature
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Test circuit
Test circuit
Figure 19. Unclamped Inductive waveform
Figure 22. Test circuit for inductive load switching and diode recovery times
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DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7
L3 L6 L7
F1 F
G1 H
F2
L2 L5
E
1 2 3
L4
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P
Q
13/16
DIM. A A1 b b1 b2 c D E e L L1 L2 P R S
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Revision history
Revision history
Table 8.
Date 12-Oct-2004 08-Sep-2005 16-Dec-2005 16-Aug-2006
Revision history
Revision 1 2 3 4 First release Complete datasheet Inserted ecopack indication New template, no content change Changes
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