Data Sheet

CE-188A

CE-188A

Features
? ? ? ? ? ? ?

16 bit x86 compatible CPU 512KB Flash 128KB SRAM 32 IO lines from CPU 1 RS-232, 1 TTL UART interface 8 external interrupt inputs 3 16-bit timer/counters

? ? ? ? ? ?

High speed CAN interface option In-circuit programmable GAL option 2 PWD inputs Single 5V power supply input CEImon Flash loader/development utility Small footprint 1.75 X 2.75

Applications
? ? ? ?

Global Embedded applications Point-of-sale terminals Industrial control systems Vending & gaming machines

? ? ? ?

Security Systems Remote monitoring & control Remote telemetry and SCADA OEM applications

Functional Description
The CE-188A is a complete, low cost, single board computer. The high performance, 16 bit x86 compatible processor makes software development fast and easy. The CE-188A is perfect for applications requiring a compact, robust and flexible solution. The CE-188A comes with an on-board monitor utility CEImon. This monitor can be used to read or write virtually any memory or IO address location during development. CEImon is also used to load binary images into flash or manually access memory or IO peripherals. The CE-188A has one RS-232 and one TTL serial port. A complete high speed CAN option is available.

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CE-188A Datasheet

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Mechanical Outline

CE-188A

Mechanical
The CE-188A module is on an 0.062 thick FR-4 PC board. It is only 1.75 x 2.75. Due to the low mass of the board and large headers, no retention is required aside from the sockets. A pair of mounting holes are provided to insure retention in high shock or vibration environments, if desired.

Power Requirements
Power Supply: Current: Maximum (with CAN option): Maximum (standard): Power save mode (CAN option): Power save mode (standard): 5V 5% 260 mA 130 mA 40 mA 30 mA

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Data Sheet
Header pin connections
Power / CAN / RS-232

CE-188A

J4 contains all of the critical IO to supply power to and communicate with the CE-188A. The optional high speed CAN controller IO is also on this header.
J4 TXD0B# GND CAN_TERM0 CANL 1 3 5 7 9 2 4 6 8 10 RXD0B# VCC GND CAN_TERM1 CANH

RS-232/CAN/Power

Memory Bus J1 brings out the full address and data bus of the CE-188A. A male vertical header may be populated on non-flash boards for rapid firmware development. In this configuration, an ALPTEX IE ROM emulator may be directly connected to the CE-188A. Contact CEI for options and availability. NOTE: Do not connect pins 1, 2, 3, 4, 23 and 34. They are for emulator use only.
J1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VCC 26 24 22 20 18 16 14 12 13 15 21 17 10 11 9 8 6 7 5 4 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 D0 D1 D2 D3 D4 D5 D6 D7 28 30 32 33 31 29 27 25 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

CE# OE#

23 19

UCS# RD#

VCC GND GND

3 34 1

VCC

Memory Bus

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IO and Auxiliary connections

CE-188A

J2 contains alternative power connections, programmable IO, chip selects and other processor features. Pins 34, 38 or 49 are reserved for future use. Do not connect anything to these pins. Pins 2 though 6 are not connected on the CE-188A. The CE-188A requires a single 5V power supply. Note that some of the IO pins are connected to two locations on the header. This is to maintain compatibility with other CEI single board computers. To use the signal as a chip select, pins 45 through 48. To use these signals as IO, connect them to the pins below 31. CSOUT1#, CSOUT2# and CSOUT3# are available only on CAN models.
J2 VCC ADEN# P22 P21 P12 P11 P1 P25 P16 P18 P3 P15 P5 P6 CSOUT2# CSOUT1# RD# RES# NMI INT1 P18 P16 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 +5V -5V +3.3V -3.3V +12V -12V ALE ADEN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 INT0 INT1 INT2 INT3 PCS0# PCS1# PCS2# PCS3# RDY GND IO and Control 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

ALE P20 P23 P26 P13 P10 P0 P24 P17 P19 P2 P14 P4 CSOUT3# WR# INT0 INT3 P19 P17

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Memory Map

CE-188A

During boot, CEImon uses SRAM for configuration and boot options. Once the processor has been initialized and control is passed to the user application at 0x80000, all SRAM is available to the application. Memory Map: F0000 FFFFF 80000 EFFFF 20000 7FFFF 00000 1FFFF CEImon FLASH Available SRAM

If the CAN model is ordered, the SJA1000 CAN controller base address is at IO address 0x0000. Otherwise, the IO bus is completely available for user access. IO Memory Map: FF00 FFFF AM186ES peripheral registers 0100 FEFF Available for user applications 0000 00FF (optional) CAN 2.0B

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Getting Started

CE-188A

The CE-188A is designed with rapid development in mind. No software is required to test new IO or memory based IO peripherals. CEImon allows the user to read or write virtually any memory or IO address. To access CEImon, start a terminal emulator at 19,200 baud, 8 data bits, 1 stop bit, no parity and no flow control.

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CE-188A

While Holding down the - key on the keyboard, reset or cycle power to the CE-188A. CEImon looks for a --- input on its RS-232 port to boot into the monitor application. If the input is not detected within about 1 second, CEImon will attempt to jump to the user application at address 0x80000.

Pressing the Enter key at the CE> will display the list of available commands. See CEImon Command Reference later in this document. At the CE> prompt you can read or write most IO or memory locations.

Care should be taken when changing IO configuration, serial port or any SRAM memory location as they may cause the system to crash. If this happens, reset or cycle power to the CE-188A as described at the beginning of this section. CEImon pre-configures the Flash and SRAM chip selects automatically. There is no need to reinitialize those registers in your application.

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CEImon Command Reference
IOWRITE <hex address> <hex value> - Writes a single byte to the specified IO address. IOREAD <hex address> - Reads a single byte to the specified IO address. WRITE <hex address> <hex value> - Writes a single byte to the specified memory address. READ <hex address> <number of bytes to read> - Reads the specified number of bytes from the specified memory address. FWRBYT <hex address> <hex value> - Writes a single byte to the specified Flash address. FERRALL

CE-188A

- Erases all unprotected sectors in the flash. CEImon resides in a protected sector and cannot be erased. FDEVCOD - Returns the flash manufactures device code. FMANCOD - Returns the flash manufactures code. FSECER <sector> - Erases the specified flash sector. The top sector in the CE-188A is protected and cannot be erased.

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Programming

CE-188A

Programming the CE-188A is simple and straight forward. CEImon sets up the Flash and SRAM chip selects before jumping to user code. Any compiler capable of creating a binary image may be used to create applications. The development kit is shipped with a special version of the HiTech Pacific C compiler with ROM extensions. Creating a project using UltraEdit-32 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. Select Project -> New Project from the menu and name it CE-188A. At the Project window, click Open. Create a new file and save it as CE-188A.C. Select Project -> Files/Settings. Select Add File and add CE-188A.C to the project. Add MAIN.C, SIO.C and SIO.H from the Demo directory to the project in the same way. Click Open to get back to the project page. On the left side of the window, change from Open Files to Project Files. This will show all of the files associated with the project. Go to Advanced->Select Compiler. Select Pacific C, Application, then click OK. Go to Advanced->Project Settings. Change Target and Command Line Arguments to .bin extensions. They default to .exe. Change Output Type to Binary. Change ROM Code to yes. Change the ROM Address to 80100. Change Reset Address to 80000. Change Processor Type to 80186. Set the Memory Model to large. Last, change Build Mode to Release Mode. Select View->Views/Lists->Output Window.

Click OK. To build the project, simply go to Advanced->Build or Advanced->Rebuild All. Once complete, the output window should display something similar the following:

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FreeLoader

CE-188A

Now that youve designed and debugged your hardware using CEImon ROM monitor from the previous section, your ready to start writing and debugging your application software. This is where FreeLoader comes in. FreeLoader is used to download a binary image into the CE-188As flash memory. FreeLoader is a Windows utility for loading binary images into the CE-188A. The utility is simple and straight forward to use: 1. 2. 3. 4. 5. 6. Connect the serial RS-232 port on the CE-188A to a serial port on a PC. Start the FreeLoader utility software. Select the binary image to load. From the menu, set the serial port, and set the baud rate to 19200 baud. Click the Load Flash button. Connect power or reset the CE-188A.

When the utility completes, the new application will be loaded and ready to go. Simply reset the CE-188A to run your application. If at any time during the download you want to break out, press <CTRL><BREAK>.

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Data Sheet

CE-188A

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Processor Information

CE-188A

The CE-188A is based on the high performance RDC8830 processor. The RDC8830 is pin compatible with the AM188ES (80x188) processor running at 40MHz. This section does not provide all information on the processor, but is intended to provide information on features supported by the CE-188A. Refer to the RDC8830 datasheet for additional information. Processor Release Level This register defines the processor manufacturer and version.
Processor Release Level Register 15 14 13 12 Processor Release Level 11 10 9 8 7 1 6 1 5 0 4 1 3 1 Address: 0xFFF4 2 0 1 0 0 1

Read Only Register specifying the processor release level and manufacturer identity Bits 15-8

Processor Version 0x01 = version A: 0x02 = version B: 0x03 = version C Manufacturer Identity D9 = RDC 01 = AMD

Bit 7-0

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Auxiliary Connection Register

CE-188A

This register defines the programmable pins that are not associated with the Programmable IO (PIO) module. Be sure to set bits 3 through 0 to 0 for the CE-188A.
Auxiliary Connection Register 15 14 13 12 11 Reserved 10 9 8 7 6 ENRX1 5 RTS1 4 ENRX0 3 RTS0 Address: 0xFFF2 Reset Value: 0x0000 2 LSIZ 1 MSIZ 0 IOSIZ

Read Only Register specifying the processor release level and manufacturer identity Bit 15 - 7 Bit 6

Reserved

ENRX1

Enable Receiver request for Serial port 1. 1 = CTS1/ENRX1 set to ENRX1 0 = CTS1/ENRX1 set to CTS1

Bit 5

RTS1

Enable Request to Send of Serial port 1 1 = RTR1/RTS1 set to RTS1 0 = RTR1/RTS1 set to RTR1

Bit 4

ENRX0

Enable Receiver request for Serial port 0 1 = CTS0/ENRX0 set to ENRX0 0 = CTS0/ENRX0 set to CTS0

Bit 3

RTS0

Enable Request to Send of Serial port 0 1 = RTR0/RTS0 set to RTS0 0 = RTR0/RTS0 set to RTR0

Bit 2 Bit 1 Bit 0

LSIZ

Set to 0

MSIZ

Set to 0

IOSIZE

Set to 0

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Power Save Control Register

CE-188A

This register defines the power save configuration. The MCS0# setting is also embedded in this register. When PSEN is set to 1, the processor clock is divided by the value in F2-F0. The processor then continues to run at the slower clock rate. This reduces power consumption and heat dissipation, which can reduce power supply costs and size as well as improve battery life in portable systems. NOTE: Clock dependent devices will need to be reprogrammed for the clock frequency changes.
Power Save Control Register Address: 0xFFF0 Reset Value: 0x0000 11 0 10 1 9 0 8 1 7 0 6 0 5 0 4 0 3 0 2 F2 1 F1 0 F0

15 PSEN

14 MCSB

13 0

12 0

Bit 15

PSEN

Enable Power Save Mode This bit is cleared by hardware when an external interrupt occurs Software interrupts do not change this bit. 1 = Enable Power save and divide the internal clock by the value in F2F0. MCS0# control bit. 0 = MCS0# operates normally 1 = MCS0# is active over the entire MCSx# Range

Bit 14

MCSB

Bit 13-11 Bit 10 Bit 9 Bit 8 Bit 7-3 Bit 2-0

Reserved Reserved Reserved Reserved Reserved F2 - F0 Clock Divisor Select. F2 0 0 0 0 1 1 1 1 F1 0 0 1 1 0 0 1 1 F0 0 1 0 1 0 1 0 1 ------------------Divide Factor Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 Set to 1 for normal operation Set to 1 for normal operation

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Watchdog Register

CE-188A

A Watchdog timer is used to make sure the processor hasnt crashed or become stuck in a loop. When enabled, the user software must periodically reset the Watchdog by writing the following sequence to address 0xFFE6: 0x3333 0xCCCC This sequence must also be written before writing the watchdog register. To read from the Watchdog timer register, the following sequence must be written: 0x5555 0xAAAA The current count should be reset before modifying the Watchdog timer timeout period to ensure that an immediate timeout does not occur. CEImon disables the Watchdog timer at reset.

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CE-188A

Watchdog Timer Control Register

Address: 0xFFE6 Reset Value: 0xC080 11 10 9 RES Enable Watchdog Timer 1 = Enable Watchdog timer 0 = Disable Watchdog timer Watchdog Reset 1 = WDT generates a system reset when the WDT timeout count is reached. 0 = WDT generates an NMI interrupt when WDT timeout count is reached if the NMIF bit is 0. If the NMIF bit is 1, the WDT will generate a system reset upon timeout. Reset Flag When the watchdog timer reset event has occurred, hardware will set this bit to 1. This bit will be cleared by any keyed sequence write to this register or external reset. This bit is 0 after external reset or 1 after watchdog timer reset. NMI Flag After the watchdog generates an NMI interrupt, this bit will be set to 1 by hardware. This bit is cleared by any keyed sequence write to this register. 8 7 6 5 4 3 2 1 0 COUNT

15 ENA Bit 15

14 WRST

13 RSTF

12 NMIF

ENA

Bit 14

WRST

Bit 13

RSTF

Bit 12

NMIF

Bit 11-8 Bit 7-0

Reserved COUNT Timeout Count The COUNT settings determine the duration of the watchdog timer timeout interval. Duration = 2Exponent / Frequency The Exponent of the COUNT setting: Bit 7 Bit 0 0 0 0 0 0 0 0 0 N/A x x x x x x x x 10 x x x x x x 1 0 20 x x x x x 1 0 0 21 x x x x 1 0 0 0 22 x x x 1 0 0 0 0 23 x x 1 0 0 0 0 0 24 x 1 0 0 0 0 0 0 25 1 0 0 0 0 0 0 0 26

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Chip Selects

CE-188A

The processor contains logic to create chip selects for both memory and IO devices. The logic can be programmed to provide ready or wait-state generation. The chip selects are active for all memory and IO cycles in their programmed areas. Six Chip Selects are available for memory and another six for memory or IO peripherals. Each peripheral chip select addresses a 256 byte block offset from a programmable base address. The upper and lower memory chip selects are omitted from this section as they are configured by CEImon before turning control over to the user application. Midrange Memory Chip Select Register This register controls the MCS3#-MCS0# chip selects. These chip selects must be programmed to be between 0x20000 and 0x7FFFF (between SRAM and Flash memory boundaries). They cannot overlay SRAM or Flash memory ranges. The midrange memory chip selects are programmed through two registers. The Midrange Memory Chip Select register determines the base address, ready condition and wait states of the memory block accessed through the MCS# pins. Both registers must be accessed with a read to activate the configured chip selects. The MCS address signals assert with the multiplexed address bus.
Midrange Memory Chip Select Register 15 14 13 12 BA19 BA13 11 10 9 8 1 7 1 6 1 5 1 4 1 3 1 Address: 0xFFA6 Reset Value: ----2 R2 1 R1 0 R0

Bit 15 9

Base Address

These correspond to bits 19 - 13 of the 1M byte address space programmable base address of the MCS# address block Bits 12 - 0 of this address space are always 0. MCS# address range must be between 0x20000 and 0x80000 (not overlap RAM or Flash memory space)

Bit 8 - 3 Bit 2

Reserved Ready Mode. This bit is configured to enable/disable the wait states inserted for the MCS# chip selects. The R1, R0 bits of this register determine the number of wait states to insert. 1 = External Ready is ignored 0 = External Ready is required Wait State value R1 R0 --0 0 --0 1 --1 0 --1 1 ---

R2

Bit 1 - 0

Wait States

Waits 0 1 2 3

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Auxiliary Chip Select Register This register controls the MCS# and PCS# chip selects.
PCS# and MCS# Auxiliary Register

CE-188A

Address: 0xFFA8 Reset Value: ----9 8 7 EX 6 MS 5 1 4 1 3 1 2 R2 1 R1 0 R0

15 1 Bit 15

14

13

12 M6 M0

11

10

Reserved MCS# Block Size This determines the total block size for the MCS3# - MCS0# chip selects. Each chip select is active for one quarter of the total block size Total M6MCSx# Address Block M0 Size Active Range 0000001b 8k 2k 0000010b 16k 4k 0000100b 32k 8k 0001000b 64k 16k 0010000b 128k 32k 0100000b 256k 64k 1000000b 512k 128k

Bit 14 - 8

M6 - M0

Bit 7

EX

Pin Selector This bit configures the multiplexed output which the PCS6# and PCS5# pins as chip selects or A2-A1 1 = PCS6# and PCS5# are configured as peripheral chip select pins. 0 = PCS6# is configured as address bit 2, PCS5# is configured as address bit 2.

Bit 6

MS

Memory or I/O Space selector 1 = PCSx# pins are active for memory bus cycle. 0 = PCSx# pins are active for I/O bus cycle.

Bit 5-3 Bit 2

Reserved

R2

Ready Mode. This bit configures the ready/wait state enable/disable feature. 1 = External ready ignored. 0 = External ready is required. Wait State value R1 R0 --0 0 --0 1 --1 0 --1 1 ---

Bit 1 - 0

Wait States

Waits 0 1 2 3

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Peripheral Chip Select Register

CE-188A

The PCS# outputs assert with the same timing as the multiplexed address bus. Each peripheral chip select asserts over a 256 byte address range. PCS4# is not available on the CE-188A.
Peripheral Chip Select Register Address: 0xFFA4 Reset Value: ----10 9 8 7 6 1 5 1 4 1 3 R3 2 R2 1 R1 0 R0

15

14

13

12

11 BA19BA14

Bit 15 7

BA19BA11

Base Address. Corresponds to address bits 19-11 of the address bus. of the PCS# peripheral chip select block. When the PCS# chip selects are mapped to I/O space, BA19 - BA16 must be set to 0000b.

Bit 14 8

M6 - M0

MCS# Block Size This determines the total block size for the MCS3# - MCS0# chip selects. Each chip select is active for one quarter of the total block size Total Block MCSx# Address Active Range M6-M0 Size 0000001b 8k 2k 0000010b 16k 4k 0000100b 32k 8k 0001000b 64k 16k 0010000b 128k 32k 0100000b 256k 64k 1000000b 512k 128k

Bit 7

EX

Pin Selector This bit configures the multiplexed output which the PCS6# and PCS5# pins as chip selects or A2-A1 1 = PCS6# and PCS5# are configured as peripheral chip select pins. 0 = PCS6# is configured as address bit 2, PCS5# is configured as address bit 2.

Bit 6

MS

Memory or I/O Space selector 1 = PCSx# pins are active for memory bus cycle. 0 = PCSx# pins are active for I/O bus cycle.

Bit 6-4 Bit 3, 10

Reserved

Wait State value Wait State value R3 R1 0 0 0 0 0 1 0 1 1 0

R0 0 1 0 1 0

-------------

Waits 0 1 2 3 5

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1 1 1 Bit 2 0 1 1 1 0 1 ------7 9 15

CE-188A

R2

Ready Mode. This bit configures the ready/wait state enable/disable feature. 1 = External ready ignored. 0 = External ready is required.

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Interrupt Controller
The RDC8830 processor can receive interrupts from internal and external sources. arranges the priority of these signals.

CE-188A

The processor hardware

There are up to eight external interrupt sources on the RDC8830. Five maskable interrupt pins (INT6, INT5, INT3, INT1,INT0) and one nonmaskable interrupt (NMI) pin. There are eight internal interrupt sources that are not connected to external pins. They are used for the three timers, two DMA channels, two serial ports, and the watchdog timer NMI. INT 5 and INT 6 are multiplexed with DRQ0 and DRQ1 respectively. They are available if the DMA is not enabled or is being used with internal synchronization. INT3, INT1 and INT0 can be either edge or level triggered. INT6 and INT5 are edge triggered only. An external interrupt controller can be used as the system master by programming the internal interrupt controller to operate in slave mode. INT6-INT4 are not available in this mode. Interrupts are automatically disabled when an interrupt is taken. Interrupt-service routines may re-enable interrupts by setting the IF flag. This allows interrupts of greater or equal priority to interrupt the currently executing ISR. Interrupts from the same soured are disabled as long as the corresponding bit in the interrupt in-service register is set. Interrupt Type An 8-bit interrupt type identifies each of the 256 possible interrupts. Software exceptions, internal peripherals, and non-cascaded external interrupts supply the interrupt type through the internal interrupt controller. Interrupt Vector Table The interrupt vector table is a memory area of 1 Kbyte beginning at address 0x00000 that contains up to 256 fourbyte memory address pointers to interrupt handlers for each interrupt type. For each interrupt, and 8-bit interrupt type identifies the interrupt vector table entry. Interrupts 0x00 to 0x1F are reserved. Maskable and Nonmaskable Interrupts A maskable interrupt is an interrupt that can be configured to be ignored. This does not mean that the interrupt event does not occur, or that it is not set in the flags register. It means that the interrupt handler is not called when the event is called. Interrupt types 0x08 through 0x1F are maskable. Of these, only 0x08 through 0x14 are in use. There is a period of time when writing the interrupt mask register that all interrupts may be temporarily be enabled. This can cause an interrupt to occur in spite of them being masked. Always disable interrupts before writing the interrupt mask register to avoid masked interrupts from being accepted. The only interrupts that cannot be masked are the NMI and software interrupts. These are serviced regardless of the interrupt enable status.

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Interrupt Handling

CE-188A

When an interrupt is requested, the controller determines if it is enabled (not masked) and that there are no higher priority interrupts being serviced or pending. When a valid interrupt is requested, the interrupt controller jumps to a 4-byte vector in the interrupt vector table. The vector table is available in the first 1K of memory space (0x0000 to 0x003FF). The vector is used to jump to the location in memory of the program that will service the interrupt. More information on interrupts is available in the RDC8830 datasheet. Interrupt Registers Following are the registers that control the function of the interrupt signals.
Serial Port 0 Interrupt Control Register Address: 0xFF44 Reset Value: 0x000F 9 8 7 6 5 4 1 3 MSK 2 PR2 1 PR1 0 PR0

15

14

13

12

11

10 Reserved

(Master Mode) Bit 15 - 4 Bit 3 Reserved

MSK

Mask 1 = Mask the interrupt source for asynchronous serial port 0. 0 = Enable Serial Port 0 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

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Data Sheet
Serial Port 1 Interrupt Control Register

CE-188A
Address: 0xFF42 Reset Value: 0x000F

15

14

13

12

11

10 Reserved

4 1

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15 - 4 Bit 3 Reserved

MSK

Mask 1 = Mask the interrupt source for asynchronous serial port 1. 0 = Enable Serial Port 1 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

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DMA 1 / INT6 Interrupt Control Register

CE-188A
Address: 0xFF36 Reset Value: 0x000F

15 0

14 0

13 0

12 0

11 0

10 0

9 0

8 0

7 0

6 0

5 0

4 0

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for DMA1. 0 = Enable DMA1 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

(Slave Mode), Reset value: 0x0000 Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for DMA 1. 0 = Enable DMA 1 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

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Data Sheet
DMA 0 / INT5 Interrupt Control Register

CE-188A
Address: 0xFF34 Reset Value: 0x000F

15 0

14 0

13 0

12 0

11 0

10 0

9 0

8 0

7 0

6 0

5 0

4 0

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for DMA0. 0 = Enable DMA0 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

(Slave Mode), Reset value: 0x0000 Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for DMA 0. 0 = Enable DMA 0 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

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Timer Interrupt Control Register

CE-188A
Address: 0xFF32 Reset Value: 0x000F

15 0

14 0

13 0

12 0

11 0

10 0

9 0

8 0

7 0

6 0

5 0

4 0

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for the timer controller. 0 = Enable the timer controller interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

(Slave Mode), Reset value: 0x0000 Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for the timer controller. 0 = Enable the timer controller interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 2 - 0

PR2-PR0

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CE-188A Datasheet

Data Sheet
INT 3 Control Register

CE-188A
Address: 0xFF3E Reset Value: 0x000F

15

14

13

12

11 Reserved

10

7 ETM

4 LTM

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15-8,6-5 Bit 7 Reserved ETM Edge-Trigger Enable. When this bit is set to 1 and bit 4 is set to 0, interrupt is triggered on the low to high edge. Level-triggered Mode. 1 = Interrupt is triggered by high active level. 0 = Interrupt is triggered by low to high edge. Mask 1 = Mask the interrupt source for INT3. 0 = Enable INT3 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 4

LTM

Bit 3

MSK

Bit 2 - 0

PR2-PR0

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CE-188A Datasheet

Data Sheet
INT 2 Control Register

CE-188A
Address: 0xFF3C Reset Value: 0x000F

15

14

13

12

11 Reserved

10

7 ETM

4 LTM

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15-8,6-5 Bit 7 Reserved ETM Edge-Trigger Enable. When this bit is set to 1 and bit 4 is set to 0, interrupt is triggered on the low to high edge. Level-triggered Mode. 1 = Interrupt is triggered by high active level. 0 = Interrupt is triggered by low to high edge. Mask 1 = Mask the interrupt source for INT2. 0 = Enable INT2 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 4

LTM

Bit 3

MSK

Bit 2 - 0

PR2-PR0

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CE-188A Datasheet

Data Sheet
INT 1 Control Register

CE-188A
Address: 0xFF3A Reset Value: 0x000F

15

14

13

12

11 Reserved

10

7 ETM

6 SFNM

5 C

4 LTM

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15-8 Bit 7 Reserved ETM Edge-Trigger Enable. When this bit is set to 1 and bit 4 is set to 0, interrupt is triggered on the low to high edge. Special Fully Nested Mode, Set to 1 to enable. Cascade Mode. Set to 1 to enabled Cascade mode for INT0 or INT1. Level-triggered Mode. 1 = Interrupt is triggered by high active level. 0 = Interrupt is triggered by low to high edge. Mask 1 = Mask the interrupt source for INT1. 0 = Enable INT1 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 6 Bit 5 Bit 4

SFNM C LTM

Bit 3

MSK

Bit 2 - 0

PR2-PR0

(Slave Mode), This register is for timer 2 interrupt control. Reset value: 0x0000 Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for timer 2. 0 = Enable timer 2 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2

Bit 2 - 0

PR2-PR0

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CE-188A Datasheet

Data Sheet
0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 ----------3 4 5 6 7

CE-188A

Low

Page 30 of 61
2004, Copeland Electronics, Inc.
CE-188A Datasheet

Data Sheet
INT 0 Control Register

CE-188A
Address: 0xFF38 Reset Value: 0x000F

15

14

13

12

11 Reserved

10

7 ETM

6 SFNM

5 C

4 LTM

3 MSK

2 PR2

1 PR1

0 PR0

(Master Mode) Bit 15-8 Bit 7 Reserved ETM Edge-Trigger Enable. When this bit is set to 1 and bit 4 is set to 0, interrupt is triggered on the low to high edge. Special Fully Nested Mode, Set to 1 to enable. Cascade Mode. Set to 1 to enabled Cascade mode for INT0 or INT1. Level-triggered Mode. 1 = Interrupt is triggered by high active level. 0 = Interrupt is triggered by low to high edge. Mask 1 = Mask the interrupt source for INT0. 0 = Enable INT0 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2 0 1 1 --3 1 0 0 --4 1 0 1 --5 1 1 0 --6 1 1 1 --7 Low

Bit 6 Bit 5 Bit 4

SFNM C LTM

Bit 3

MSK

Bit 2 - 0

PR2-PR0

(Slave Mode), This register is for timer 1 interrupt control. Reset value: 0x0000 Bit 15-4 Bit 3 Reserved MSK Mask 1 = Mask the interrupt source for timer 1. 0 = Enable timer 1 interrupt. Priority. These bits determine the priority of the serial port relative to other interrupt sources. Priority Selection: PR2 PR1 PR0 --Priority 0 0 0 --0 High 0 0 1 --1 0 1 0 --2

Bit 2 - 0

PR2-PR0

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CE-188A Datasheet

Data Sheet
0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 ----------3 4 5 6 7

CE-188A

Low

Interrupt Status Register 15 DHLT 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 MSK

Address: 0xFF30 Reset Value: ---2 TMR2 1 TMR1 0 TMR0

(Master Mode) Bit 15 DHLT DMA Halt 1 = Halts any DMA activity. When non-maskable interrupts occur. 0 = When an IRET instruction is executed.

Bit 14-3

Reserved TMR2TMR0

Bit 2 - 0

1 = corresponding timer has an interrupt request pending.

(Slave Mode), Reset value: 0x0000 Bit 15 DHLT DMA Halt 1 = Halts any DMA activity. When non-maskable interrupts occur. 0 = When an IRET instruction is executed.

Bit 14-3

Reserved TMR2TMR0

Bit 2 - 0

1 = corresponding timer has an interrupt request pending.

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CE-188A Datasheet

Data Sheet
Interrupt Request Register 15 14 13 Reserved 12 11 10 SP0 9 SP1 8 I4 7 I3 6 I2 5 I1 4 I0 3 D1/I6

CE-188A
Address: 0xFF2E Reset Value: ---2 D0/I5 1 Res 0 TMR

(Master Mode) The interrupt request register is a read-only register. For internal interrupts (SP0, SP1, D1/I6, D0,I5, TMR). The corresponding bit is set to a 1 when a device requests an interrupt. The bit is reset during internally generated interrupt acknowledge. The INT4-INT0 bits reflect the current value of the external signal (I4-I0). Bit 15-11 Bit 10 Bit 9 Bit 8-4 Reserved SP0 SP1 I4-I0 Serial Port 0 Interrupt request. Serial Port 1 Interrupt request. Interrupt Requests 1 = corresponding INT pin has an interrupt pending. DMA channel or INT interrupt request 1 = corresponding DMA channel or INT pin has an interrupt pending.

Bit 3-2

D1/I6-D0/I5

Bit 1 Bit 0

Reserved TMR Timer Interrupt request. 1 = The timer control unit has an interrupt request pending.

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CE-188A Datasheet

Data Sheet
In-Service Register

CE-188A
Address: 0xFF2C Reset Value: 0x0000

15

14

13 Reserved

12

11

10 SP0

9 SP1

8 I4

7 I3

6 I2

5 I1

4 I0

3 D1/I6

2 D0/I5

1 Res

0 TMR

(Master Mode) The bits in the INSERV register are set by the interrupt controller when the interrupt is taken. Each bit in the register is cleared by writing the corresponding interrupt type to the EOI register. Bit 15-11 Bit 10 Reserved

SP0

Serial Port 0 Interrupt in-service. 1 = the serial port 0 interrupt is currently being serviced. Serial Port 1 Interrupt in-service. 1 = the serial port 1 interrupt is currently being serviced. INT Interrupt in-service. 1 = the corresponding INT interrupt is currently being serviced. DMA channel or INT interrupt in-service. 1 = the corresponding DMA or INT interrupt is currently being serviced.

Bit 9

SP1

Bit 8-4

I4-I0

Bit 3-2

D1/I6-D0/I5

Bit 1 Bit 0

Reserved TMR Timer Interrupt in-service. 1 = the Timer interrupt is currently being serviced.

In-Service Register

Address: 0xFF2C Reset Value: 0x0000 12 11 10 Reserved 9 8 7 6 5 TMR2 4 TMR1 3 D1 2 D0 1 Res 0 TMR0

15

14

13

(Slave Mode) The bits in the INSERV register are set by the interrupt controller when the interrupt is taken. Each bit in the register is cleared by writing the corresponding interrupt type to the EOI register. Bit 15-6 Bit 5-4 Reserved TMR2-TMR1 Timer2, Timer1 interrupt in-service 1 = the corresponding TMR interrupt is currently being serviced. DMA channel or INT interrupt in-service. 1 = the corresponding DMA or INT interrupt is currently being serviced.

Bit 3-2

D1/I6-D0/I5

Bit 1 Bit 0

Reserved TMR0 Timer 0 Interrupt in-service. 1 = the Timer 0 interrupt is currently being serviced.

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CE-188A Datasheet

Data Sheet
Priority Mask Register 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0

CE-188A
Address: 0xFF2A Reset Value: 0x0007 2 PRM2 1 PRM1 0 PRM0

(Master Mode) Determines the minimum priority level at which maskable interrupts can generate an interrupt. Bit 15-3 Reserved PRM2PRM0

Bit 2-0

Priority Field Mask. Determines the minimum priority required for a maskable Interrupt source to generate an interrupt. Priority (High) 0 1 2 3 4 5 6 (Low) 7 PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1

(Slave Mode) Determines the minimum priority level at which maskable interrupts can generate an interrupt. Bit 15-3 Reserved PRM2PRM0

Bit 2-0

Priority Field Mask. Determines the minimum priority required for a maskable Interrupt source to generate an interrupt. Priority (High) 0 1 2 3 4 5 6 (Low) 7 PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1

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2004, Copeland Electronics, Inc.
CE-188A Datasheet

Data Sheet
Interrupt Mask Register

CE-188A
Address: 0xFF28 Reset Value: 0x07FD

15

14

13 Reserved

12

11

10 SP0

9 SP1

8 I4

7 I3

6 I2

5 I1

4 I0

3 D1/I6

2 D0/I5

1 Res

0 TMR

(Master Mode) Bit 15-11 Bit 10 Reserved

SP0

Serial Port 0 Interrupt Mask. The state of the interrupt mask bit for serial port 0. Serial Port 1 Interrupt Mask. The state of the interrupt mask bit for serial port 1. Interrupt Masks Indicates the state of the interrupt mask of the corresponding INT interrupt. DMA Channel or INT Masks Indicates the state of the interrupt mask of the corresponding DMA channel or INT interrupt.

Bit 9

SP1

Bit 8-4

I4-I0

Bit 3-2

D1/I6-D0/I5

Bit 1 Bit 0

Reserved TMR Timer Interrupt Mask. The state of the mask bit of the timer control unit.

Interrupt Request Register

Address: 0xFF28 Reset Value: 0x003D 11 10 9 Reserved 8 7 6 5 TMR2 4 TMR1 3 D1/I6 2 D0/I5 1 Res 0 TMR0

15

14

13

12

(Slave Mode) Bit 15-6 Bit 5-4 Reserved TMR2-TMR1 Timer 2 / Timer 1 Interrupt Mask. The state of the mask bit of the Timer Interrupt Control Register. 1 = Timer 2 / Timer 1 interrupt requests are masked. DMA Channel or INT Masks Indicates the state of the interrupt mask of the corresponding DMA channel or INT interrupt.

Bit 3-2

D1/I6-D0/I5

Bit 1 Bit 0

Reserved TMR0 Timer0 Interrupt Mask. Indicates the state of the interrupt mask of Timer 0.

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CE-188A Datasheet

Data Sheet
Poll Status Register 15 IREQ 14 13 12 11 10 9 Reserved 8 7 6 5 4 S4 3 S3

CE-188A
Address: 0xFF26 Reset Value: ---2 S2 1 S1 0 S0

(Master Mode) The Poll Status (POLLST) register mirrors the current state of the Poll register. The POLLST can be read without affecting the current interrupt request. Bit 15 IREQ Interrupt Request. 1 = Interrupt pending. S4 - S0 contain valid data.

Bit 14-5 Bit 4-0

Reserved S4-S0 Poll Status Indicates the Interrupt type of the highest priority pending interrupt.

End-Of-Interrupt 15 NSPEC (Master Mode) Bit 15 NSPEC Non-specific EOI 1 = indicates non-specific EOI 0 = indicates specific EOI type in S4-S0 14 13 12 11 10 9 Reserved 8 7 6 5 4 S4 3 S3

Address: 0xFF22 Reset Value: ---2 S2 1 S1 0 S0

Bit 14-5

Reserved S4S0

Bit 4-0

EOI Source Type Specifies the EOI interrupt currently being processed.

End-Of-Interrupt 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0

Address: 0xFF22 Reset Value: ---2 L2 1 L1 0 L0

(Slave Mode) Bit 153 Bit 2-0

Reserved L2-L0 Interrupt Type. Encoded value indicating the priority of the interrupt service bit to reset. Writes to these bits cause an EOI to be issued for the interrupt type in slave mode.

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CE-188A Datasheet

Data Sheet
Interrupt Vector Register 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 T4 6 T3 5 T2 4 T1 3 T0

CE-188A
Address: 0xFF20 Reset Value: ---2 0 1 0 0 0

(Slave Mode) Bit 15-8 Bit 7-3 Reserved T4-T0 Interrupt Type. Sets the five most significant bits of the interrupt types for the internal interrupt type. Interrupt type Timer 2 interrupt controller T4,T3,T2,T1,T0,1,0,1 Timer 1 interrupt controller T4,T3,T2,T1,T0,1,0,0 DMA 1 interrupt controller T4,T3,T2,T1,T0,0,1,1 DMA 0 interrupt controller T4,T3,T2,T1,T0,0,1,0 Timer 0 interrupt controller T4,T3,T2,T1,T0,0,0,0

Bit 2-0

Reserved

Page 38 of 61
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CE-188A Datasheet

Data Sheet
DMA Controller

CE-188A

DMA (Direct Memory Access) allows transfer of data between memory and peripherals without the CPUs involvement. The CE-188A has two independent DMA controllers. DMA sources can come from the serial channels, timer 2 or an external DRQ source. The DMA controller needs to know from where the transfer is coming, to where it is going, how many bytes to transfer and how (increment, decrement or neither for both from and to addresses). More information is available in the RDC8830 datasheet.
DMA Control Registers DMA0 Address: 0xFFCA Reset Value: 0xFFF9 14 DDEC 13 DINC 12 SM/IO 11 SDEC 10 SINC 9 TC 8 INT 7 SYN1 6 SYN0 5 P 4 TDRQ 3 Res 2 CHG 1 ST 0 B/W

15 DM/IO DMA1

Address: 0xFFDA Reset Value: 0xFFF9 14 DDEC 13 DINC DM/IO 12 SM/IO 11 SDEC 10 SINC 9 TC 8 INT 7 SYN1 6 SYN0 5 P 4 TDRQ 3 Res 2 CHG 1 ST 0 B/W

15 DM/IO Bit 15

Destination Address Space Select. 1 = The destination address is in memory space. 0 = The destination address is in IO space. Destination Decrement. 1 = The destination address automatically decrements after each transfer. The B/W bit determines the decrement value by 1 or 2. When both DDEC and DINC are 1, the address is constant. 0 = Disable the decrement function. Destination Increment. 1 = The destination address automatically increments after each transfer. The B/W bit determines the increment value by 1 or 2. 0 = Disable the increment function. Source Address space select. 1 = The source address is in memory space. 0 = The source address is in IO space. Source decrement. 1 = The source address is decremented after each transfer. The B/W bit determines the decrement value by 1 or 2. The address remains constant when both SDEC and SINC bits are set to 1. 0 = Disable the decrement function. Source increment. 1 = The source address is incremented after each transfer. The B/W bit determines the increment value by 1 or 2. The address remains

Bit 14

DDEC

Bit 13

DINC

Bit 12

SM/IO

Bit 11

SDEC

Bit 10

SINC

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CE-188A Datasheet

Data Sheet
constant when both SDEC and SINC bits are set to 1. 0 = Disable the increment function. Bit 9 TC

CE-188A

Terminal Count. 1 = The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0. 0 = The synchronized DMA transfer is not terminated when the DMA transfer count register reaches 0. Unsychronized DMA transfers always terminat when the transfer count reaches 0. Interrupt 1 = DMA unit generates an interrupt request when the transfer count completes. The TC bit must also be set to generate an interrupt. Synchronization Type Syn1 Syn0 --0 0 --0 1 --1 0 --1 1 ---

Bit 8

INT

Bit 7

SYN1-SYN0

Synchronization Type Unsynchronized Source Synchronized Destination Synchronized Reserved

Bit 5

Priority 1 = Selects high priority for this channel when both DMA channels are in transfer at the same time. Timer Enable / Disable Request 1 = Enable the DMA requests for Timer 2. 0 = Disable the DMA requests for Timer 2.

Bit 4

TDRQ

Bit 3 Bit 2 Bit 1

Reserved CHG ST Changed Start Bit. This bit must be set to 1 to modify the ST bit. Start/Stop DMA channel 1 = Start the DMA channel. 0 = Stop the DMA channel. Byte / Word Select 1 = The address is incremented or decremented by 2 after each transfer. 0 = The address is incremented or decremented by 1 after each transfer.

Bit 0

B/W

Page 40 of 61
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CE-188A Datasheet

Data Sheet
DMA Transfer Count Register DMA0 15 TC15 DMA1 15 TC15 Bit 15-0 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3

CE-188A

Address: 0xFFC8 Reset Value: ---2 TC2 1 TC1 0 TC0

Address: 0xFFD8 Reset Value: ---2 TC2 1 TC1 0 TC0

TC15-TC0

DMA Transfer count. The value of this register is decremented by 1 after each transfer.

DMA Destination Address High Register DMA0 15 14 13 12 11 10 9 Reserved DMA1 15 14 13 12 11 10 9 Reserved Bit 15-4 Bit 3 - 0 Reserved DDA19-DDA16 High DMA Destination Address. These bits are driven onto A19-A16 during the write phase of a DMA transfer. 8 7 6 5 4 3 8 7 6 5 4 3 Address: 0xFFC6 Reset Value: ---2 DDA19DDA16 1 0

Address: 0xFFD6 Reset Value: ---2 DDA19DDA16 1 0

DMA Destination Address Low Register DMA0 15 14 13 12 11 10 9 8 DDA15 DDA0 7 6 5 4 3 Address: 0xFFC4 Reset Value: ---2 1 0

DMA1 15 14 13 12 11 10 9 8 DDA15 DDA0 7 6 5 4 3

Address: 0xFFD4 Reset Value: ---2 1 0

Bit 15-0

DDA15DDA0

Low DMA Destination Address. These bits are mapped to A15 - A0 during a DMA transfer. The Value of DDA19-DDA0 will increment or decrement by 2 after each DMA transfer.

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CE-188A Datasheet

Data Sheet

CE-188A

DMA Destination Address High Register DMA0 15 14 13 12 11 10 9 Reserved DMA1 15 14 13 12 11 10 9 Reserved Bit 15 - 4 Bit 3 - 0 Reserved DSA19-DSA16 High DMA source address. These bits are mapped to A19-A16 during a DMA transfer when the source address is in memory or IO space. If the source address is in IO space (64kbytes), these bits must be set to 0000b. 8 7 6 5 4 3 8 7 6 5 4 3 Address: 0xFFC2 Reset Value: ---2 DSA19 DSA16 1 0

Address: 0xFFD2 Reset Value: ---2 1 DSA19 DSA16

Page 42 of 61
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CE-188A Datasheet

Data Sheet
DMA Source Address Space Low DMA0 15 14 13 12 11 10 9 8 DSA15 DSA0 7 6 5 4 3

CE-188A

Address: 0xFFC0 Reset Value: ---2 1 0

DMA1 15 14 13 12 11 10 9 8 DSA15 DSA0 7 6 5 4 3

Address: 0xFFD0 Reset Value: ---2 1 0

Bit 15-0

DDA15DDA0

Low DMA Source Address. These bits are mapped to A15 - A0 during a DMA transfer. The Value of DSA19-DSA0 will increment or decrement by 2 after each DMA transfer.

Page 43 of 61
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CE-188A Datasheet

Data Sheet
Timer Controller

CE-188A

The CE-188A has 3 16-bit programmable timers. Timers 0 and 1 are programmable and connected to external pins (input and output for each timer). These can be used to count or time external events. They may also be used to generate waveforms. Timer 2 is used for real-time coding and time-delay applications. It can also be used as a prescale to timers 0 or 1 or a DMA request source.
Timer 0, Timer 1 Mode / Control Register Timer 0 15 EN Timer 1 15 EN Bit 15 14 ENH 13 INT 12 RIU 11 0 10 0 9 0 8 0 7 0 6 0 5 MC 4 RTG 3 P 14 ENH 13 INT 12 RIU 11 0 10 0 9 0 8 0 7 0 6 0 5 MC 4 RTG 3 P

Address: 0xFF56 Reset Value: 0x0000 2 1 0 EXT ALT CONT

Address: 0xFF5E Reset Value: 0x0000 2 1 0 EXT ALT CONT

EN

Enable Bit 1 = Timer is enabled. 0 = Timer counter is disabled The ENH bit must be set to 1 while writing the EN bit. The ENH and EN bits must be modified at the same time.

Bit 14

INH

Inhibit Bit This bit allows selective writing to the EN bit. The INH bit must be set to 1 during a write to the EN bit. Both must be modified at the same time. This bit is not stored and is always read as 0.

Bit 13

INT

Interrupt Bit 1 = An interrupt request is generated when the count register equals the maximum count. If the timer is configured in dual-max count mode, an interrupt is generated each time the count reaches max count A or max count B. 0 = Timer will not issue an interrupt request. Register In Use Bit 1 = The max count Compare of the Timer is being used. 0 = The max count Compare A register of the Timer is being used.

Bit 12

RIU

Bit 11-6 Bit 5

Reserved MC Maximum Count Bit When the timer reaches its maximum count, the MC bit will be set to 1 by the

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CE-188A Datasheet

Data Sheet
hardware.

CE-188A

In dual maxcount mode, this bit is set each time either Maxcount Compare A or Maxcount Compare B register is reached. This bit is set regardless of the EN bit. Bit 4 RTG Re-triggering bit This bit defines the control function by the input signal of the TMRIN1 pin. When EXT = 1, this bit is ignored 1 = Timer Count Register counts internal events. Rising edge triggered. 0 = Low input holds the Timer Count Register value. High input enables counting. EXT 0 0 1 RTG 0 1 X --------Setting Timer counts internal events if TMRINx pin is high. Timer counts internal events with the count being reset on rising edge of TMRINx pin. TMRINx pin input acts as a clock source and Timerx Count Register increases once for every four external clock cycles.

Bit 3

Prescalar This bit and EXT define the timer clock source. EXT P --- Setting Timer count register increases once for every four internal processor 0 0 --- clocks. Timer count register increases with prescale using timer 0 1 --- 2. 1 X --- TMRIN1 pin acts as an input acts as clock source and the count register increases once four every four external clocks. External Clock Bit 1 = Timer clock source is external. 0 = Timer clock source is internal. Alternate Compare Bit. This bit controls whether the timer runs in single or dual maximum count mode. 1 = Specifies dual maximum count mode. In this mode the timer counts to Maxcount Compare A Then resets the count register to 0. Then the timer counts to Maxcount Compare B, then resets the count register to 0 again and starts over with Maxcount Compare A. 0 = Specify single maximum count mode. In this mode the timer will count to the value contained in Maxcount Compare A and reset to 0. Maxcount Compare B is not used. Continuous Mode Bit 1 = Sets the timer to run continuously. 0 = The timer will halt after counting to the maximum count and the EN bit will be cleared.

Bit 2

EXT

Bit 1

ALT

Bit 0

CONT

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CE-188A Datasheet

Data Sheet
Timer 0, Timer 1 Count Register Timer 0 15 TC15 Timer 1 15 TC15 Bit 15-0 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3

CE-188A

Address: 0xFF50 Reset Value: ---2 TC2 1 TC1 0 TC0

Address: 0xFF58 Reset Value: ---2 TC2 1 TC1 0 TC0

TC15-TC0

Timer Count Value This register contains the current timer count. The count is incremented by one every four internal processor clocks or prescaled by timer 2, or by one every four external clocks from the TMRIN1 signal.

Timer 0 / 1 Max Count Compare A Register Timer 0 15 TC15 Timer 1 15 TC15 Bit 15-0 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3 Address: 0xFF52 Reset Value: ---2 TC2 1 TC1 0 TC0

Address: 0xFF5A Reset Value: ---2 TC2 1 TC1 0 TC0

TC15-TC0

Timer Compare A Value

Timer 0 / 1 Max Count Compare B Register Timer 0 15 TC15 Timer 1 15 TC15 Bit 15-0 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3 Address: 0xFF54 Reset Value: ---2 TC2 1 TC1 0 TC0

Address: 0xFF5C Reset Value: ---2 TC2 1 TC1 0 TC0

TC15-TC0

Timer Compare B Value

Page 46 of 61
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CE-188A Datasheet

Data Sheet
Timer 2 Mode / Control Register

CE-188A
Address: 0xFF66 Reset Value: 0x0000

15 EN

14 ENH

13 INT

12 0

11 0

10 0

9 0

8 0

7 0

6 0

5 MC

4 0

3 0

2 0

1 0

0 CONT

Bit 15

EN

Enable Bit 1 = Enable Timer 2 0 = Timer 2 counter inhibit. The ENH bit must be set to 1 when writing the EN bit and must be done during the same write. Inhibit Bit This bit allows selective update to the EN bit. Interrupt Bit 1 = An interrupt request is generated when the count register equals maximum count. 0 = Timer 2 interrupt disabled.

Bit 14

ENH

Bit 13

INT

Bit 12-6 Bit 5

Reserved MC Maximum Count Bit When the timer reaches it's maximum count, this bit is set to 1 by the hardware. This bit is set regardless of the EN bit state.

Bit 4 - 1 Bit 0

Reserved CONT Continuous mode bit 1 = Timer continues to run after it reaches maximum count. 0 = The EN bit is cleared and the timer is held after each timer count reaches the maximum count.

Timer 2 Count Register 15 TC15 Bit 15-0 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3

Address: 0xFF60 Reset Value: ---2 TC2 1 TC1 0 TC0

TC15-TC0

Timer 2 Count Value This register contains the current count of timer 2. The count is incremented by one every 4 clock cycles.

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CE-188A Datasheet

Data Sheet
Timer 2 Maxcount Compare Register 15 TC15 Bit 15-0 14 TC14 13 TC13 12 TC12 11 TC11 10 TC10 9 TC9 8 TC8 7 TC7 6 TC6 5 TC5 4 TC4 3 TC3

CE-188A
Address: 0xFF62 Reset Value: ---2 TC2 1 TC1 0 TC0

TC15-TC0

Timer Compare A Value

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Data Sheet
Asynchronous Serial Controller

CE-188A

The CE-188A has two independent asynchronous serial channels. They provide full-duplex, bidirectional data transfer using standard communications protocols. Asynchronous port 0 is available. Asynchronous port 1 is RS232 compliant. Asynchronous port 1 is also used by CEImon to download new application firmware and for user debug. These ports support: ? ? ? ? ? ? ? ? ? ? Full-duplex operation 7, 8 or 9 bit data transfers Odd, even or no parity Short or long break characters Parity, Framing and overrun error detection Hardware handshaking (serial 0 only) DMA transfers to and from Interrupt support Independent baud rate generators Double buffered transmit and receive buffers

Flow Control Serial port 0 supports hardware flow control. The flow control signals (RTS0#/RTR0#) are configurable by software to support different protocols. DCE/DTE Protocol The DCE/DTE protocol provides flow control. This protocol provides flow control where one serial port is the receiver and the other a transmitter. In this protocol, the DTE device sends data. When data is available to send the DTE asserts the RTS# signal. The DCE sees this as a request to enable its receiver. The DCE signals the DTE device that its ready to receive data by asserting RTR#. The DTE cannot signal the DCE that it is ready to receive data and the DCE cannot signal that it is ready to send data. To configure for this protocol, ENRX bit should be set and the RTS bit should be cleared. To implement the DTE device the ENRX bit should be cleared and the RTS bit should be set. These bits are located in the AUXCON register. CTS/RTR Protocol This protocol is the most common form of hardware flow control. It provides flow control in both directions. When a port is ready to receive data, the port asserts the RTR# signal. The other port will not send data until its CTS# signal is asserted. To enable this protocol, clear both the ENRX and RTS bits for the serial port. This is the default configuration. Asynchronous Serial Registers Following is a list of registers for both Asynchronous Serial channels. Note that serial channel 1 does not support hardware flow control and is used for RS-232 only.

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Data Sheet
Serial Port Control Register Serial Port 0

CE-188A

Address: 0xFF80 Reset Value: 0x0000 13 12 RISE 11 BRK 10 TB8 9 FC 8 TXIE 7 RXIE 6 TMOD 5 RMOD 4 EVN 3 PE 2 1 MODE 0

15

14 DMA

Serial Port 1

Address: 0xFF10 Reset Value: 0x0000 13 12 RISE 11 BRK 10 TB8 9 FC 8 TXIE 7 RXIE 6 TMOD 5 RMOD 4 EVN 3 PE 2 1 MODE 0

15

14 DMA

Bit 15-13

DMA

DMA Control Field. These bits configure the serial port for use with DMA transfers Bit Bit Bit 15 14 13 Receive Transmit NO 0 0 0 NO DMA DMA 0 0 1 DMA 0 DMA 1 0 1 0 DMA 1 DMA 0 0 1 1 N/A N/A 1 0 0 DMA 0 NO DMA 1 0 1 DMA 1 NO DMA NO 1 1 0 DMA 0 DMA NO 1 1 1 DMA DMA 1

Bit 12

RSIE

Receive status interrupt enable 1 = Enable serial port interrupt enable. Send BREAK 1 = Drive TXD pin low. Long Break = TXD driven low for greater than (2M * 3) bit times. Short Break = TXD driven low for greater than M bit times. *M = start bit + data bits number + parity bit + stop bit

Bit 11

BRK

Bit 10

TB8

Transmit Bit 8 This bit is transmitted as the ninth data bit in modes 2 and 3. This bit is cleared after each transmission. Flow Control Enable 1 = Enable hardware flow control 0 = Disable hardware flow control Transmitter Ready Interrupt Enable When the transmit holding register is empty (THRE in status register), an interrupt occurs. 1 = Enable

Bit 9

FC

Bit 8

TXIE

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Data Sheet
Interrupt 0 = Disable Interrupt Bit 7 RXIE Receive Data Ready Interrupt Enable When the receive buffer is full (RDR in status register), an interrupt occurs. 1 = Enable Interrupt 0 = Disable Interrupt Transmit Mode 1 = Enables the transmit section of the UART 0 = Disables the transmit section of the UART Receive Mode 1 = Enables the receive section of the UART 0 = Disables the receive section of the UART Even Parity This bit is valid only when the PE bit is set. 1 = Even parity checking enforced. 0 = Odd parity checking enforced. Parity Enable 1 = Enable parity checking. 0 = Disable parity checking. Mode of Operation Bit Bit 2 1 0 0 0 1 0 1 1 0

CE-188A

Bit 6

TMOD

Bit 5

RMOD

Bit 4

EVN

Bit 3

PE

Bit 2-0

MOD

Bit 0 1 0 1 0

Mode 1 2 3 4

Data Bits 7 or 8 9 8 or 9 7

Parity 1 or 0 N/A 1 or 0 N/A

Stop Bits 1 1 1 1

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Data Sheet
Serial Port Status Register Serial Port 0 15 14 13 Reserved Serial Port 1 15 14 13 Reserved Bit 15-11 Bit 10 Reserved BRK1 Long Break Detected 1 = Long Break Detected Short Break Detected 1 = Short Break Detected Received Bit 8 This bit should be reset by software. This bit contains the ninth data bit received in modes 2 and 3. Received Data Ready. Read Only. 1 = The received data register contains valid data. This bit can only be reset by reading the Receive Register. Transmit Hold Register Empty. Read only. 1= The transmit register is ready to accept data. This bit is reset by writing data to the transmit register Framing Error Detected 1 = Framing error detected. This bit must be reset by software. Overrun Error Detected 1 = Overrun error detected. This bit must be reset in softare. Parity Error Detected 1 = Parity Error Detected (mode 1 and 3). This bit must be reset in software. Transmitter Empty. Read Only. 1 = Transmit shift register is empty Handshake Signal. Read only. This bit reflects the inverted value of the CTS# pin. 12 11 10 BRK1 9 BRK0 8 RB8 7 RDR 6 THRE 5 FER 4 OER 3 PER 12 11 10 BRK1 9 BRK0 8 RB8 7 RDR 6 THRE 5 FER 4 OER 3 PER

CE-188A

Address: 0xFF82 Reset Value: ---2 TEMT 1 HS0 0 Res

Address: 0xFF12 Reset Value: ---2 1 0 TEMT HS0 Res

Bit 9

BRK0

Bit 8

RB8

Bit 7

RDR

Bit 6

THRE

Bit 5

FER

Bit 4

OER

Bit 3

PER

Bit 2

TEMP

Bit 1

HS0

Bit 0

Reserved

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Data Sheet
Serial Port Transmit Register Serial Port 0 15 14 13 12 11 Reserved Serial Port 1 15 14 13 12 11 Reserved Bit 15-8 Bit 7-0 Reserved TDATA Transmit Data Data written to this register is transmitted out the serial channel. 10 9 8 7 6 5 4 TDATA 3 10 9 8 7 6 5 4 TDATA 3

CE-188A

Address: 0xFF84 Reset Value: ---2 1 0

Address: 0xFF14 Reset Value: ---2 1 0

Serial Port Receive Register Serial Port 0 15 14 13 12 11 Reserved Serial Port 1 15 14 13 12 11 Reserved Bit 15-8 Bit 7-0 Reserved RDATA Received Data The RDR bit should be read as 1 before reading the RDATA register. 10 9 8 7 6 5 4 RDATA 3 10 9 8 7 6 5 4 RDATA 3

Address: 0xFF86 Reset Value: ---2 1 0

Address: 0xFF16 Reset Value: ---2 1 0

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Data Sheet
Serial Port Divisor Register Serial Port 0

CE-188A

Address: 0xFF88 Reset Value: 0x0000 13 12 11 10 9 8 BAUDDIV 7 6 5 4 3 2 1 0

15

14

Serial Port 1

Address: 0xFF18 Reset Value: 0x0000 13 12 11 10 9 8 BAUDDIV Baud Rate Divisor The general formula for the baud rate divisor is: Baud Rate = Processor Clock / (16 * BAUDDIV) 7 6 5 4 3 2 1 0

15

14

Bit 15-0

BAUDDIV

Supported Baud Rates The serial ports can operate at different baud rates. NOTE: If power-save mode is enabled, the baud rate divisor must be reprogrammed to reflect the new processor clock frequency. Also, since power-save is exited automatically when an interrupt is taken, serial port transmit and receive data may be corrupted if the serial port is in use and interrupts are enabled in power-save mode. The formula for determining the baud rate is as follows: BAUDDIV = (Processor Frequency (16 baud rate))

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Data Sheet
Baud Rate 300 600 1050 1200 180 2400 4800 7200 9600 19200 28800 38400 56000 57600 76800 115200 128000 153600 Divisor at Processor Clock Rate 20 MHz 40MHz 4116 8333 2083 4166 1190 2380 1041 2083 694 1388 520 1041 260 520 173 347 130 260 65 130 43 86 33 65 22 45 22 43 16 32 10 22 9 19 5 16

CE-188A

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Data Sheet
Programmable I/O

CE-188A

The CE-188A has 24 available IO pins. Each of these pins may be programmed as an IO signal if the special function of the pin is not needed. Each pin may be programmed as an input or output, with or without pull-up or pull-down resistors. These may also be used as an open-drain output. Below is a list of IO signals and theyre use on the CE-188.
PIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Function TMRIN1 TMROUT1 PCS6#/A2 PCS5#/A1 DT/R DEN# SRDY A17 A18 A19 TMROUT0 TMRIN0 DRQ0/INT5 DRQ1/INT6 MCS0# MCS1# PCS0# PCS1# PCS2#/CTS1#/ENRXQ# PCS3#/RTS1#/RTR1# RTS0#/RTR0# CTS0#/ENRX0# TXD0 RXD0 MCS2# MCS3#/RFSH# UZI# TXD1 RXD1 S6/CLKDIV# INT4 INT2 Reset Status Input with 10K pullup Input with 10K pulldown Input with 10K pullup Input with 10K pullup Normal Operation, Input with 10K pullup Normal Operation, Input with 10K pullup Normal Operation, Input with 10K pulldown Normal Operation, Input with 10K pullup Normal Operation, Input with 10K pullup Normal Operation, Input with 10K pullup Input with 10K pulldown Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pulldown Input with 10K pulldown Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup Input with 10K pullup CE-188A Use A17 A18 A19 CAN / Available TXD RXD Reserved CAN Int/Reserved Reserved

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Data Sheet
PIO Mode Registers

CE-188A

This and the direction register determine whether each pin is a function, or is enabled as an IO signal. Each bit in these registers represent a PIO pin.
PIO 1 Mode Register Address: 0xFF76 Reset Value: 0x0000 12 11 10 9 8 7 6 5 4 3 2 1 0 PMODE (31 - 16) Bits 150

15

14

13

PMODE31-16 PIO Mode Bit The definition of the PIO pins are configured by a combination of PIO Mode and PIO Direction. Each PIO pin is programmed individually Mode Dir Pin Definition 0 0 --Normal Operation 0 1 --PIO Input with Pullup/Pulldown 1 0 --PIO Output 1 1 --PIO Input without Pullup/Pulldown

PIO 0 Mode Register 15 14 13 12 11 10 9 8 7 6 5 4 3

Address: 0xFF70 Reset Value: 0x0000 2 1 0 PMODE (15 - 0)

Bits 150

PMODE 15-0 PIO Mode Bit The definition of the PIO pins are configured by a combination of PIO Mode and PIO Direction. Each PIO pin is programmed individually Mode Dir Pin Definition 0 0 --Normal Operation 0 1 --PIO Input with Pullup/Pulldown 1 0 --PIO Output 1 1 --PIO Input without Pullup/Pulldown

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Data Sheet
PIO Direction Registers

CE-188A

This field determines if the specified IO is an input or output. A 1 defines the specified pin as an input, and a 0 defines the pin as an output.
PIO 1 Direction Register Address: 0xFF78 Reset Value: 0xFFFF 11 10 9 8 7 6 5 4 3 2 1 0 PDIR (31 - 16) Bits 15-0 PDIR31-16 PIO Direction Register 1 = Configure PIO pin as an input. 0 = Configure PIO pin as an output.

15

14

13

12

PIO 0 Direction Register

Address: 0xFF72 Reset Value: 0xFFFF 11 10 9 8 7 6 5 4 3 2 1 0 PDIR (15 - 0)

15

14

13

12

Bits 15-0

PDIR15 - 0 PIO Direction Register 1 = Configure PIO pin as an input. 0 = Configure PIO pin as an output.

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Data Sheet
PIO Data Registers

CE-188A

If a pin is defined as an output, the value of the corresponding bit in the data register is driven on the pin. If the pin is defined as an input, the pin state is reflected in this register.

PIO 1 Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3

Address: 0xFFFA Reset Value: ---2 1 0 PDATA (31 - 16) PDATA3116 PIO Data Bits These bits map to PIO31-PIO16 and indicate the value driven when the PIO pin is programmed as an output or reflects the external level when read.

Bits 15-0

PIO 0 Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3

Address: 0xF74 Reset Value: ---2 1 0 PDATA (15 - 0) PDATA 150 PIO Data Bits These bits map to PIO15-PIO0 and indicate the value driven when the PIO pin is programmed as an output or reflects the external level when read.

Bits 15-0

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Data Sheet
Revision Information
Revision 1.0 ? Initial Release

CE-188A

Warranty
All CEI products are covered against defects in manufacturing for a period of 30 days from date of purchase.

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CE-188A Datasheet

Data Sheet
Contact Information
Copeland Electronics, Inc. 440 Colony Place Gahanna, OH 43230 Tel: (614) 475-1690 Fax: (614) 882-6062 Email: info@copelandelectronics.com Internet: www.copelandelectronics.com

CE-188A

Legal
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Copeland Electronics, Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Copeland Communications products as critical components in life support systems is not authorized. Copeland Electronics, Inc. does not guarantee its products for use for any specific purpose. It is the buyers responsibility to protect life and property against failure. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights Trademarks: Windows is a trademark of Microsoft. All other products or technologies are the trademarks or registered trademarks of their respective holders.

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CE-188A Datasheet