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gttips SemiconductoB

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80C51Family

80G51 familyarchitecture

80C5,IARCHITECTURE MEMORY ORGANIZATION lor prcgram All80c51 devices hav sparals addrcss spacs and loglcalsopafatlon daia memory, ashown inFigulos l snd2.Th or progEm anddata memory allows lhdalalliemory lo bac.6sd
which canbequickly sioedandmanipulaied by by8-biteddrosses, 16-bh canalso an8 bitcPU.Nevrlhlss, daiamemory addr6$as begenehiedthoush the DP'IRgisl6r. (ROM, EPROM) n onlyberead, nolwdtlen to. P@gEm 'ie'nory memoryIn the 80c51, the Therecanbe uplo 64kbytosof program vsrsions, lowesl 4k b!,iesol progEmareon{hip, ln lh ROMIss all prcg@nr ls exlemal. The Ead slrobelor exlemalprogran rnemory sioe enabre). memory is tlreFSEN(prcgram (RAr',4) a separale addrcssspacerDm DataMemory occuples PrcgEn Memoryln lh 80C51 , ihe lowst 128byiesoi data Uplo 64kbytsot oxtmalMl', can be mgmory ae on-chip. Data Memorv sDa@. Inlhe ROMless addre66ed inlhexiernal 128byles areon-chip. ThecPU generales read veBiof,lhelowest dunng exlernal Data andwdte signals, RDandWR,asneeded andsxlomalDalal'rsmorymayb ExlmslProgEmMemory if desied by applying the ROand PSEN signslsto th6 combined inputs of anANDeateandusingthe oulputof lh gal asth read mehory s1rcb6 lo lhe sxlemaiPDgEm/Data

arespaced ar 8-b!,1e intetuals: 0003H The Inb|nipt sNicelocations iorTlmer0,0013H ior Enemal forE{6mal'nterruot 0,0008H Interupi 1,0018H ior]lmer1, etc.lf an interupt ewic routine i5 ihe cas6l. co.aolapplitlons) itcan shodonolqhiasisonen reside enli.elywjhin thal&by4e inleryal. Longer seryie.outi.es to skipoversubsquenlinlrupt n useajumpinslruclion locqlions,lfothor inl6nupls afin us6. Th6lowesl4k btiss ot Progn Memory cnsitherbo in lh on-chip ROM Thisselectior is made bystapping the orin anexiemalRO[l. g (E{omalAccess) pinto eiiher Vcc,orVss.lnihe80C51, !iihe E pin s siEppedio Vcc, thenihe progEmietchesto addrcsses 0000Hlhrough oFFFH arediecied lo theintemalROM. Progmm through FFFFH lo exlernal felchos to addsss 1000H aredirecled ROM. 10 Vss,thenallpbobm ietches are flh6m pinis slrapp6d pads(8031,80C31, diected io exienalROM. TheROMles6 etc,) lo musl have ihispinenemaltslrappd lo Vsslo 6.abl6lh6m x6cut frornexlomalProqrarn liernory. Th6radlrobelo extnal ROtl, PSEN,is usedfiI all extehal prcqram ierches. PSENis noractivared ior intemalprcgram ielches. progEmexe@lion Thehardware connguEiion for external is shown (Pods in Figure 4. Note lhai 16l/Olines 0 and2) arddicBtd b durlng extemal Prcgram Memoryfetches. Port 0 (P0 bustu.ctions lho InFigure 4) serues asa multiplexed addre66/dala bus.11ftits (PCL)as an address, andthen lowbyteof lho PrcgmCountr goesIntoa foai siateawaiting theam'val of lhe codebtle ftomthe [,lemoryDur'nglhe timethai the low byteol lhe Prcgm Program nable) counleris validon Porl 0, lh 6ignal ALE{Add6ssLatch Pon2 (P2in clock8 lhisby4s inloan addss labn.Meanwhile, FiCUre 4)emitsihe highbtle otihePrcgFm Courtff(PCH).Ihen FSENsiobes ihe EPROM andlh6 cod6b!,leis readinlolhe 16biiswide, even ihough Pogm l4emory addresss aralways the aciualamount oi Pmgm l\,4omory usedmaybe less&an 64k irc oflhe 8-bt pons, by[es.Enemalprcgrnoxeculonsacrlflces of addre$ing ihePrcgram Memory P0andP2,lolhetuncton

Program Memoty
Fieue 3 shows a mapol th loworparl of the PbgEm Memory begins execulion fromlocation 0000H.4s After ser,rheCPU intrrupt is assigned a nxed lotionin 3, each shdn in Figure thecPu lojumplo thal ProgEm [4emory Theinlsnupi causes execuiion oi the *ryi@ Eut ne, lo6iion. whrit commences is assigned !o location 0003H, lf Extemal Inlerupl 0,ioretample, rculinemust Intempl0 is golngto be used,its seruice ExGmal is notgoinglo be uBed, its 0003H, It the Interrupi beginal location purpose PogEmMemory location i! available asgeneEl sewice

BlockDiagram Figurel. 80c51

Family 80C51

80C51familyarchitecture

ftlgEmMsmo'y (RBd oirY)

stNcture Momory Figur.2. 80C51

I
)

Figurc3. 80C51Prosramlvl.mory

Figu.e 4. ExcutingItom Exl.rnal ProgEm MEmory widOnebvl 1or2 bvls canbilher Mtroryaddess66 '/o oth$ithoneo' more in conjunclion used adde;es areoften 5 in Flgure pags as shown lhe RAM, linsto Trc-btte addssescnalso be used'in whichcaselhe high addE$ b)'teiEomited al Polt 2. 6 Thet-ory spa i5 if Figur Fapped lrteaa' DalsMemoryis ae gerEtvrlercdtoas wl'rcn inlotie blocks shdn oiviod andSFRspace' Upper128, iheLow$128,tho

theinlenalardextemalDai6 hafoiFiquc 2 sFods Thedoht Flgure 5 shMBa user' 80C51 lo R| availsble Mem; sDacs o'6'lernal upto 2kbvles for.ccsssilg hedw;rconliou6tion Pod0 int6malROM inll'lsc5sisx{'uling'om RAM.TheCPU 3 lln6 ol and RAM, bus lo the addtesvdaia seN6sas a multiplxed ;;n t arbenq ;seo !c passlhe RAlvlThe cPU snratBRD RAMsccssgs Th6r dudng ex[e'nal asneedd anoWRsio.als ExrenalDal6 o'nendOala Memory' cdnbeuoio 64hb!'ies 1995 March

DataMemory

80C51 Family

80C51familvarchitecture

InlemalDalaMemory addssesa.e alwaysonebytewld,which impllqs an addross spac6oi only256 byias,Howvr, ihe addressing mod$ for intemalRAMcanin lacl ac@omodale 384 bti6, using a simpl lrick, Di6claddsses higherthan 7FH accs ondernory Bpae,andindirectaddBeshigherihan 7FH accs a diferenimemory spae. ThusFigure 6 shows th6 Upper 128andSFRspa@ occupyin! ihesame blo6k oi addresses, 80H lhsy are physically throlgh FFH,alihouoh sparalg 6nt;ti63. TheLowe'128 byles of RAI'I arepresert inal.80C5'devi@s as mapped in Figue7.Theldesl32 by,isarcgrouped inlc4 lanks ProgmInsiruollons oi 8 reglsteB. callout th6sefsglslsrsas R0 through R7.Twobiis in ihe PbgramStaiusWord(PSW) slecl whlcheglster bankis in u*. Thisallowsmoreefiiclenlusof cod6 spa@,eince gistr imlructiomar shodsrthar inslruclions that

Ths isxt 16by4s abovelhe rcgisterbanksfom a blockof bilddessable nemorv sDace. Th80C51 inslruclion 6elincludes a wideseleclio.of slnOl-bh inslructons, andth 128bilsin thls aa canbs dicly addrssd by ih$e imtruclionsThebii addr6ss6s Inlhisara a 00Hlhrcugh 7FH. All oi lhs b'ts i. lh Lowr128@n be accessed by eilherdiecl or indiectaddressing. TheUppe.l28(Flguls 8) canonlyb6accesd Flgure 9 glvesa bdtlookat lh6 Special Funclion Resistq(SFR) pedpheral spac, SFR6 include lhePortlatches, timeB, conibls, etc.TheseregisieBen only be accessed by dlEct addresslng. Sixtn addresses in SFRspaceare boihbyte-andbiladdressabl. Thebi-addlBable SFRS ae trlGe who* address ondsin 0Hor 8H,

Rl"
"{
Fisure 5. Acc3ing Extemal Datsllemory rthePrcgm Memory k Intemal, ih Oth.r Blts of P2Ars Avall.ble as UO Flgur, Intemal DataMemory

By'* of Intemal RAtl Fisurc 7. Lower'128

128Bytes of IniemalRAM Figure 8. Uppr

March1995

80C51 Family

80C51 family architecture

Flsurc 10. PSW(ProgEm StatusWord)Reslsterin 80Csl Dvlcs

SET INSTRUCTION 80C51FAMILY ft'r &bit@nlrol appllcadons setis oplimlzd inslructlon ths 80c51
for a@slifg th a vadoty of iasi addssingmodes It provldes on smalldatasLuclur63 i.t6mal RAM!o ladlitatb),teoperalions ior onebii vadablos sei providss onensivesupport Theinstruciion in @ntrol diect bit manlpuialion datatype,allowlng as a separaia ihai quirs Boolean andlogicsystems Plocessing. sevel shtus bils lhal Status word (Psw) @ntains The Prcgmm rofleciihe currenlstaieof lhe cPu. The Psw shownin Figu 10, in the sFR space.lt conlahsthe catry bil, lhs Auxiliary Gids ihe two rglslerbankl6lcl blts,the Cary (i BCDoperalions), status ndgs 169. aPaiiybil a1dlwouser{Fnable Overflow Ths Canybii, othrlhan seNingth tunciionoI a Cafrybil in as lhs "Accur.ulaioflor s abo srues operaiions, adthmetic opsralions. numbgr oJB@lean to 6lscl oneolthiourrister andRS1 areused fte bitsRSO rererlo the6 7. A numbetol inslruclions in Figurc banks shown 1995 March

of whlchof thefour as R0throughR7.Theselection RAMlocations is bingreiercd to is madoon the basisof th RSoandRSI ai P = 1 li ol 1sin rheAccumulalor; The Padtybit llcls the number ls, andP = 0 ii lh anoddnumberol conlains thoAccumulalor thenumber of 1s of 1s.Thus contains anevennumber Accumulalor plusP isalways aro even, Twobitsinlhe PSW inlhAccumulalor purpose slatus flag5. asgeneral andmaybs used uncommlited Addresalng Modes sst re asfollows: mod6 in lh 80C51inslruclion Theaddrosshg by an 8-bitaddss the opeEndis spcffied In dkecladdrssing only inlena' DataFAMandsFRscnbe fieldin rho'nstruclion.

statusWord Program

80C51 Family

80C51 family architecture

In indirect 6ddrs6ingthe insLuclion specifies a .egister which @nlains lhe address of the opeland. 8o1i inlemalandextemal M[4 canbirdicilv addrssd. Theaddrs register lor 8-biladd!6er caf be R0o. R1 of the or lhe StackPoinlerTheaddress reqister solocled bank, ior l Fbli ldata poiniel regisier, addresse canonlybeihe 16-bit DPTR. Thereqisierbanks, @niaining reqisters R0ihoughR7,en !e a@ssed byedain inslrucliom whicherry a 'bit gisier soecifiion wilhinlhe oo@deol the in6lruclion. lnslruclions that ihis wayare codeeffclent,slncoihls node accss lhe rcglsrers lininalsssn addrss b!,ie.Whnlho instuclionis execulsd, onof lhe eightreglsGFin the selecled bankis ac@ssed. Oneofiour banks :s selecld at xcutontimby lhs alvo banks6l6clbils in the Reglslorpecatic Instructions Some lnstructons arespeoinc b a @.taingister Forexample, someinsLuclions alwayG opBt6on lh Acclrnulator. or Dala byteis needed ropoint io ir-Theopcodo Poinlgt tc., so noaddEss itselldo6 hai lnslruclion! lhat tr lo thAccumulalor a6A assemble asa@umulatorsogcifi coocodss. ths opcodo Th6valuof a consianl caniouow ln Progmlvemory M O VA . # 1 0 0 100. loads theAccumulalor wlihl'rddmalnumbs Thesam6 number 6dd bespecilied inhexdigits as 64H. pbgEmMemorynbeaccg$ed wilhindexed add|sing, Only andil canonJy be read.Thisaddlessing modis iitendodfor rcadins l@k-up iabls i. Prcgram MemoryA lGbil bas registor polnls10the baseor th (einer DPTR or L'r6Plogm CounleD is sei upwiih lhe lableenirynumber lable,andli Ac.umuJator is iomed by Ths address of thetableeniryin ProgmMemory theAccumulaior dala!o lhe basepo'nter addinq addrcsslng is used ln ihe'sejump' Anolhert}? ol Indexod on.Inlhlscase ihedeslination addEs ota iumD instruclion inslruc ls comDuled as lhe sumol lhs bassoolntrandlh Accurnulalof

Adthme{ic lnstructions
Themenuof arilhmeric instructions is lisrod in Tabl1, Th6table lndlcates lheaddressi.g modos !161can b6us6d wilhach <bls> opnd, roaccgsslhs lnsr,.ucrlon For/mple,lh Aoo insttuclion A,<byl6> canbs wnflonasl ADD a,7FH(direcl addre$ing) (indiEct ADD A, @R0 addssins) ADD a, R7{gistd addssing) ADD A. *127limmediaie constanil in Tabl6 Th6sxgcurlon tmslistod 1 asum a 121',,lHz clock lrequency. Allollhearilhmetic insirucljons execute in 1psexepi theINCDPTR instruclion, which lakes 2Us, andtheMulliply and Divide inslruclions, whichtake4Us. Indro Intemal Datal,lgmoryspacscanb Notrharany by,ls going incmontd wilhout thrcush lhAccumuraloi Onoi lhINCin6lrucliors opral66 onlhe 16-bil DalaPoinler The DataPoi'nrisus6d1ogenle 1Fbil add66s tor exlemal memory,60 being able lo increment ii inone16-biioperation isa TheMULAB instruction multiolies iheAc@mulaior bvthedata in producl iheB egisier andpuisihe 16-bil inioihemnienated B andAccumulator regisie.s. ThsDIV ABinslruclion divldssthsAccumulalorbvth datainlhB quolient .egisier andleaves lhe8"b't in iheAccumulalor, andlhe remaindr intheB reglstr 8-blt 'divide" Oddlyenough, DIV ABfinds lessusein adhmetic outnes thanin dix @nveBions andprog6Bmableshiftopetions.An example ol iheuseo'DIV ABin a 6d @nve'6ior willbegiven lalei ln 6hifloperations, dividi.g a numbr by 2n shift5its n bilsto thdghi. Uing DIV ABto pfom lhodivision complts lheshinii lheB iegislerholding thebilslhatweeshifred out. 4Lsandleaves The DAA insiruclion is for BCDadthmetic operatons. In BCD aitrmetlc, ADOandADDC inslruclions should always beiollowd thai the resuliis alsoin BCD.Note by a DAA opetion,to ensure thatDAA willnot6nven a binary number [o BCD. TheDAA producs opelion a .ranhgtul rsult onlyas lhosecond sl6ph lh addilion of two BCDbyles,

Table1.

80C51 ArithmeiicInstruction3
MNEMONIC

OPERATION
DIR

ADDRES6ING MODES IND REG IMM

EXECUTION tlME{ps)

X
SUBBA,<byl>

x
x
2

INCA
INC DPTR

DECA

x
MULAB DIVAB

March1995

Family 80C51

architecture family 80C51

Tabi 2 shM lhs ltslol 80C51losi@linslruclionsThelrstruclrons OR NOT)on (AND,OR, Exclusive oplalions thal oorfom Boolean Thatis if th ba6is. on a bil_by-bii bvds oedom the operalion 010100118, contains andbt4e oo110101B A;cud;la[or @ntains ANL A,<byls>

LodicalInstructions

rvlovE B,#10 DIV AB ADD A,B ol the tensdigitInthe lowntbble th nl]mberby 10 leaves Divldlng thAdmulalor, andlh onesdigit in lhe B registerTh6swAP and ot th moveihe lsns digiito li highnibbio ADDinsiructions digit io thelownibbls. andtheonos Accumulator,

000100018 holdlng theAccumulato. wlllleav lhat canbe usd!o accesslhe <bvl> modes Theeddressing 2 lnTabl6 ae lisid opend <byt6> mavtakeanvoI lhs iorms: instruction A, TheANL (dic1 addtossing) ANL A,7FH (lnd!cl addsring) ANL A,@R1 (glsler addrcssins) ANL A,R6 (irimedialsconstanl) ANL A,#53H execule areAccumulator-specilic All of lhe logil instuciion! thst 'rhe olhelstake q$ clock). a 121\,lHz in 1us(using opetionsn bEporiom6don nvbytein the Notelhat Boolean spa wilholt golngthrcughlhe Accumulalor Memory Dala intemal for exanple,offersa quick6nd Th6XRL<btt>,#da!ainstruclion, ponbits, a6inxRL Pl' #oFFH. wayto inved easy nol usingthe is InEsponseto an interrupt, li theoDeEi'on thetimandeflbdio pushil onioths siackin lhe savos Accumulator TheRotaieinstuciions(RL,A, RLc A elc ) shifl theAc'umubtor I irLo ll'e LSB o tro thleitor dgll Forbn o|,[on fie MSBrolls theLSB'olsirlo lheMSBpos'for' position. Fo'a dghrrotation, lh highandlow nibblos interchnges A Inslruclion Th SWAP thoAdlmulator This is a usotulopiion in BCD whhin a brnary cortairs itlheAccumLlator Fo_xarple manjoulauons. ll'ar 100 itn beouic[v num;6.whicn ls nown lo b l6ss code: to BCDby drcfollowing convedad

DataTransfers
for moving thal aB available the menuof Instruclions Tabl6 3 shows andtheaddresslng memory spaces, tneintemal wilhln data around alloi clock' on.wiih a 12MHz wilheach sodslhaten beused in either1 or 46 oxecute iheseinsiruotions all@s dataio betransiersd The [4OV<desF,<src>insLuclion goilg will'out orSFRlocallons aryhro rtemarRAM be&eeF ofdata 128bvl6s theUppsr Romembr, theAccumulator ihrouoh andsFRspa@ addfesing' onlvbvlndiEci RAM-can beaccessod addr6slng. onlybydirci RAM rsidss Inon-chip ' and the6tack devics, lhatin 80C51 Not lheSlack nd incemenis instruclion ThePUSH ows urwards, Fo'nt$ isP), lhsn @piesthe bvtinlo lhe slack PuSHend PoP or being6aved to ideilt the bv16 useonv dnectaddressing irdke.i add6s'ing bv t" it"et' Uut tt"" sr""t ,"rto,ed, "ccessed ca4go:.to lie upper means lhstack usirorhsPregisterTFis bLtrol .tosFRspace moleme.lgd RAM i',lheyare 128byresof in lhe80c51ror 128b'4es of RAv a 1orimplrenled Th6Uooer ilrhg cou.teTensWrn heseoevi@s 'i ir6ioMles6orEPROV a losl andPoPed bvles PUSHd rolhe upper128, sP points bytesarIndeleminale MoV lhat canba a 16_blt TheOataTansiar Inslrucibnsinclude lablesin lor look-up lhe oata Pointd (DPTR) used!o inltlali@ or ior 16-bilxlornalDalaMenoryaccases PogramlMmory

Table2

80C5'l Logical lns:ructlons

IVNEMONIC
OPEIIAT]ON

MODES ADDRESSING DIR

IND REG IMM

EXECUTION TIME(rs)

x
<byt> = <byie> ,AND.A .byt> = <byt>.ANDirdala

x x x
x

2 1
1

<byle> = <byt> .oR.l4ata

- <byie> xo!1 <by4e>

<hue> = <b!te> .XOR.#data

RIC A

Lefr1 bit RoiateACC Carry Lefl lhrough Rolate RoiateACCRisht1 bit RotatRightlhrugh Carry

2 1 1 2 1 1 1 1 1 1 1

MaEh 1995

80C51Family

80C51familyarchitecture

Table 3.

DataTransfer hstructionsthat AccesslnternalDaiaMemory Space

MNEMONIC

OPERATION
DIR

ADDRESSING MODES IND REG IMIM

EXECUTION TIME{!s)

x
X = l Gbitlmmgdlat DPTR cofstani INC SP:MO\r@SP',<s.c> MOV <d6st>.'@SP':OEC SP
ACC nd <by1> 6rch6nsedaia XCHD A.@Ri ACC and @Rixchanoe low ribbls leavesihe lasi byte,lotion 2EH,holdirgthe lastt/o diqilsoi lho shiitednumberThe poinieEare decremenled, and the loopis repealei ior locallon 2DH. Tho CJNE inslruction (Compare and Jump if Not Equal) is a loop contlol thal wlll be described laier The loopx6cut6d lom LOOPio CJNEfor Rl= 2EH,2DH,2CH,and 2BH.Ai lhal poinilhe digillhat was originally shiitedoul on ihe nghi has pDpagated to lotlon 2AH.Sln@that lotlon shouldbo lt wllh 0s, the lost dlgit ls moved to th Accumulator. Table4 shows a lisr of th Data Tmnsfff lnstructons that accss n6malDala Memory. Only indici addsEing . be used.The choic8 is wheiher io use a one-byte addess, @Ri, where Ri can be eiihe. R0 or R1 of the seleoted register bank, or a twobyle addes, Th disadvantag to u6ing16-biladdssesifonly a lew k @DPTR. by,leB of nenal RAM a involved is ihat 16-bil addssE use all 8 biisol Pod 2 as addressbus-On lne otherhand,8-biladdsses allow one to address a Gw bytes oi RAM, as shown in Figlre 5, wilhod naving to sacnfie all oi Port 2. All of ihese insiruclions execulo In 2 ps, w'th a 12[,lHz clock. Noteihalin allenemalDaia RAIM aesses, ihe A@umulaioris always eber lhe deslination or solrce of ihe &la. Th rad and wdto slrobs to xlgrnalRAM ar aclivatd only duringth xarlionof a MOVXi.st,uclion.Nomally thsosignals afe inacttus,nd In fact ll they re nor golng to be used ar all, rhek Dinsa .vailablas 6nfa tOlins.

X X

2 2 2 2

TheXCH A, <byle>insLuclion causs5 th Accumulalor and addBed btie to exchange dala, The XCHD A, @Ri instruclion is bui onlylhe low nibbles a involved in lhe exchange. similar, To see how XCH and XCHD cn b ud io facilital data manipulalions, @nsider lirstthe problm olEhilting an 8{igit BCD numberhrodigils[oihenghl Figue 1l shom howthis can be done us'ng dieci MOVS,and for @npad$n how il 6n be done To ald 'n undeFlanding howihe code lslng XCH Instruciions. wort, th @nlnls ol urs rgislIs thal ars holdirg ih BCD numbersnd lh conint of lh6 Accumulalor aro shownalongsid ea6h inslruciion lo indica[e lheir stalug aier the instuclion has been Alier ihe butine has been executed, the Acdmulaior contalns the two digiisthatweE shiiledoul on ihe dghl.Doingtherculinewilh dircl MOVSuss 14 code bytes and 9l1sof exe@tlon ii6e (assuninga 121',lHz wilh XCHSlss clock). The sameoperatlon only I bytes and execuls almost lwi@ as tast. To ishl-shinby sn oddnurnbroidlglls, a on-dlgltshitnust b6 Fioure12 showsa sampleol codethatwill dghl-shift a BCD number Again,the @ntenlsol ihe onedlgii,usin! ihe XCHDinsiruction. Eglslersholding lhe numberandol the Accumllatorae shown alo.gsido eachInsttucllon. Firsl, pointrs R1 and R0 ae sel up io poini io lhe two bttes -rh6. @nlaining lh lsst tour BCD digns. a loop ls execolod wblch

AU.|i!diEd[ov,|i.byb!'9F

Digits toth Right Figure l'1. shinlnsa acD Numbe.Two

March1995

Flglr.12.

Shlftlng a BCO Number One Digitlo the Right

Family 80C51

familyarchitecture 80C51

Table 4,

Space DataMemory that AccessExlernal Instructions 80c51DataTransfer

]IINEMONIC

ADDRESS WIDTH 8 bits 16biis 16blts

OP!RATION Ml'/ @Rl Read rlmar RAlt @ Rl Wdtextrnal FiAM Readexremal @ OPTR wnte extemalRAM @ DPTR

A,@Ri t\4ovx
MOVX @Ri,A MOVXA,@DPTR MO\,,(@DPTR,A

EXECUTION T|MEfus) 2 2 2 2

Tablo

LookupTableReadInstructlons 80C51
MNEMONIC OPERATION al (A + DPTR) Readplogm memory
Read DbqEft mmorv at (A + PC)

(lll) TIME EXECUTION

MOVCA,@A+DPTR MOVC A,@A+PC

2
2

fo'radlng onsthala svail.ble Tao . 5 shows fi nto irst ucac.ess the6 Instuctions Memory' Sin@ in Prcgm lookuptables lablsscanonlvb rsad,nol h lookup onlyPEgramMemory, lhonthe read is io exlsrnalPrcgrsmMemorv, lf lhs tableaccss sfobe ls PSEN. rBt MOVC io!'mov6constant'The is MOVC Themremonlc a tableof upto 256enlds 5 en accommodats in Table inslruclion of ths desied enlryis loaded 255.Thnumber o through numbred B sl up to poinlio |ne andihe DalaPointer lntoihe Accumulaioi Then: oflh6labie. beginnl.g MOVC A,@A+DPTR lableenlryintothe Accunulator lhe de5ird oopis hE instaclionwork th sameway,oxcepr ThotherMOVC as ihlablebaseandthelablais couiisr (Pc)is usd P@gm ollh desired though a subbuiino FiBt lhe number accessd i' lted: andlh subroutine intoth Accumulator, is loadod enl,ay MOV A,ENTRYNUMBER CALL TABLE looklikslhis: SABLEwould Thesubrouline TABLE| MOVC A,@-A+PC RET in iollowsthe RET(Eium) Instrudion Theiablltseffimmediately Tl'is lype ol lab e n haveup lo 255entds PrcaratrMetrory. be usedbeuseat lho 255. NJrbero cnnol nutrbecd1 lhrouq1 lhe addross is exclted,ths PC contains inslructlon timthe MOVC An entrynlmbered0 wouldbeth RET ol nr RETinstruclion Boolean Instructlong prccssor (single'bit) Boolean a comPlete caniain 80C51 devices bits andiheSFR 128addressable contains RAM Theintemal Allol thepon bilsaswell. upto 128addssable spac6 caf suppon 5s a @n bs lreated each one and llnesare bit-addrssable, porl Theinstructlons lhat accessthosebiis aro sepaiesingl-bil bEnch6s,buta complelsmenuol move set ni iustconditional kinds orbit These oR, andANDinstruclions de;r.complemm, silh ahy 'rthnedurs othor i/l obla)ntd opfttrons a@noteady $ltware of btte onenid amount 6 All proes6or is shownin Tablo setlor the Boolean Theinsiruction aroby dict addrsssing bil accsses 128'andbil 7FHa ln theLower lhrough BitaddBssOoH space a in SFR FFH thrclgh 808 address* 1995 lvlarch

to a portpin' n bemoved an intemalllag h@ oasily Note MOV C,FLAG MOV P1.0,C bitinthe of anvaddrssable lsthenarn FLAG Inthis6xample, An l/Olins(theLsBol Port1, inlhis Lower 128or sFR6pac. lho flagbit i5 1 or 0 onwhether es) is set or clarcddePending aslhsingle_biiAccumul.loror TheCarry bhInthePSWls used pro@ssoiBit hsirucliorc that referio th6 Carrybit as ihe Booloan Instuc{on(CLRC etc ) TheCarv as Carry'specific C assemble in lhe PSWrgisier' .inc lt resides bit alsohasa directaddress, whichis bit-addrossable. ANLandORL Insiruciion set includes Noi6lhat ihe Boolan oR) oplionAnxRL butiot rhexRL (Excllslve opeljons, in softwareSupposeior xample, opeEiionis slmpleto implement ORof two bils: It is Bquirodio lom tho Exclusive bit2 C - bltl .XRL, to dolhat @uldbe as bllowsl Th6sofrwar MOV C,bltl b|I2,OVER JNB C CPL Fi6! b[1 is rovsd lo the Carry'lf bll2 = 0 thenc nowcdniaintth Thal ls, bitl .XRl bii2 = bill li bii2 = 0 Onlhe olhsr corct result. of lhecorcl lhecomplemenl hand, il blt2= 1, C nowcontains (CPLC) io complete ih6 opeEtion. rsuii.lt nsedonlybo Invened oneof a 66ios of bil-t6sr Thiscodeuseslhe JNBinslruction, bilis 66t(JC JB a jumpiflhe addrsssed execulg inslruotionswhlch JBC) orlt theaddrs*dbills notsei(JNc,JNB) lnlheabov ]s tested, and!i bit2= o thecPL c Instruciion 6s;, b[2 is beinq bltissel'ndalsocloars ifthaddssd lh6lump JBCxecutes -lhus f,a! en betesledandclearod ln oneopraiionAll a th iit. bil orthe add.sabl, solhePadty bitsarsdireclly ihPSW io lhabirtesl arsalsoavailable puDoss tu xample, geieral nags,

lo the is specifd addrsssiorthesejumps Thdslination mnorv' in PbsEm lddss ah 6ctu.l labal ot bv a a$wbJet W addss assenblesio a lalive ofisei H.w6v6rlh; dstlnation whicl s added by1 otsse! s complmenr, ls a sig.ed(two TFi6 by1e. :' thsjumpis 6xecJted srilhmslic 6 h Pc in Moa complemnl -128 to +127ProsEmr"4emorv Themngeof thejwp is the.iore lhe inslruclion bvt iollowing to lh6 filsi blt6s relauvg

80C5'1 Family

80C51 family architecture

t a D t eo .
ANL

80C5'lBooleanlnstructlons
MNEMONIC C,bii

OPERANON C=C.AND.bit C = C.AND..NOT.bil c:c.OR..NOlbll blt=C

EXECUTION TlilE (ps)

2

oRL
oRL MOV

C,bti
C,/bil C,bit

l',lOV
CLR

blr,c

2 2 2 1 2
'I 'I

c
SETB SETB CPL
JC

C b|t

bit-1 C= -NOT.C blt=.NOT.bll

1 1 1
'I

JB JNB
JBC

2 2 2 bit,rl
2

Table 7.

Unconditional JumDsin 80C5'lDevlces

MiIEMONIC OPERATION

(ps) EXECUTION TIME

2
JMP @A+DPTR

RET
REfI

NOP

JumDInstructions
Tabl 7 shows ihelislofuncondiilonaljuhpswith exetutlon tlme icr Thei.bl lislsa singl"JtlP add/ Insruc on,bul Iniacl lhrsar whlch dlffer Intheiornatof ths lhEeSJMP, LJMandAJMP, JIMP is a geredc mnemonicwhlch n be used dstinarlon address. tfthepEgfammerdo$ nolere which waylh6jump is encoded. TheSJMP instruclion en@des lhe dEstinalion addrs5 aBd reralive above. TheJnstao onis 2 bt14long, ofsel,asdescdbed Tf6jurp @dsrirg o'll.opcode dndh cla'ivo"slbla, 10 rangsof-128 1o+127b}ls elalive to lhe dislanc ls limltd following ihe SJMP lnslruction Inslruc{on enodesthedesiinalion addes asa 16'bit TheLJMP Thelnstruction is 3 byteslong,consisling of the opcode consiant. byt$. Thedeslinalion add6scanbe anywhein andflvoaddress space. lh 64k PbgramMemory The,IJMP insltuclion en@des thede6tination addr$aBan 11-bil is 2 by[eslon!, consisting of ihe opcode, @nstant, Th6lnslruclion biis, iollowed bvanother which il3elf conleins 3 0i rho11address $e l@ 8 bils of th dsunafon add38.Whsnlh by.re conlainins ihe* 11bils aresimplysubslituied for lhe inslrucionls oxocuted, th ow11biisinihePC.Thehigh5 bitsslaylhs sfi6.Hsnco hasto bewithinlhe same2k blocks the instruction dgslination

In all cases ihe p.ogEmmer specines ihe deslinaiion addres to lho assembler inthesame way:as a label or asa ! 6-biiconsianl. The a6.mblr willpulthdeslinalion add6s intolhecorect fonnal lor lhegiven inslruction. lf ihefomatrequicd bytheinstruciion willnoi lo lhspcifigd suppod lhs dislance dslnaion addss, a 'Doslnalionout oi rang6'mossago is witten Intoths Listtlo. Insttuctlon Th6 Th6Jl',lP suppods casejumps. @A+DPTR destnation addrs is compuied atex,.cution timeasihesumoi ihe DPTR is selup 16-bit DPTR rogislr andthA@umulalo. Typically, wiihtneaddss ofajumptable. Ina s-way branch, ior eEmple, an 'lhs inleger0 though 4 i5 loaddintoth Accumulator codlo be executed mightbe as iollows: MOV DPTR,#JUMPTABLE MOV A,INDEX-NUMBER @A+OPTR (0 thlough4) to an The RLA instrucuon coivsris th ind6xnumb. numberon iherange 0lhrough 8, because each enlry inthe evon is2 bles lonoi lumplable JUMPTABLE: riJMP CASE O r'iJMP CASE1 PiJMP CASE2 AJ]VP CASE 3 AJ]\,IP CASE4 JMP

1995 March

-:l

Family 80C51

familyarchitecture 80C51

builhe artwoof addl inslrucllon, 7 shows a single'oALL Table whichdifierin th iormath whichh5 thm,LCAILandACALL, is a gonsric io iheCPU CALL addss i5given subouline notoae en blsed ifthpogEmmerdoos mnemonlcwhich is en@ded, whichwaythe address addre$ iomat, and$e instruclion ussthe 16_bit The LCALL spacs. Momory n boanylvheinthe 4k Program subrouiine fomal,andthesubroutin uss th 11-bh i.slrucllon TheACALL lhe lollowing asih insiruclion musl beinihesne 2k block ACALLihe subouljnoaddEssto th6 spscifies n anycase,ih programmer Th constani way: as a labsl or as a 16_bn inthesamo assenblsr inlolh corfsctiomat for ho glven wlll putthe addrss assemblr whichrelums endwith a RETinslruclion, Suboltin! should g th CALL tollowin eieollion to th nslruction routineThonly Bervic RFII ls used!o rotumf.oman Interrupt betveenRETandRETIls ihat RETItslls lhe intenpl difference proqe*isdor ltLhere isro liat iheinltuptin 61110' sysln oxecuted lnnlie RET|is RET|ls rleruplin prcgssallh6tme lo REL idntjcal tunclionally ihe lisl oi onditionallumpsava 6bl6lo the 80c51 Table 8 shows addr$sbvlhe ihedesljnatlon speclry userAlloflhsejumps !o a j!6p dislancsoi -128 andso are limitd oibsl melhod, rlarive jump tollMinstheconditonal trcn lhs insiruction io +127 b!4es io the 6peciis hNevr, the user lo nol, lmpodant Instruclion, addr*3 lh samewav as lhe other thectualdesunalion assembler ju.iips: or a 16-bil constani asa label TheJZ andJNZinst uclio.s test blt in ths PSW. Thereis no2611' daiafotthatcondilion theAc.umulalor (Dcremeni andJlmP il NotZero)is lor loop Insiruclion The DJNZ a loopN limes,loada counierbvtswfthN and Toexecute conlrol. of lh6 looP,as to lhs boginnins lh loopwilh a DJNZ trminate forN = 10. shdn below MOV COUNTER,#1o

(conpa andJump canalso be lI NotEqual) insttuctlon ThoCJNE in lne usedfor loop@ntol ss in FiguE 12 Twobles arespeciiied Thejumpi6rcclted onlvif ths i{o opeEndild of ihe inslruclion. bttes dronotqual.In lhs r6ple of Fjgure12,lhe nvobyteswe in Rl was2EH. ThiniUaldaia daiai. R1andihecon6lsnl2AH. andihe R1wasdcremenlBd, Every lims ihe loopwa! xcuGd, 2AH unil the R1datareached wasto continue looping ihan" is in'greaierihan,less ofthisInstrucijon Anolher spplicaiion neldae taknas Thetwo bytsin the operand comparisons, ihenlhoCarry thanlhesecond, It thefirstis lss integrs. lnsigned io tho se@ndihen bit is sei (1). ll ths fiIst ls lGaier thanor equal CPU Tlmlng er be have af on{hlposcillalorwhich microconLollors All8OC51 usedil dsled 6 ii clocksourcfor the cPU Touslhe on chip bel'tenthe conreota crvstalor ceErnicrsonalor oscillator. io pinsoi lhe micocontoller,andcapacitoB xrALl andXTAL2 13. in Fig'rrc soundas shown oscillalor ate ol howto ddveihe clockwlih an extrnal Examples (8051elc)th ihatinlh NMosdevics Note shown h Fisure14. qeneratoi divestheinienalclock XIAL2pinactLrally signalalthe (80C51. e[c.),ihe signalat lhe XTALIpin devi@s In ihe CMOS The intemalclockgenerator ddvesthe intemalclockgeneraior' of slateslhat makeup lhs 80c51machino lhe squsnce definos

DJNZ

COUNTER,LOOP

osclllator Figur.l3, Usingtho on-Chip

Table8.

Devlces Jumpsin 80C51 Condltional

i,INEMONIC OPETIATION
DIR

IVODES AOORESSING tMtllt tNo

EXECUTION (Fs) TIME 2

JZ PI JNZ el andjufiP lf notarc Decremsnl

2
2

1995 l4arch

10

.Fhil'p! Semi@nduciors

80C51Family

80C51familyarchitecture

a. NMOS or GMOS

b.N OSOnly
Figuc14. Uslng d E.b.mal Clock

c. CII|OS Only

Machlne Cycles
A machi.e cycl @nsists oi a sequene of 6 stal6, nunbercd Sl lhrough S6. Esdr sial6 tng l*15 lor lwo cdllaror oriod& Thus a machins cycl ldk6 12 Gcillaior pedo& o. 1ps it th6 @ittator Each siale is divided inlo a Phas6 t haf and 6 Pba* 2 han F gure 15 shors that ftch/sxdne sequenB in sraias .nd phas for vanous klnds of inslrudjons. Nofinally two progEm blchs ard generaled dudng 6ach nachine clcle, eEn if ihe instruction bing xculsd doosn l qui il. f ihe inslruclion bing oxedied do6n t ned mor6 code btls, :he cPU simply lgnors ihe qt-a let h, and lh Prog6m C-unteris nol in@me.ted. Exe@tion ofa one{ycle 'nstruclion (Flgus 15a and l5b) begins dunng State 1 ol lhe machine cycle, whn ths opcode is tatded into the Inslruciion Rgisier,A scond fetc*' o@uB dunng 54 of ths sans machins cycl6. Erecu$on is @mDlele at ihe ed of Sial6 6 of Th6 MO\X inslruclions lake lwo machine ctcles io eiolba. No prcgEm letch is geneEted dudng ihe scond ctd6 of a MOVX insiruclion. This is tho only lims prcgfi tlchs ae sklpped. Ihs ietch/oxeculs $qu6nl6 ior MOVX inlruclioN is shM in Flgur

Tt' fatch/exe@te sequme ar th sane whether the PbgEm Momry b intehal or extemal 10ths chip.Executrion iimesdo nol dpnd onwfietherlhe PrcgEmMnoryis intemal or extemal. Figue 16shtr lhe slgnals andliminginvoted in progamftches whd ihe PogramMmory is extemal. lf Program Mnoryis e{emal, thnlhe P.ogEmMemory rcadsbobFSENis nomatty qcle, s shoM in Figure16a.tf an aclivatd lui@ permacbine aclE$to exlemalDala grnoryo@uB, as shownin Flgur16b, leioEE_FSareskipped, b@us the address anddalabusare blngusd60r the DalaMemory accss. Notethata DalaMemry bus cydelaks twie as muchtimeas a PogEn Memory buscryde. Flgurc166hows tne relaiiveiimingof rhaddrss beingemitiedat Ports0 and2, a.d of ALEand PSEtr AIE is usdio latchthe lowaddss bytliom Pointolhe Whentr'e CPUis sxeculi.gfromintenal Pbg,am l\4mory, PSENis notachied, and pmgram addrsss a nol emitled. Howeve., ALE6r inuesio b activald lyice per machine cycleandso it is availablo 63 a d@t oulputsiqnal.Nols,how6vr, thatoneALEis jnsLuclion. sldppd dud.s the ddlion orihe MOVX

1&.

1995 March

80C51 Family

80C51familvarchitecture

*-_t___
a. l.byte, l.yclo l.struclion, e,9., INC A

b. 2-byt,1+ycle Inslructlon,..9., aDD a,#data

I I I

@de

{dbrd)

e.9.,INCDPTR c. l.byte,2-cycl In.lructlon,

tbb | opoe (dserd)

I l.--,-

(1-b'te, 2.cycle) d. MOVX In 80C51 FamilyD.vlces Sequnce FiguB15. State 12

'

-Phil,psScmlconductoB

80C51 Family

80C51 familyarchitecture

I" |;] J ":i":"i":' [" p"i'""ii. " F" l

PcL dr

FI "+,rT"r'-F

Flgure16, BuCycleE in 80G51 Famlly Dovlcs Executing fromExtemal Program Mmory

80C51Family

80C51 familyarchitecture

(MSB) X ES ET1 EXI

(LSB) EXO

(MSB)

(LSB)

Olsabls allintrupts. llFA= o, io inrenupr wlllbeacknowldgd, lf EA - 1, each intoruplsourco is individually enablod ordlsblod bystting orcladns lP,4 tE.6 tE.5 tE.4 lP3 lP.2 pnoriv Denn6lheSedal PoriinteFupl l6v6l. PS= I prcSms illo ihehisher pdodtylevel. ,]'imer Defin6 lhe 1 inierupt priorit level. PTI = 1 programs ll b $ higher pnodtylevel. Oefn the Ext6malIntnupt I prloriv iitothehigher level. PX1= 1 programs pnodlytevel. Enabls or disables lhe llmer0 Inlerupt piorily l6vel.PT)= 1 progns it rc th6 prioriv highe! level. Dolins th Exl6melhtrrupl0 prlodly le@|. PXo= 1 proShms lt to lhehlgher pdoriiylov6l.

ES

E.ables ordisables ihoSsril Porl Interupt.lf ES = 0, ihe SedalPorl Enabls or dlsabl* lh limer 1 Overflow int6n'rpt.lr ETl = 0, the nmq 1 inlerupi Enabl$or disabl$Extonal In!6rrupi 1lf EXl = 0, Engmd Intnupt I idsbl6d. Enables or disabl* ihe Timer0 Overfow InEEupr. trcru = u,he Imeru hcrupr Enabl* or disbles Exetemal Intenupl 0. ll EXo= 0, Exiemal ln[erupi0 is diebled. PTO

ET1

rE.3
tE.2

lP.1 lPo

ETO EXO

tE.1 tE.0

Flgur 17. Int.rupt Enable {lE)R.glster

(lP)Rogbrr Flgu 16. In6.ruptPnodty

"-('

"4,
()'<'r

"4, .4,
I

Flgur t9, Inl.mpt Contrc!Ay3tem

1995 l'/arch

Piilips SemiconductoE

80C51Family

80C51 family architecture

IntefiuptStructure
The80C51 anditsROMlessand EPROM versions have 5 inierrupt porl $ur@s:2exteinal intsrupts, 2 timer iniRpis, andtheserial Whar iollows:s anovetuiew of ihe interrupr structlreior th dvlce. Infomatlon ior spocifrc monb3r6of lh 80C51 l\,{odralled deivalivefam y is provided in lalsr chapla6of lhis uer's suide. Eachinierupi solrce canbe individually enabled or disabled by lE (lntrupt s6ilins or cleaing a bilinth6SFRnamd Enable). Thi6 Fsisl$ alsocodainsa globaldisb16bit,lvhichcsn b6 cleared !o disable all inlenpls at once.FiguB 17 shows ihe lE rcgister poqEmhedio on6oi interupl solre n alsobeindividlally Each lwoprio ly levels byse$n! orcleadng a biiintheSFRnamed lP Flgurc 18shows lhe lP egislerA loepriorily Prlodly). {lntgrupl htrupt, but nol by 'nlerupt canbe lnleruptdby a hlgh-pnonly another low pdonty inierupt.A high-piorilyinteruptcnt b inGFupied byanyolher in!6mpt sour@. ll &o In16rupt requests of diferenlpriontybvels are recelved pdonvisseNlced. lf Intsrupl reqlest sjmullanously,lho ofhigher slmullaneously, an requesls oilhe samprloily levelarerecelved whlchrgqueslls srulcod. inlemalpolling sgqunc detefmlnes Thuswithineachpdonty bvel the i3 a secondpdodt 6lruclure sequen@. Figure 19sho$ howihelE dgtrrnhed bylhepolling workio dstermin which andlPglsle|s andihepolling sequence lt anvinleruDtwillbe 66Rlced. InopeElion, alllheintemplflags arelatched intolheinteFupl during Siale5 of everymachine cycle.Theemples cont'olsystem during thefollowing machine cycle. lilhe nagbran arpolled enabled intempl isfound to bsl(1),thoInlgnl]pl sysim genefates an LCALIlo lhs apprcpnat loclionin Prcgm Monory oiier@ndilion blockEthe inleFupt. Severa I condilione unloss some @nblockan inlrrupl, anong thmthat an Interrupt ot equalor hisherp orjlylevlis alradyin progrsss. qneraled LCALL causes iheconienls ofthe Thohardwar+ io b6 pushod inio ihe stack,and eloads ihe PC Prcgram Coun!r buune.as pfevlously wilhth beginning addrss of th6 serulce

(Figue noted 3),lheseruice rculineioreach inierupt bgins ai a pushed Program is automalically Onlylh Countr ontoihe shck, notlhs PSWor anyolherregislerHaving onlylhe PCaulomalically savsd allows lhs prcgBmmrio decid howmuch limeshould be spntsaving olhergislars,This enhan@s the idempt response lime, albeitatthe expense ol 'ncEasing ille progEmmels burden ot fsponsiblllty. As a rsult,manyInlampl tunclions lhat ai typiclin conttol applications toggling a podpinlorexample, orrcloadins a timeior unloading a sedal buffer canonen becompleied inle$ limelhanit iakesotherarchiteotuEs to compleie. Slmulatinga Thl.d Priorlty LevolIn Software Som6appllcauons qulfs morelhnhlo prlodlylsvelsthal are prcvidd byon-chip hadwafe in 80C51 dvic66.ln lh6s cass, rlslivgly simpl66onwscanb s.rit. lo poducgth sam6fecl as a lhird pioily lev|.Fit, inlsmpls t'at to hqvhighr pnodty lhan1 a assigngd to pnodty1 in lh6 Inloftlpl Pdoity (lP) rcgisterTheseNicercutines lor pnodty1 inieruptslhat are arewriltento slpposedto be lnterrupteble by pdonly2 interrupls lhefollowhg Include codol PUSHIE I''OV IE,#MASK CAIL LABEL (execute seruie outine) IE RET LABEL: As soonas a.y pnofty interupl ls acknowledged, the lnierupt (lE)rglster is edefrned 2 so astodisableallbutprjoniy Enablo inteftupts.lhn a CALLto LABE! excuts lh RETIinst.uclion, whichclears th piodly 1 intfiupi-in-progss fip-flop.At lhis poinl anypdonv 1 inteiruptthal b efsbled can be ssrviced, bul only priority 2 Inlenpls ars 6nsbl6d. POPing lE restorstheodginal enable byte. Then a nomdREI ihe seMceoutine. {ralherlhananotherRETI)is usedto terminate (ai 12MHz)topdoity Theaddlilonal $frwareadds1ojrs 1

1995 March

15