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name: _______________________

student number: _______________


THE UNIVERSITY OF NEW SOUTH WALES

School of Electrical Engineering & Telecommunications


FINAL EXAMINATION

JUNE 2003

ELEC3006 Electronics A


TIME ALLOWED: 3 HOURS
TOTAL MARKS: 100
TOTAL NUMBER OF QUESTIONS: 6

THIS EXAM CONTRIBUTES 70% TO THE TOTAL COURSE ASSESSMENT.


This paper contains 6 questions and 1 pages.
Candidates must .++ixv+ roun qiis+ioNs o:v.
All questions are of equal value, worth z marks each.
Useful data for this examination is appended on page 1.
This paper may not be retained by the candidate.
Answer each question in a separate answer book.
Slide rules and drawing instruments may be brought into the examination room.
Candidates may not bring their own electronics calculators.
An electronic calculator will be supplied by the Examinations Section.
All questions must be written in ink. Except where they are expressly required,
pencils may only be used for drawing, sketching or graphical work.
Question One [25 marks]

a) Figure 1 shows an operational-amplifier circuit with input V
i
and output V
o
.
You may assume that the op-amp is ideal.
i) By deriving a relationship between the output and the input, show that
this circuit is an ideal differentiator. [ marks]

Figure 1
This circuit, however, is sensitive to high-frequency noise. A more practical
version is shown in Figure z.
ii) Find the transfer function
( )
( )

j V
j V
i
o
and the sketch Bode plot (both
magnitude and phase) for the circuit in Figure z. [8 marks]

Figure 2
iii) Why is the ideal differentiator in Figure 1 sensitive to high-frequency
noise? Explain how the more practical circuit in Figure z is more immune
to noise. What is the limitation of the latter? [ marks]
2
b) A Miller integrator is shown in Figure below.
The component values are R = 10 k and C = 0.1 F.

Figure 3
i) Assuming that the op-amp is ideal, derive an explicit expression for the
output V
o
and show that the circuit does indeed act as an integrator.
[ marks]

In practice, this circuit will not operate as desired because uc imperfections in
the op-amp will give rise to an output offset current that will charge the
capacitor. The uc parameters of the op-amp are as follows:
input bias current I
B
= 100 nA (directed into the input terminals)
input offset current I
io
= 10 nA
input offset voltage V
io
= 2 mV
ii) The output offset current IC flows in the direction indicated on the
diagram. What is the worst-case output offset current if the input V
i
is
connected to ground? [6 marks]

Thus, even with no input (V
i
= 0), the op-amps uc imperfections lead to
saturation at VCC (the supply voltages), depending on the polarity of the
imperfections.
iii) Find the worst-case (i.e., minimum) time to saturation if the op-amp
output saturates at VCC = 10 V and the capacitor is initially discharged,
i.e., 0
0
o
=
= t
V volts. [z marks]
3
Question Two [25 marks]

A n,+ amplifier using a Darlington pair with emitter-feedback biasing is shown in
Figure below. Assume that the two transistors Q1 and Qz are matched, with
forward current gain = 1oo at room temperature and a base-emitter voltage drop
V
BE
= 0.7 V.

R
S
= 10 k R
B1
= R
B2
= 100 k R
C
= R
E
= 1 k


Figure 4

For parts (a) (e) below, assume switch S is open, i.e., CE is disconnected.
a) Neglecting base currents where appropriate, find the transistors quiescent
collector currents I
C1
and I
C2
, and the uc output voltage v
o
at the operating
point. [ marks]
b) Hence, estimate the hybrid- parameters g
m
and r

for each transistor.

[z marks]
4

c) Draw an .c equivalent circuit of the amplifier suitable for mid-band analysis.
[ marks]
d) Calculate the mid-band voltage gain
s
o
v
v
v
A = of the amplifier. You may assume
that the r
b
= 0, r

and the Early voltage V

A
. (Hint: It may be useful to
convert the left-hand side of the circuit to its Thvenin equivalent.) [; marks]

e) Determine the mid-band input resistance R
in
as shown in Figure . [ marks]

For parts (f) and (g) below, assume switch S is closed, i.e., CE is connected.
f) What would the values of quiescent collector currents I
C1
and I
C2
now be, with
CE connected in the circuit? [z marks]
g) Draw an .c equivalent circuit of the amplifier suitable for mid-band analysis in
this case. [ marks]
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Question Three [25 marks]

A n,+ amplifier in the cascode configuration, whereby the collector of a common-
emitter amplifier is directly coupled to the emitter of a common-base amplifier, is
shown in Figure j below. The transistors Q1 and Qz are matched, with forward
current gain = 1jo at room temperature.

R
1
= 33 k R
2
= R
3
= 22 k R
C
= 1.5 k R
E
= 1 k R
L
= 2.7 k
R
S
= 1 k C
B
= 10 F C
1
= C
2
= 1 F C
E
= 220 F


Figure 5
6
7
a) Given the quiescent collector current I
C1
= I
C2
= z.z mA through both n,+s,
estimate the hybrid- parameters g
m
and r

for each transistor. [z marks]

b) Draw the small-signal equivalent circuit of the amplifier in a form suitable for
low-frequency .c analysis. You may assume that the emitter resistor RE is
adequately bypassed, even at low frequencies. Omit r

from the small-signal

model (i.e., r

open-circuited). [ marks]
c) Draw the small-signal equivalent circuit of the amplifier in a form suitable for
high-frequency .c analysis. Again, omit r

from the small-signal model.

[ marks]

Now, for parts (d) (f), use the hybrid- capacitances C

= 2 pF and C

= 1 pF, and
assume that r
o
and r
b
= 0.
d) Calculate the lower corner ( dB) frequency f
L
using the short-circuit time-
constant method. You will have to calculate the time constants for C
1
and C
2
,
but you may assume that the short-circuit time constant associated with C
B
is

B
= .j ms. Use the dominant-pole approximation. [j marks]
e) Calculate the upper corner ( dB) frequency fH using the open-circuit time-
constant method. Use the dominant-pole approximation. [ marks]
f) Briefly explain the Miller effect. How does the cascode configuration lead to a
reduction of the Miller effect? [ marks]
Question Four [25 marks]

a) Figure 6 shows a relatively low-gain broadband amplifier known as the shunt-
series pair because of its feedback topology.

Figure 6
i) Two types of feedback topology are used in this amplifier. What are they?
Justify your answer and identify the network elements corresponding to
each of the two types of feedback topology. [ marks]
ii) Derive expressions for the loading resistances or admittances using the
appropriate two-port model for each of the two feedback networks.
[ marks]
iii) Draw the small-signal equivalent of the amplifier suitable for determining
the mid-band open-loop gain. Include the loading effects of the feedback
network. [ marks]
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b) A general amplifier model with series-series feedback is shown in Figure ;.

R
11
= 1 k R
22
= 50 k R
L
= 1 k R
F
= 100 h
FE
= 250


Figure 7

i) Using the appropriate two-port network model, derive an expression for
the feedback factor . [z marks]
ii) Determine an expression for the open-loop transconductance gain of the
amplifier
i
o
o
v
i
A = . Remember that the feedback network will load the
open-loop amplifier. [j marks]
iii) Hence, calculate the closed-loop transconductance gain A
f
. [z marks]
iv) Find an expression for the closed-loop output impedance of the amplifier
looking into the amplifier from R
out
as shown in Figure ;. Why is the load
resistance R
L
excluded? [j marks]
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Question Five [25 marks]

a) A monostable multivibrator employing a Schmidt trigger is shown in Figure 8.
This multivibrator is triggered by narrow negative pulse of sufficient height
applied at V
p
. The comparator has a saturation voltage V
m
= 10 V.
R
1
= 1.2 k R
2
= 10 k R
3
= 6.8 k C = 100 nF

Figure 8
i) What is a monostable multivibrator? Why might such a circuit be useful?
[ marks]
ii) Explain the operation of the circuit with the aid of graphs showing V
p
, V

and V
o
as a function of time when the appropriate trigger is applied at V
p
.
[j marks]
iii) By applying a pulse train at the input V
p
, this circuit could be used as a
square-wave generator. If a train of suitable pulses of width 1o s and
frequency z kHz is applied, calculate the duty cycle of the resulting
square-wave output at V
o
. [ marks]
iv) Suppose the frequency of the pulse train applied at V
p
is doubled to
kHz. Would the duty-cycle of the resulting square waves at the output V
o

simply be double that calculated in part (iii)? Justify your answer.
[ marks]
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v) It is often desirable for the output levels of a multivibrator to be more
precise than the saturation voltages of a comparator. How might the
circuit in Figure 8 be modified to clamp the output levels below the
saturation voltage of the comparator? [z marks]




b) The op-amp circuit in Figure below has two inputs v
1
& v
2
, and one output v
o
.
You may assume that both op-amps are ideal.

Figure 9
i) Show that the first stage of the circuit is an adder by deriving an
expression for v
x
as a function of the inputs v
1
& v
2
. [z marks]
ii) Find an expression relating v
x
and v
o
, and hence derive an explicit
expression for v
o
in terms of the inputs v
1
& v
2
. What is the function of the
second stage of this circuit? [z marks]
iii) Suppose that the sinusoidal signals v
1
(t) =
2
1
sin t and v
2
(t) =
2
1
sin 3t
are applied to the inputs v
1
& v
2
respectively. If both op-amps have a slew
rate of 1o V/s, what is the highest frequency at which the output v
o

will not be distorted? [ marks]

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Question Six [25 marks]

a) Figure 1o below is the diagram of an n-bit binary-weighted digital-to-analogue
converter. Each switch connects the corresponding resistor to the reference
voltage V
R
when its input a
i
= 1; otherwise, it connects the resistor to ground.

Figure 10
i) Show that this circuit does indeed work as a u.c by deriving an explicit
expression for the output voltage V
o
in terms of the digits a
i
of the binary
word. [ marks]
ii) What are the problems that arise when implementing a 16-bit u.c using
this method? (Write no more than a paragraph.) [z marks]
iii) Which other type of u.c might be more suitable for 16-bit conversion?
Justify your answer. (Write no more than a paragraph.) [ marks]
iv) Define the following three terms as they apply to digital-to-analogue
conversion: [ marks]
gain error
offset error
integral non-linearity
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b) With the aid of a diagram, describe the operation of a successive-
approximation analogue-to-digital converter. [j marks]



c) Answer the following questions. Use diagrams to support your answer where
necessary.
i) Explain how instability may arise in an amplifier circuit configured for
negative feedback. [ marks]
ii) What is a dominant pole? [z marks]
iii) Briefly discuss the principle behind dominant pole compensation.
[ marks]
Two-Port Network Parameters



Admittance Parameters


2 12 1 11 1
V y V y I + =
2 22 1 21 2
V y V y I + =

0
1
1
11
2
=
=
V
V
I
y

0
2
1
12
1
=
=
V
V
I
y

0
1
2
21
2
=
=
V
V
I
y

0
2
2
22
1
=
=
V
V
I
y

Impedance Parameters

2 12 1 11 1
I z I z V + =

2 22 1 21 2
I z I z V + =

0
1
1
11
2
=
=
I
I
V
z

0
2
1
12
1
=
=
I
I
V
z

0
1
2
21
2
=
=
I
I
V
z

0
2
2
22
1
=
=
I
I
V
z

Hybrid Parameters


V

2 12 1 11 1
V h I h + =
2 12 1 21 2
V h I h I + =

0
1
1
11
2
=
=
V
I
V
h

0
2
1
12
1
=
=
I
V
V
h

0
2
1
21
2
=
=
V
I
I
h

0
2
2
22
1
=
=
I
V
I
h

g Parameters


V

2 12 1 11 1
I g V g I + =
2 22 1 21 2
I g V g + =

0
1
1
11
2
=
=
I
V
I
g

0
2
1
12
1
=
=
V
I
I
g

0
1
2
21
2
=
=
I
V
V
g

0
2
2
22
1
=
=
V
I
V
g


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