DUAL PORT STATIC RAM TESTING

MANUEL J. RAPOSA

Sun Microsystems Inc Mountain View, CA 94043

ABSTRACT
The introduction of Dual-Port Static RAMs (DPSRAM) has meant solutions for designers of multiple processor systems, and confusion for the engineers who are required to implement component level test. This paper will show the basics of that test methodology which has been approved by Integrated Device Technology, the leading manufacturer of Dual-Port Static RAMs.

mode, this state of contention must somehow be resolved, with access granted to only one port. This arbitration can be implemented through software, or through the hardware features of a busy flag (/BSY), and semaphore flags (/SEM).

Difficult to test.
With little more than this background information and a data sheet, the test engineer must now develop a test strategy for this device. The strategy itself is not nearly as difficult to define as it is to implement. A standard Dual-Port has twice as many address, data and control lines as a typical SRAM of equal size. The arbitration and interrupt circuitry must be tested, and all the normal DC and AC tests must be performed on each port. The fundamental problem in testing DualPort Static RAMs is how to address the entire array from both sides individually. Any memory tester with dual pattern generators and dual timing systems would suffice, but most existing memory testers were designed and built before DPSRAMs were introduced, and offer no such solution. Therefore, the following three methods have been proposed, and the advantages and disadvantages of each will be explored.
1. Same address, both ports.

DUAL-PORT BASICS Just what is a Dual-Port?

A Dual-Port Static RAM is actually a single memory array with two wholly independent sets of interface logic (Figure A). Duplicate sets of address inputs, control lines, and I/Os, are both capable of accessing the same memory cell simultaneously, yet separately. This allows for truly asynchronous operation of this device by two completely unrelated processors or systems. One of the most common tasks performed by the DPSRAM is message passing. The ability of this device to be operated by two non-compatible systems makes it the ideal interface to pass data or messages. A function of this data transfer is the ability of either port to alert the opposing port of a pending message. This feature has been implemented in some Dual-Ports through the use of an interrupt flag (ANT), triggered by writing to a specific memory cell in the array. When not used for message passing, the device can be utilized unrestricted by either port, which leads to the possibility of both ports addressing the same cell. Should either of the ports be in a write

Tie the address lines from both ports together so that Xn drives both LXn and RXn. (L=left port, R=right port) With this method, both ports receive the same address.
2. Complement address.

Combine the above method with inverted drivers so that LXn = Xn, while RXn = /Xn. Using this method, the right port address is always the complement of the left port address.

Paper 20.3 362

1988 InternationalTest Conference

CH2610-4/88/0000/0362$01 .OO 0 1988 IEEE

2K x 8 MEMORY ARRAY

/LI\

ROW SELECT

ARBITRATION LOGIC

Figure A: Dual-Port Static RAM block diagram.

TEST

HEAD

Separation of ports. Assign XO thru Xn to the Left port A0 thru An. Assign Y O thru Yn to the Right port A0 thru An. (Figure B.) This method will provide independent addressing.
3. X 1 Y

Same address, both ports. This is accomplished by tying corresponding address lines together on the loadboard. The advantages of this scheme are readily apparent. This simplistic approach is easily implemented without requiring extensive hardware, but the disadvantages are equally obvious. Although the ports can operate independently with selective enabling, they cannot be tested simultaneously. Enabling both ports will force the device into address contention.

P 0 R T

Figure B: X / Y Separation of Ports.

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363

Complement address. This approach can be implemented either by manipulating the address formatters, or with the addition of inverters on the loadboard. The advantages again include simplicity, and the fact that the two ports will never be in contention. This is also a disadvantage though, as it becomes impossible to test the arbitration circuits. Complementing with inverters will certainly cause an unacceptable timing delay and reduce the accuracy of any measurements.
X I Y Separation of ports. This design uses the X address drivers to manipulate the left port, and the Y address drivers to manipulate the right port. It requires the tester to have twice as many VOs as the device, and at least 6 clock drivers. The advantage of this combination is totally independent addressing of ports. The disadvantages appear when writing topologically correct patterns, and as a requirement for address format control to adequately perform contention testing.
It is apparent that XiY separation of ports is the most logical solution. The pattern issue is solved through software, and the format control is handled with tester hardware. Plus, independent port access allows simultaneous AC testing of both ports.

Figure C shows a standard Checkerboard pattern in an array, and Figure D shows how that same pattern must be visualized and implemented to achieve the desired results. Another thing to consider when writing these patterns, is the AC testing of both ports simultaneously. With a March pattern for instance, the left port may begin writing at the top of the array, incrementing its way down. At the same time, the right port can begin writing opposite data at the bottom of the array and decrement its way up. By keeping this a one to one relationship, the even number of cells in the array will naturally avoid any contention.

0 1 o

i : j

l 0 1

; : ;

O 1 0

; : :

l 0 1

TESTING A DUAL-PORT
So how is it done?
By not distinguishing between rows and columns, we are misleading the tester with regard to the array configuration. For example, a 2K array may have 32 rows and 64 columns, but by combining all of the row and column address and assigning them to the tester X drivers, we are telling the tester that there are 2048 rows in a single column. This eliminates the usefulness of any standard pattern library. In fact, using this addressing scheme with a standard pattern, the tester would be expecting a 4 Meg array. New algorithms must be designed to produce the desired topological effect.

Figure C: Standard Checkerboard Pattern

Figure D: Dual-Port Static Ram Checkerboard Pattern

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Care must be taken at the crossover point, which occurs in the exact center of the array. At this point, each port must switch from "writing data" to "read opposite data, write data", continuing this to the end of the array. At that point, each port repeats the sequence in the reverse direction writing opposite data. At the conclusion, each port will have marched both 1's and 0's through the entire array, although not in the classic sequence. This technique of simultaneous testing can be applied to any pattern.

SemaDhore testing.
Semaphores are simply a set of latches which can be accessed by either port. Once a semaphore has been requested, and granted, it can only be released by the port it has been granted to. Normally there are multiple semaphores available, and they can be used for any purpose. While they are not physically tied to the memory array, they may utilize the same data and address lines. The simplest method of testing semaphore flags are to request, verify, and release every latch. A typical test sequence for 8 semaphore flags is outlined in Table 1.

Jntempt testing.
Interrupt testing is performed by writing data to the interrupt location while monitoring the ANT output of the opposing port. If the test system has sufficient comparators, one can be dedicated to the ANT output. Otherwise, a comparator may have to be switched from a data output to the ANT output. This can be accomplished with relays or FET switches on the loadboard.

Contention testinp.
Contention testing is by far the most difficult element of Dual-Port testing to perform. It requires a great deal of forethought and planning, and a firsthand knowledge of the hardware. In order to correctly test contention, we must first understand and then visualize the completed test. Only then can we develop an algorithm to implement it. A state of contention arises when both ports attempt to address the same cell simultaneously. The contention circuitry will arbitrate between the two ports, granting write access to the winner, and read only access to the loser. This arbitration is decided solely on the signal timing relationship, with the won / loss status being displayed by the busy flags (IBSY).

Arbitration testingA
Arbitration circuitry has taken on two major forms. First, contention circuitry which continuously monitors the address applied to both ports, activating a busy output (/BSY) when they match, and second, semaphore flags.

TABLE 1: Semaphore flag test sequence

STEP

Left Port

Right Port

1.
2.

3. 4.

5.
6. 7. 8. 9. 10.

Release all semaphores (0..7) Request all even semaphores (0,2,4,6) Verify even semaphores granted Request all odd semaphores Verify odd semaphores not granted Verify even semaphores unchanged Release all even semaphores Verify even semaphores were released Verify odd semaphores were granted Repeat steps 1-9 for odd semaphores

Release all semaphores (7..0) Request all odd semaphores (7,5,3,1) Verify odd semaphores granted Request all even semaphores Verify even semaphores not granted Verify odd semaphores unchanged Release all odd semaphores Verify odd semaphores were released Verify even semaphores were granted Repeat steps 1-9 for even semaphores

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If we use the IDT7132 as an example, the data sheet states that in order for a port to be guaranteed access to a cell, its address must arrive at least 5 nanoseconds prior to being addressed by the opposite port. This is specified as the Arbitration Priority Set Up Time (Taps). In other words, if we want to test this circuitry, we must be certain that the address applied to one port is stable for at least 5 nanoseconds before the opposing address arrives.

TEST FOR NON-CONTENTION, IGNORE ERRORS TEST FOR CONTENTION

COMX, HOLDY COMX, INCY INCX HOLDY

When the test system has separate timing generators for the X and the Y address drivers, then we can simply specify different timing for each. If however, there is a single timing generator for all address drivers, (as is the case with most existing memory test systems), we must be more clever in our approach. Basically what we must do is to apply the same signal at the same time to both ports, and have one arrive before the other. This can be accomplished by using both the single timing generator, and the address formatters. Suppose we specify the timing as follows: Period length 60nS Address start 1OnS Address stop 15nS Both ports enabled If in conjunction with this, we specify an address format of XYBAR, XY (inverted address followed by true address) we will get signals such as those in Figure E (1). If we now disable the Y complementor, we modify those signals to match those in Figure E (2). The effect, as you can see, is that of one signal arriving 5 nanoseconds before the other.

This pattern is designed for use with the Y address complementor disabled, and will allow that port addressed by the Y drivers to win the arbitration. The pattern is initiated with the X address at 0, and the Y address at N (address max). The pattern to test for the X drivers to win contention is identical except that the address states are switched, with the X complementor disabled. Sample waveforms resulting from this combination of pattern, format, and timing are displayed in Figure F.

DC testing.
DC testing is very much the same for DPSRAMs as it is for standard SRAMs. One area where differences do occur is standby current (Isb). With two ports, and each port at one of two possible levels (CMOS vs. TTL), 4 possibilities must be tested for. See Table 2 for the conditions of each.

OnS

lOnS 15nS

X address

N-l

XNx
-

I I
I

60nS

Now that we can achieve the timing required, we must turn our attention to the sequence. This is a two step process, forcing the condition that one port wins, then the other, and is easiest performed by writing separate patterns for left port and right port contention. Once contention has been tested for, it must be removed, and the /BSY flag under test verified to have returned to an inactive state. Once again, additional comparators are used, or switched into place to monitor the /BSY output. The pattern used must increment through each cell in the array, testing for both the active, and inactive state of the /BSY flag. The following 3 step pattern does just that, using step 2 as an ignore cycle to reconcile X and Y for the following step.

address N-l

xNx
I

X address, N-l

mNx
I

Y
address

N-l

)i:

Figure E. Combination effect of timing I format.

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TABLE 2: STANDBY CURRENT (Isb) CONDITIONS

SYMBOL PARAMETER TEST CONDITION

Isbl

Standby Current Both ports TTL level inputs Standby Current One port TTL level inputs

/CEL and /CER 1 Vih

lsb2

/CEL and /CER 1 Vih Active port outputs open F = Fmax /CEL and /CER 2 Vcc - 0.2V Vin 2 Vcc - 0.2V or Vin 0.2V One port /CE 2 Vcc - 0.2V Vin 2 Vcc - 0.2V or Vin 5 0.2V Active port outputs open F = Fmax

lsb3

Full Standby Current Both ports all CMOS level inputs Full Standby Current One port all CMOS level inputs

lsb4

CYCLE

Right Port address

Ay

-1
I
1

iI
I I

I I

iI

i
I I
I

I I
I

I I I
I

I I I
I
ACTIVl
I

BSY
(expected)

I
I

I
I

I I I

I I

I I
I

I I I
I I I

I INACTIVE I I I I I I
I

* $
I
I

I
I I

I I I
I

I I I

Strobe

I I I

I I I
I

I I
I
Ax = Ay

I I

I I

I I

NON

LINEAR

SCALE

Figure F.

Contention test resultant waveforms

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TESTER REOUIREMENTS
What is needed?
In order to successfully employ the X/Y Separation, the memory test system used must have sufficient address pins. In the case of a 2K x 8 DPSRAM, each port has 11 address inputs, and therefore requires the tester to have at least 22 address drivers (1l X , 11Y). The 8 data pins on each port necessitates a minimum of 16 tester I/O pins, with either 4 additional comparators, or the ability to switch relays needed in order to test /BSY and ANT. At least one parametric measurement unit (PMU) must be used to perform the DC tests. Performance of the AC tests requires a pattern generator capable of complex algorithms, some type of address format control, and a minimum timing pulse width less than or equal to Taps. Six clock pulse generators are required to isolate the chip enable (/CE), write enable (/WE), and output enable (/OE) functions of each port.

CONCLUSION
What has been described is a successful way of correctly testing Dual-Port Static RAMS. However, possession of this information alone does not make it an easy task. Loadboard design, software coding, debugging, and understanding the process are all time consuming and difficult. But with the above information, these difficulties can all be overcome.

ACKNOWLEDGMENTS
I would like to acknowledge Dave Barta for his work developing this methodology, and I would like to thank Chris Schott alid Jeff Vesey for their assistance in preparing this manuscript.

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