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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

Low-Voltage CMOS Current-Mode Preamplier: Analysis and Design


Fei Yuan, Senior Member, IEEE
AbstractThis paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplier is sat . The preamplier employs a balanced conguration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specic to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of networks to achieve both a at frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplier at high frequencies. The preamplier has been designed using a 0.18- m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplier has a at frequency response with 25.3 dB dc current gain or equivalently 60 dB transimpedance gain with a 50- load and bandwidth of 2.15 GHz.

Fig. 1.

Scaling of supply and threshold voltages.

Index TermsCMOS current-mode circuits, current feedback, inductive series peaking, preampliers.

I. INTRODUCTION

MOS current-mode circuits have found increasing applications in multi-Gbps data communication systems, such as optical communications, low-voltage differential signaling (LVDS) based point-to-point data links, and high-speed bus systems, to name a few. The most challenging block to design in these systems is the front-end, also known as the preamplier, arising from the stringent requirement on both the noise and bandwidth. Preampliers are often designed using a trans-impedance conguration to take its advantages of relatively low noise and large bandwidth [1]. In this conguration, a high current gain is achieved from an intermediate voltage amplication stage [2], [3]. Due to the existence of high-impedance nodes, the drawbacks of voltage-mode circuits, such as limited bandwidth and the need for a high supply voltage, can not be avoided. In addition, this conguration requires a current-to-voltage conversion stage, usually a passive resistor, which deteriorates the noise performance. It is advantageous to amplify the current directly [4]. It is well known that CMOS current-mode circuits have many intrinsic
Manuscript received July 28, 2004; revised March 9, 2005. This paper was recommended by Associate Editor I. M. Filanovsky. The author is with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON M5B 2K3, Canada (e-mail: fyuan@ee.ryerson.ca). Digital Object Identier 10.1109/TCSI.2005.854414

advantages over voltage-mode counterparts including low supply voltage requirement, wide bandwidth, tunable input impedances, high slew rates, and less susceptible to power and ground uctuations [5], [6]. These unique characteristics make current-mode circuits particularly attractive for multi-Gbps data communications [7], [8]. Two critical challenges exist in design of high-speed CMOS preampliers: (i) performance degradation caused by the aggressive reduction of the supply voltage of modern CMOS technologies and (ii) bandwidth and slew rate requirements to support multi-Gbps data rates [9]. The reduction in the supply voltage of modern digitally CMOS technologies originated by the aggressive downscaling of MOS devices has many prominent effects on the characteristics of monolithic CMOS circuits including high packing density, small device parasitics, high device speed, and low power consumption [10]. Unlike the supply voltage, the threshold voltage of MOS devices, however, is reduced at a rather slower pace, as shown in Fig. 1, mainly constrained by subthreshold conduction. As a result, reduced dynamic range, small effective gate-source , and low device output impedance [11] critvoltage ically affect the performance of CMOS current-mode circuits, particularly those that employ cascodes [5], [12]. In addition to supply voltage reduction, in design of multiGbps preampliers, the large capacitance of the media through which data are transmitted, such as the junction capacitance of photo diodes in an optical communication system and the parasitic capacitance of coaxial cables in a serial link, is often encountered at the input of preampliers. The bandwidth of netpreampliers is often set by the cutoff frequency of the work formed by this capacitance and the input impedance of

1057-7122/$20.00 2006 IEEE

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Fig. 2. Current amplier with inductive series peaking and its response. Circuit parameters: W = 10 m, W = 100 m, L A = 10.

= 0:18 m, J = 0:5 mA,

the preampliers [13]. A low input impedance is achieved traditionally by increasing the width of the input transistor and its dc biasing current, however, at the expense of chip area, power consumption, and bandwidth. Several circuit techniques that are based on active feedback at the input have been proposed recently to reduce the input impedance of current-mode circuits [14][16]. As demonstrated quantitatively in [17] that the effectiveness of these techniques vanishes at high frequencies. The technique introduced in [18] improves bandwidth by canceling out the dominant pole with a compensating zero introduced by the resistor inserted between the gates of the input and output transistors. The added resistor, however, affects the noise performance. Also, bandwidth enhancement is much smaller if the current gain is large. CMOS preampliers that have large bandwidth, sufcient gain, are able to operate at a low supply voltage, and suppress power and ground noise are critically needed for low-cost multi-Gbps data links. In this paper, we present the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplier. The proposed preamplier employs a balanced two-stage conguration to suppress mismatches-induced output offset current. In addition, we propose a new inductive series peaking technique to increase the bandwidth of current-mode circuits without affecting their DC characteristics. To further increase the bandwidth, a new current feedback mechanism is introduced. We show that this technique not only increases the bandwidth but also reduces the value of the peaking inductor. We further show that inductive series peaking improves the noise performance of the preamplier at high frequencies. The paper is organized as follows: Section II introduces an inductive series peaking technique specic to current-mode circuits and its effect on the bandwidth of CMOS current ampliers. Section III introduces a new current-current feedback technique for CMOS current-mode circuits and its effect on the input impedance and bandwidth. In Section IV, the joint effect of the inductive series peaking and current feedback is examined. Section V investigates the input impedance of the preampliers. In Section VI, the noise behavior of preampliers is examined. The dynamic range of the proposed preampliers

is investigated in Section VII. Section VIII presents a numerical study of the average slew rate of the preampliers. Low power design issues of current-mode circuits are addressed in Section IX. In Section X, the effect of mismatches is investigated in detail, and a fully balanced conguration that minimizes the bias-dependent offset output current is proposed. In Section XI, the design of a low-voltage fully balanced differential CMOS current-mode preamplier with both inductive series peaking and current feedback is presented. The layout of the preamplier and simulation results from SPICE are presented. Concluding remarks are given in Section XII. II. INDUCTIVE SERIES PEAKING When the channel length modulation and the high-order effects of MOS transistors are neglected, the basic current amhas a dc current gain plier shown in Fig. 2 with and bandwidth (1) where and are the transconductance and gate-source , respectively, , capacitance of transistor , and zero load impedance were assumed to simand the bandwidth plify analysis. The current gain are conicting design parameters. To increase the bandwidth without sacricing the current gain, we notice that inductive shunt peaking that employs a compensating inductor in parallel with the dominant capacitor is effective in boosting the bandwidth of voltage-mode circuits [19]. This technique, however, is not particularly applicable to current-mode circuits due to the existence of a biasing current source between the ac ground and the dominant pole of the circuits. Because the dominant pole of the current-mirror amplier is at the gate of the input and output transistors, a compensation inductor can be placed , as shown in Fig. 2. With the assumption in series with , the transfer function of the amplier is given by (2)

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

Fig. 3. Left layout of square-shaped spiral inductors in a 6-metal CMOS technology. Right lumped circuit model of planar spiral inductors.

with the poles at (3) We examine the preceding results in detail prior to further development: 1) The amplier has two identical real poles if , a pair of complex conjugate poles if , and two distinct real poles if . In the critically damped case where (4) the amplier has a at frequency response with no ringing in its step-input response. Its bandwidth is given by (5) If the inductance is further increased, a pair of complex ,a conjugate poles exist. When maximally at frequency response known as Butterworth response is achieved with bandwidth given by [21] (6) Note that in this case small ringing exists in the response of the amplier to a step input. 2) The added inductor does not affect the dc characteristics of the amplier. This is important because it not only ensures that the gain of the amplier will remain unchanged, the mismatch compensation circuitry to be introduced shortly will also not be affected. 3) The inductor is sized based on the criterion that a maximum at response and the maximum bandwidth are achieved simultaneously. To illustrate this numerically, the current amplier is analyzed using Spectre with BSIM3.3 device models that account for device parasitics. The response is plotted in Fig. 2 with inductor value varied from 0 to 20 nH. 4) On-chip inductors are usually implemented in a planar spiral conguration, as shown in Fig. 3 [20], [19], [22]. Multi-layer inductors have also been proposed recently

[23]. Planar spiral inductors have the following characteristics: (i) low quality factor arising from the ohmic loss at high frequencies; (ii) low inductance due to the loss of the magnetic energy caused by the planar structure; (iii) large parasitic capacitances to the substrate; and (iv) extremely area-greedy. Inductors larger than 100 nH is rarely used in practice [20]. The main design parameters , , , and the number of of planar inductors are , turns whose denition is given in Fig. 3. Typically is required to improve the inter-winding magnetic coupling and to reduce the chip area. Also, is often kept large to minimize the series resistance. The inductance is calculated using the well-known Greenhouse method [24]. A typical lumped equivalent circuit of planar spiral is the series reinductors is shown in Fig. 3, where sistance, mainly governed by the loss of the skin effect is the inductance, is the of the inductor layer, overlap capacitance between the spiral and the center-tap under-passes. The effect of the inter-turn fringing capacitance is usually small due to the nearly identical potential is the spiral-substrate capacitance. of adjacent turns, To minimize both the series resistance and parasitic capacitances of the inductors, the top metal layer should be used. Also, no devices should be placed in the area directly underneath the inductor. Several ground shielding techniques have been proposed most recently to reduce this interaction, among which patterned ground shielding is proven to be the most effective [22]. of the inductor does not affect 5) The series resistance the bandwidth of the circuit severely. As demonstrated in [18], when properly valued, this resistor helps increase the bandwidth of the amplier. For a 10-turn planar inductor implemented using m6 of a typical 0.18- m 6-metal 1-poly CMOS technologies, the series resistance is usually less than 10 . Fig. 4 shows that the series resistance of the peaking inductor increases the bandwidth marginally in this case. is in 6) The spiral-substrate capacitance of the inductor , and lowers the bandwidth of the amparallel with plier, as shown in Fig. 4. Its negative effect can be compensated by the resonant characteristic of the network , and . formed by ,

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Fig. 4. Left The effect of the series resistance of the peaking inductor on the bandwidth of the amplier (L 0 to 10
with step 2
); Right the effect of underpass capacitance C and inductor-substrate capacitance C (L = 15 nH, R = 0, C = C =3, and C is varied from 0 to 100 fF with step 25 fF).

= 15 nH, C = C = 0, and R

is varied from of the inductor on the bandwidth of the amplier

III. CURRENT FEEDBACK It was shown in the preceding section that inductive series times. The bandwidth peaking increases the bandwidth by enhancement obtained from the inductive series peaking is often insufcient to support multi-Gbps data rates. To increase the bandwidth without employing inductors. We notice that currentcurrent feedback is capable of lowering the input impedance and boosting the bandwidth [25], [27]. This mechanism, however, usually requires the insertion of a current-sensing element, usually a resistor, in the output current loop. The large voltage drop across the current-sensing resistor arising from the large dc current of the output branch, however, reduces the dynamic range of the amplier. To sense the output current without affecting both the dc biasing condition, we introduce a new current feedback mechanism shown in Fig. 5. It is worth noting that a similar approach was used in design of current-mode integrators [28]. Neglecting parasitic capacitances, the transfer function is given by (7) where pacitance of and is the gate-source ca. The bandwidth is given by (8) where was assumed. It is seen that as compared with the basic amplier, the bandwidth is increased by . The proposed current feedback has the folthe factor lowing characteristics. 1) Since there are only two transistors stacked between the power and ground rails in the feedback network and its conguration is identical to that of the output branch, no increase in the supply voltage is needed. 2) No high-impedance node exists in the circuit. This guarantees a small time constant at every node of the amplier. This is a typical characteristic of current-mode circuits.

Fig. 5. Current amplier with current feedback.

3) The feedback factor can be adjusted independent of the forward-path gain . This is critical because the bandwidth and the current gain of the amplier can be controlled by adjusting without affecting the dc characteristics of the amplier. 4) The feedback does not increase the output impedance of the preamplier. This is a drawback of this conguration. A large output impedance is desirable because it is equally important as a low input impedance in minimizing the loading effect of current-mode circuits. 5) The feedback reduces the current gain by the same factor . To have a sufciently large current gain, feedback must not be too strong. Clearly, a compromise between the bandwidth and gain is to be made. IV. INDUCTIVE SERIES PEAKING WITH CURRENT FEEDBACK It is evident from the preceding analysis that the bandwidth enhancement mechanisms of inductive series peaking and the current feedback differ fundamentally. This suggests that both techniques can be employed simultaneously to further improve bandwidth. Consider the current amplier of Fig. 6 where both techniques are employed. The transfer function of the amplier is given by (9)

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

Fig. 6. Left Current amplier with current feedback and inductive series peaking; Right frequency response of current amplier. Circuit parameters: W = = 0:18 m, J = 0:5 mA, A = 10. Top-left: L = 0, W = 1 m; Top-right: L = 10 nH, W = 1 m; Bottom-left: L = 0, 10 m, W = 100 m, L W = 10 m, Bottom-right : L = 6 nH, W = 10 m.

with poles at (10) In the critically damped case where (11) we have the bandwidth (12) In the case of a maximally at response where (13) the bandwidth becomes (14) Observed is that the bandwidth in this case is times times that of that of the amplier with inductor-peaking only, the amplier with current feedback only, and times that of the basic current amplier. Also seen is that the value of the series peaking inductor is reduced from without feedback to with feedback. The reduction of the inductance using current feedback is very attractive because a smaller inductor, subsequently, a smaller chip area and a less parasitic effect, is needed to achieve the same bandwidth. To demonstrate this, the current amplier is implemented in a 0.18 m CMOS technology and analyzed using Spectre with BSIM3.3 device models. Fig. 6 shows the frequency response of the amplier. The bandwidth enhancement from both inductive series peaking and feedback is evident.

V. INPUT IMPEDANCE As aforementioned that a low input impedance not only reduces the loading effect, subsequently improves the accuracy of current-mode circuits, it also plays a critical role in boosting the bandwidth of the ampliers. In this section, we examine the input impedance of the proposed ampliers. Assuming , and neglecting , , and the second-order effects, one can derive the input impedance of the ampliers and the results are tabulated in Table I. It is seen that the input impedance of ampliers without inductive series peaking has a low-pass characteristic. Current feedback reduces the input impedance. Also seen is that the input impedance of the ampliers with inductive series peaking exhibits a band-reject characteristic with the rejection frequency at the self-resonant frequency of the amplier (15) Current feedback increases the frequency of the minimal input impedance, resulted from the reduced effective inductance. The effect of the peaking inductor vanishes when . Fig. 7 plots the simulated input impedance of the ampliers. The peaking of is due to the parthe input impedance at frequencies beyond asitic capacitances that were not accounted for in the preceding derivation. VI. NOISE The noise of preampliers directly affects the overall noise performance of receivers. In Appendix A, the power of the and that of the noise input-referred noise voltage generator current generators of the proposed preampliers are derived and are tabulated in Table II. It is seen that the thermal noise of the gate series resistance and that from the channel contribute

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TABLE I INPUT IMPEDANCE OF CURRENT-MODE AMPLIFIERS

is the power of the thermal noise of where is the resisthe source resistance, is Boltzmanns constant, tance of the source, and is temperature in degrees Kelvin. The noise gure of the amplier with both series inductive peaking and and current feedback can be obtained by substituting of the amplier given in Table II into (16). To simplify analysis, we notice that the bandwidth of the am. Because the frequency plier is given by and , of the input is upperbounded by the terms in the expression of can be simplied as follows:

(17) As a result

(18)

The noise gure of the amplier is obtained from

(19) Fig. 8 plots the noise gure of the ampliers for the given circuit parameters. The relatively large value is due to the chosen circuit parameters. It is observed from the gure that current feedback deteriorates noise performance. Also, the ampliers without series inductive peaking levels up at high frequencies, mainly due to the increased coupling between the input and output stages. Series inductive peaking does not increases noise gure. It signicantly reduces noise gure at high frequencies.
Fig. 7. Input impedance. Top-right: amplier with current feedback; bottom-left: amplier with inductive series peaking; bottom-right: amplier with both current feedback and inductive series peaking. The same device sizes as those in Fig. 6 are used.

VII. DYNAMIC RANGE The lower bound of the input dynamic range of the ampliers is set by the power of the input-referred noise generators whereas the upper bound is determined by the level of the harmonic distortion at the output. Although there are many denition of the upper bound of the dynamic range of ampliers, such as using the amplitude of the input when 1% of total harmonic distortion is observed at the output [34] or when the distortion level equals to the noise level to set the maximum input amplitude, these methods, however, exclusively relies upon CAD tools. In this section, we give an efcient technique that uses the pinch-off condition to estimate the upper bound of the cur. rent-mirror amplier. Consider the basic amplier with is given by The pinch-off condition of the output transistor , where is the maximum

equally to and . The ampliers with current feedback exhibit a higher level of noise due to: (i) reduced current gain and (ii) additional noise from the feedback network. Inductive series peaking does not increase the noise. It, in fact, improves the noise performance of the ampliers, especially when frequency approaches the self-resonant frequency . The noise gure ( ) of the ampliers is obtained from (16)

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AND i

OF

TABLE II CURRENT-MODE AMPLIFIERS

, is the surface mobility of free where is the gate capacitance per unit area. For , electrons, and neglecting the effect of channel length modulation, we have (21) Substituting (20) into (21) yields (22) Equation (22) quanties the maximum input current, i.e., the upper bound of the dynamic range. The lower bound is set by the input-referred noise current generator given in the preceding section. Following a similar procedure, one can show that the maximum input current of the amplier with feedback is given by (23)
Fig. 8. Noise gure. Parameters used in simulation: sheet resistance of poly R = 8
, L = 10 nH, A = 10, f = 0:1, C =  =t = 85:78 10 F=M , effective gate voltage 0.3 V, W = 10 m, W = AW , W = Af W , L = 0:18 m, g = 0:958 10 A=V, g = 10g , g = Af g , C = C W L, R = 50
, and R = 50
.

output voltage set by the pinch-off condition of the device threshold voltage. At the pinch-off of

and is , we have

Equation (23) reveals that the current feedback improves the dynamic range. An an example, let and mA, we have mA without feedback and mA when . Fig. 9 plots the output current of the amplier for various feedback gains with the input current swept from 0 to 1.2 mA. The estimated upper bound of the input current agrees reasonably well with the simulation results. VIII. SLEW RATE

(20)

Slew-rate is a large-signal gure-of-merit quantifying the eye opening of the response. It is well understood that the slew rate

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Fig. 9.

Dynamic range (left) and average slew rate (right).

of voltage-mode circuits is set by the ratio of the dc biasing current to the value of compensation capacitor [27]. A number of techniques including dynamic biasing that improves slew rate by automatically increasing the DC basing current when a large input is encountered, and slew-rate enhancement (SRE) circuitry that employs additional circuitry to provide additional charging and discharging currents in the event of a large input [30][33], have been proposed to improve slew rate. These approaches, however, suffer from the following drawbacks. 1) Both dynamic biasing and slew rate enhancement circuitry are only sensitive to the magnitude not the rate of change of inputs. 2) Slew rate enhancement circuit must be carefully biased such that it is disabled under normal conditions and activated only when a large input is present. 3) Due to the increased circuit complexity, these circuits can not operate at high frequencies. Unlike voltage-mode circuits, the maximum current for charging and discharging the capacitor constituting the dominant pole in CMOS current-mode circuits is only limited by the maximum current set by the saturation constraint of transistors. The average slew rate of the amplier, dened as the time for the output current to a step current input to change from 10% to 90% of its steady-state value is shown in Fig. 9. It is seen that inductive series peaking improves the average slew rate. IX. LOW-POWER DESIGN One of the drawbacks of current-mirror ampliers is their high dc power consumption, arising mainly from the large dc current of the output branch. Consider the two-stage current am. Assume a perfect device plier shown in Fig. 10 with match and neglect the effect of channel length modulation. The and the biasing curoutput current is given by . To rerent of the output branch is given by duce the dc current of the output branch, the dc current source as shown in Fig. 10 is added. The channel current of is given by and that of is given by . If we impose and , then the output current is given by .

and , The total biasing As an example, let when and current will be when , a reduction of 81%! Power consumption can be further reduced by varying . This technique is particularly attractive for multistage current ampliers. Fig. 10 plots the frequency response of the circuit with and without this technique. It is seen that the bandwidth is increased from 857 MHz without employing this technique to 1.428 GHz with. Also observed is that the current gain is also increased. The total current drawn from the supply voltage is reduced from 7.48 mA without to 4.19 mA with. X. MISMATCHES AND COMPENSATION It is well understood that mismatches give rise to an output offset current in current mirrors. In this section, we show that the output offset current consists of bias-dependent and signal-dependent components. We further show that the bias-dependent output offset current is time-invariant and can be minimized using the balanced conguration proposed in this section. A. Output Offset Current . Consider the basic current amplier of Fig. 2 with In the following analysis, we shall use , , and to denote the total, the dc component and the ac component of the gate voltage, respectively. Similar conventions apply to other variables. Using the rst-order model of MOS transistors and mismatch, where is the gate oxide thickness, neglecting we arrive at (24) The output offset current due to -mismatch, -mis-mismatch, and -mismatch can be derived from match, (24) individually and the results are given in Appendix B. It is seen from Table III in Appendix B that the dc-dependent output offset currents are time-invariant whereas the ac-dependent output offset currents are time-varying. Also seen is that both components are directly proportional to the current gain.

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Fig. 10.

W = 50 m, M = 30 m for J

Power reduction technique for current-mode circuits. Circuit parameters: L = 0:18 m for all transistors, W = 5 m, W = 20 m, W = 10 m, . Transistor width for J and J is 10 m and 25 m, respectively.

TABLE III OUTPUT OFFSET CURRENT OF CURRENT-MODE AMPLIFIERS

The output current of the amplier with mismatches considered is given by (25) where the mismatch coefcient from in the worst case is obtained

Fig. 11.

Balanced conguration.

rent mirrors have the same mismatch coefcient analysis. Making use of (25)

to simplify

(26) where we have neglected the second-order terms and . In a similar manner (27) The difference of (26) and (27) yields the output current

or in a more standard form

B. Balanced Conguration The fact that the dc-dependent output offset current is time-invariant suggests that it can be minimized using the balanced conguration given below. Since the mismatch coefcient of nMOS mirrors differs from that of pMOS mirrors, the two-stage conguration consisting of a nMOS stage and a pMOS stage, as shown in Fig. 11, is employed. Note that both biasing current sources have identical paths to the output node. Because the difference between the mismatch coefcient of nMOS current mirrors is much smaller as compared with the difference between the mismatch coefcients nMOS current mirrors and that of pMOS current mirrors, it is reasonable to assume that all nMOS current mirrors has the same mismatch coefcient and all pMOS cur-

(28) It is evident that the output offset current is reduced from without the balancing network to with the balancing network. For class A usually holds, a current-mirror ampliers, because signicant reduction in the output offset current is achieved. To assess the effectiveness of this technique, the circuit of Fig. 11 was analyzed using Spectres Monte Carlo simulation and are assumed to be the same for all tools. Because nMOS and pMOS current-mirror pairs, respectively, the device , , dimensions are set as the follows: and are Gaussian with the mean and standard dewhere m and m, respectively. viation given by

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Fig. 12. Statistical analysis of balanced network. Circuit parameters: J = 200 A, A = A = 1, W = 10 m and L = 0:18 m. Only the dimension mismatch of nMOS mirrors is considered. The input is a sinusoid of frequency 1 GHz and amplitude 10 A, 20 samples in Monte Carlo analysis. Left balancing network is activated. Right balancing network is not activated.

Fig. 13.

Simplied schematic of differential current-mode preamplier. TABLE IV CIRCUIT PARAMETERS OF PRE-AMPLIFIER. ALL TRANSISTORS HAVE THE SAME CHANNEL LENGTH L = 0:18 m

Fig. 12 shows the output current of the circuit with 20 samples. It is observed that without the balancing network, the output current contains both the bias-dependent and signal-dependent A A. components and spreads over the range With the balancing network, the bias-dependent output offset current is removed. As a result, the spread of the output current is much smaller. XI. FULLY BALANCED DIFFERENTIAL CURRENT-MODE PREAMPLIFIER In this section, we apply the inductive series peaking, current-current feedback, and balanced conguration to the design a fully differential current-mode preamplier. The schematic of the preamplier is shown in Fig. 13 with its parameters given in Table IV. The dominant poles are located in the second stage and a pair of series peaking inductors are placed in the second stage. The preamplier is analyzed using Spectre with BSIM3.3 device model. All stages are biased carefully with biasing volt-

ages

V, V, V, and V. The frequency response of the preamplier is shown in Fig. 14. The dc gain of the preamplier without series inductive peaking and current feedback is 42.4. Its bandis used, the dc gain width is 0.747 GHz. When only

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A large number of vias were used to route signals from the top metal layer to lower metal layers to minimize the effect of contact and via resistances. Two series peaking inductors are placed and buses so that their effect on the core is minoutside imized. To minimize pad-to-substrate capacitances, only the top two metal layers (m6 and m5) were used to construct the pads. and , respectively, to reduce Four pads were used for the switching noise. To minimize the parasitic capacitance of the signal interconnects, the top metal layer was used to route both the input and output signals. Also, the interconnects neighboring the signal lines are placed as far as possible to minimize the mutual capacitances. No shielding is used for both input and output signals as it deteriorates the bandwidth. XII. CONCLUSION
Fig. 14. Frequency response of preamplier. L is varied from 5 to 25 nH with step 5 nH. The series resistance of the inductors is 5
.

drops to 18.45 and the bandwidth increases to 1.37 GHz. When and nH are used, the preamplier provides a differential dc current gain of 18.45 and bandwidth 2.15 GHz. With a 50 load, the preamplier provides a transimpedance gain of 60 dB . To analyze the effect of the spread of circuit parameters, in particular,devicemismatches,ontheresponseofthepreamplier. and are Monte Carlo analysis was carried out. Because assumed to be the same for all nMOS and pMOS current mirrors with the same input nMOS (pMOS) transistor size, respectively, , the device dimensions are set as the follows: , , , , , , , , , , , where , , and are Gaussian with mean m, m, and m, and standard deviation m, m, m, respectively. The series peaking inductor nH and standard deviation of is also Gaussian with mean nH. Fig. 15 plots the results of Monte Carlo simulation with 20 samples. As a comparison, the randomness of the width of of the preamplier was removed all biasing transistors and Monte Carlo analysis was carried out. The results are also plotted in Fig. 15. It is evident that the spread of the output current without the balancing network is much larger as compared with that with the balancing network. As pointed in [25] that the common-mode output of a differential amplier is mainly due to the mismatches of the amplier. Common-mode feedback is usually required to ensure that the common-mode output is well controlled so that transistors are always biased properly. In out implementation, common-mode feedback was not employed because the balanced conguration effectivelyminimizestheoutputcurrentresultedfromdevicemismatches, as evident from the results of Monte Carlo analysis. The layout of the preamplier is shown in Fig. 16. Symmetrical multinger interdigitized layout techniques were used to layout all matched transistors. In addition, a global n-well was used to house all pMOS devices. Multiple pull-up contacts were used to ensure that the n-well is well connected to the power rail.

The analysis and design of a low-voltage differential CMOS current-mode preamplier has been presented. The number of transistors between the power and ground rails is only two so that the minimum supply voltage of the preamplier is . To increase the bandwidth, inductive series peaking and current feedback, have been proposed. The inductive series peaking improves the bandwidth by making use of the resonant networks. The added inductor does not characteristics of affect the dc characteristics of the preamplier. It is sized based on the criterion of maximum bandwidth with minimum ringing. The effect of both the parasitic series resistance and shunt capacitances of the inductor on the performance of the preamplier has been investigated. To further increase the bandwidth, a new current feedback that is specic to low-voltage CMOS current-mode circuits has been proposed. No series current-sensing element is required. Because the mechanisms of inductive series peaking and current feedback differ fundamentally, they can be used simultaneously to achieve further bandwidth improvement. This has been conrmed from the simulation results. The employment of current feedback also effectively reduces the inductance needed for bandwidth enhancement. This is signicant because on-chip spiral inductors are extremely area-greedy not only because of its small inductance, but also because of the large clearance between spiral inductors and other neighboring devices set by the design rules of CMOS fabrication processes. Current feedback increases the noise of the amplier, arising from the thermal noise of the feedback network. The series peaking inductor does not increase the noise. Instead, it improves the noise performance of the amplier at high frequencies. The employment of current feedback increases the upper bound of the dynamic range. The output offset current of current-mode circuits consists of bias-dependent and signal-dependent components. The former is time-invariant whereas the later is time-varying. The biasdependent component can be minimized effectively using the balanced conguration. APPENDIX I INPUT-REFERRED NOISE OF PRE-AMPLIFIERS Here, we derive the power of input-referred noise voltage and that of the noise current generators of the generator

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Fig. 15. Monte Carlo analysis of preamplier. Top left: time-domain response with balancing network; top right frequency response with balancing network; bottom left: time-domain response without balancing network; bottom right frequency response without balancing network.

Fig. 17. Noise equivalent circuit of the preamplier with current feedback and inductive series peaking.

Fig. 16.

Layout of preamplier.

preampliers. The assumption is used for simplifying analysis. The noise equivalent circuit of the preamplier of Fig. 6 is shown in Fig. 17. Note that since the preampliers operate at high frequencies, the icker noise

of MOS transistors, which has a typical corner frequency of a few MHz [27], is neglected without introducing a large error. Further neglecting the thermal uctuation of diffusion current, the power of the thermal noise of the MOS transistor is mainly due to the thermal uctuation of the drift current [29], where for deep and is given by submicron devices [26]. The thermal noise of the gate series resistance is modeled as a noise voltage generator with its , where is the series resistance of power , and are the the gate computed from is the sheet width and length of the gate, respectively, and is typically in the range of 57 resistance of the poly gate.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

. The thermal noise of the gate resistance can be signicant as compared gate-referred noise of the thermal noise of the . The gate series channel given by resistance must be minimized in order to reduce its thermal noise. This can be achieved effectively using multi-nger layout , techniques from which the gate resistance becomes is the number of ngers. In this section, we neglect where the modulation effect of the thermal noise of the gate resistance on the transconductance of the transistors simply becomes , where is the dc gate voltage. As a result, the thermal noise of the channel is considered to be stationary and uncorrelated with the thermal noise of the gate series resistance. The noise generated by other parasitics of MOS transistors, such as source and drain bulk resistances is usually much smaller as compared with and , and is neglected here. Here, we derive the input-referred noise voltage generator and noise current generator of the amplier with the peaking inductor and current feedback. To derive , we rst short-circuit the input port and compute the total output noise power due to the noise sources in the circuit (29) We then remove all noise sources and compute the noise power only of the output current due to (30) Equating (29) and (30) yields (31) To derive , we rst open-circuit the input port and compute the output noise power due to all noise sources in the circuit

Fig. 18. Dimension mismatch. Left: MOS transistors with one nger. Right: MOS transistors with two ngers.

APPENDIX II MISMATCH-INDUCED OUTPUT OFFSET CURRENT In this Appendix, we analyze the output offset current of the current ampliers. A. -Mismatch

-mismatch is due to the variation of fabrication process. . Consider dimension mismatch only and let Since large transistors are normally laid out using multinger conguration to minimize both the gate series resistance and source/drain-to-substrate capacitances, the dimension mismatch of transistors with multinger conguration differs from that of transistors with single-nger conguration, as shown in Fig. 18. In the two-nger conguration case, whereas in the one-nger conguration . For ampliers with current gain of , we have (35) , , and denotes where mathematical expectation operator. Equation (35) reveals that mismatch. transistors with multiple ngers have a large Equation (24) becomes (36) where . It is seen that the smaller , the smaller the misthe dimension mismatch coefcient match-induced output offset current. B. -Mismatch

(32) The internal noise sources are then removed. The input-referred noise current generator is applied to the input port and the corresponding output noise power is derived

-mismatch is mainly due to process variation and unbalanced interconnects connecting the gate and source of the input -mismatch. Let and output transistors. Consider , . Neglecting the second-order term, we arrive at (37) where . Note that since the effective is usually small, contributes signifgate voltage icantly to the overall output offset current. C. -Mismatch

(33) Equating (32) and (33) yields

-mismatch is process-induced and can be analyzed in a -mismatch. similar way as (38) (34) where for -mismatch, . For the same reason as that -mismatch is critical.

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D.

-Mismatch mismatch, one can show

In a similar manner as that of that

(39) where . For long channel devices, because is small, the effect of channel length modulation is -mismatch is small. For deep negligible. So the effect of submicron devices, , however, must be taken into account. , , we have In practice, since and , subsequently and . This leads to

(40) The dc and ac components of the output offset current are tabulated in Table III. REFERENCES
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[17] F. Yuan and B. Sun, A comparative study of low-voltage CMOS current-mode circuits for optical communications, in Proc. IEEE MidWest Symp. Circuits and Syst., vol. 1, OK, Aug. 2002, pp. 315319. [18] T. Voo and C. Toumazou, High-speed current mirror resistive compensation technique, Inst. Electron. Eng. Electron. Lett., vol. 31, no. 4, pp. 248250, Feb. 1995. [19] S. Mohan, M. Hershenson, S. Boyd, and T. Lee, Bandwidth extension in CMOS with optimized on-chip inductors, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 346355, Mar. 2000. , Simple accurate expressions for planar spiral inductances, IEEE [20] J. Solid-State Circuits, vol. 34, no. 10, pp. 14191424, Oct. 1999. [21] A. Sedra and K. Smith, Microelectronic Circuits, 5th ed: Oxford Univ. Press, 1998. [22] C. Yue and S. S. Wong, On-chip spiral inductors with patterned ground shields for Si-based RF ICs, IEEE J. Solid-State Circuits, vol. 33, pp. 743752, May 1998. [23] A. Zolfaghari, A. Chan, and B. Razavi, Stacked inductors and transformers in CMOS technology, IEEE J. Solid-State Circuits, pp. 620628, Apr. 2001. [24] H. Greenhouse, Design of planar rectangular microelectronics inductors, IEEE Trans. Parts, Hybrids, Packag., vol. PHP-10, pp. 101109, Jun. 1974. [25] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001. , Design of CMOS Integrated Circuits for Optical Communica[26] tions. New York: McGraw-Hill, 2003. [27] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001. [28] S. Lee, R. Zele, D. Allstot, and G. Liang, CMOS continuous-time current-mode lters for high-frequency application, IEEE J. Solid-State Circuits, vol. 28, pp. 323328, Mar. 1993. [29] Y. Tsividis, Operation and Modeling of the MOS Transistors, 2nd ed. New York: McGraw-Hill, 1999. [30] J. Ramirez-Angulo and M. Holmes, A simple technique to signicantly enhance slew rate and bandwidth of one-stage CMOS operational ampliers, in Proc. IEEE Int. Symp. Circuits and Syst., vol. 2, 2002, pp. 835838. [31] J. Ramirez-Angulo, A novel slew-rate enhancement technique for on-stage operational amplier, in Proc. IEEE Int. Symp. Circuits and Syst., 1997, pp. 710. [32] H. Lee and P. Mok, A CMOS current-mirror amplier with compact slew rate enhancement circuit for large capacitive load applications, in Proc. IEEE Int. Symp. Circuits and Syst., vol. 1, 2001, pp. 220224. [33] K. Nagaraj, CMOS ampliers incorporating a novel slew rate enhancement technique, in Proc. Custom Integrated Circuits Conf., 1990, pp. 11.6.111.6.4. [34] G. Groenewold, The design of high dynamic range continuous-time integratable bandpass lters, IEEE Trans. Circuits Syst., vol. 38, no. 8, pp. 838852, Aug. 1991.

Fei Yuan (S96SM02) received the B.E. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering, and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, ON, Canada in 1995 and 1999, respectively. During 19851989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989, he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, ON, Canada. During 19891994, he worked for Paton Controls Limited, Sarnia, ON, Canada as a Controls Engineer. Since July 1999, he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada, where he is an is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the coauthor of Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with A. Opal). His current research interests include design and simulation of mixed analogdigital circuits for Gbps data communications. Dr. Yuan received the Ryerson Research Chair award from Ryerson University in January 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 19971998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. He is a Registered Professional Engineer in the province of Ontario, Canada.