Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology

Master thesis performed in Electronic Devices

Author: Golnaz Ebrahimi Mehr

Report number: LiTH-ISY-EX--13/4657--SE Linkping, April 2013

Design of a ROM-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology

............................................................................ ............................................................................ Master thesis Performed in Electronic Devices at Linkping Institute of Technology by Golnaz Ebrahimi Mehr

...........................................................
LiTH-ISY-EX--13/4657--SE

Supervisor: Dr. Behzad Mesgarzadeh Examiner: Professor Atila Alvandpour Linkping, April 2013

Presentation Date 16 April 2013 Publishing Date (Electronic version) 29 April 2013

Department and Division Department of Electrical Engineering Electronic Devices

Language English Other (specify below) 65 Number of Pages

Type of Publication Licentiate thesis Degree thesis Thesis C-level Thesis D-level Report Other (specify below)

ISBN (Licentiate thesis) ISRN: LiTH-ISY-EX--13/4657--SE Title of series (Licentiate thesis) Series number/ISSN (Licentiate thesis)

URL, Electronic Version http://www.ep.liu.se Publication Title Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS technology. Author(s) Golnaz Ebrahimi Mehr

Abstract

A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

Keywords Rom-Less DDFS, Current Steering Digital-to-Analog Converter, Interleaved DACs, Return-to-Zero, Sine weighted DAC

Abstract

A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

Key words: Rom-Less DDFS, Current Steering Digital-to-Analog Converter, Interleaved DACs, Return-to-Zero, Sine-weighted DAC

Acknowledgment
I would like to express my deepest appreciation to all the people who have helped me during the conduction of this thesis work. I would like to thank my supervisor Dr. Behzad Mesgarzadeh for his valuable ideas, guidance and help during this project. Thank you so much for the experience. I also would like to express my gratitude to Associate Professor Dr. J Jacob Wikner, for all his insightful discussions and guidance which was given with the most passion and generosity in time and knowledge. I am also grateful for all the valuable help that I have received from Petter kllstrm, Ph.D. student of Electronic System division, Ameya Bhide, Ph.D. student of Electronic Devices division, and Farrokh Ghani Zadegan, Ph.D. student of Embedded Systems Laboratory. I am also thankful from all other researchers who have helped me during this project. My special thanks to Amin Ojani, Ph.D. student of Electronic Devices division, for his discussions and technical help throughout this work. His enthusiasm and curiosity is admirable. A big thank you goes to my beloved family, my parents and my dear sister Golpooneh, for their unconditional love and support. I am also thankful to all my friends, who have enriched my life with love and joy. My acknowledgments to Linkping University, for providing all the resources that I needed to learn and grow.

Contents
Abstract ......................................................................................................................................................... 1 Acknowledgment .......................................................................................................................................... 2 Table of Figures ............................................................................................................................................ 5 Table of Tables ............................................................................................................................................. 7 Chapter1 Introduction ................................................................................................................................... 9 1.1 1.2 1.3 Motivation ..................................................................................................................................... 9 Thesis Organization .................................................................................................................... 10 List of Acronyms ........................................................................................................................ 11

Chapter 2 DDFS Principles and Architectures ........................................................................................... 13 2.1 Conventional DDFS .................................................................................................................... 13

2.1.1 The Phase Accumulator ............................................................................................................. 14 2.1.2 The phase to amplitude converter .............................................................................................. 17 2.1.3 The Digital to Analog Converter................................................................................................ 18 2.1.4 Anti-aliasing Filter ..................................................................................................................... 21 2.2 ROM-Less Direct Digital Synthesizers....................................................................................... 23

2.2.1 Direct digital synthesizer using a sine weighted DAC ............................................................... 23 2.2.2 Direct digital synthesizer using triangle to sine wave converter ................................................ 24 Chapter 3 Noise Analysis of DDFS output spectrum ................................................................................. 26 3.1 3.2 3.3 Spurious related to the phase truncation error............................................................................. 26 Spurious related to the DACs finite resolution .......................................................................... 28 Spurious related to the nonlinearities of the DAC ..................................................................... 28

3.3.1 Static performance ..................................................................................................................... 28 3.3.2 Dynamic performance ................................................................................................................ 32 3.3.3 Output spectrum of the digital to analog converter .................................................................... 35 3.4 The phase noise of the DDFS .................................................................................................... 37

Chapter 4 DAC Interleaving ....................................................................................................................... 38 4.1 4.2 DAC limitations for high frequency performance ..................................................................... 38 Different approaches for DACs interleaving ............................................................................. 39

4.2.1 Hold Interleaved DACs .............................................................................................................. 39 4.2.2 Data Interleaving DACs ............................................................................................................. 40 4.2.3 Data and Hold Interleaving DACs ............................................................................................. 41 3

4.3

The Interleaving and Return to Zero approach used in this project ........................................... 42

Chapter 5 Designed Direct digital frequency synthesizer ........................................................................... 46 5.1 5.2 5.3 System Overview ....................................................................................................................... 46 High Level Simulation Results .................................................................................................. 52 Transistor Level Simulation Results ........................................................................................... 55

Future Work ................................................................................................................................................ 64 References ................................................................................................................................................... 65 Appendix A ................................................................................................................................................. 68

Table of Figures
Figure2-3 Pipelined Phase Accumulator [18]........................................................................................... 16 Figure 2-4 Logic to exploit quarter wave symmetry [1]. ............................................................................ 18 Figure 2-5 N bit binary weighted current steering DAC. ......................................................................... 19 Figure 2-6 N bit thermometer coded current steering DAC. ...................................................................... 20 Figure 2-7 N bit segmented current steering DAC ...................................................................................... 20 Figure 2-8 Frequency response of DDFS (a) Ideal anti-aliasing filter (b), Realistic anti-aliasing filter (c) [5]. .................................................................................................................................................................... 22 Figure 2-9 DDFS Block Diagram using sine weighted DAC [2]..................................................................... 24 Figure 2-10 DDFS Block Diagram using triangle to sine wave converter [3]............................................... 25 Figure 2-11 TSC schematic (a), TSC transfer function (b) [18]. ................................................................... 25 Figure3-1 DDFS Spur Sources [1]. ............................................................................................................... 26 Figure 3-2 Transfer Characteristic of a DAC [20]. ....................................................................................... 29 Figure 3-3 Thermometer DAC with finite output current source impedance [7]. ...................................... 32 Figure 3-4 DACs full scale transition [20]. .................................................................................................. 32 Figure 3-5 The Current Cell of Current Steering DAC ................................................................................. 35 Figure 3-6 Image replicas and nonlinearities in a DAC [9] .......................................................................... 36 Figure 3-7. The ZOH and Sinc function of DAC............................................................................................ 36 Figure 4-1 Hold Interleaving DAC. ............................................................................................................... 40 Figure4-2 Data Interleaved DAC ................................................................................................................. 41 Figure4-3 Data and Hold Interleaving [9].................................................................................................... 42 Figure4-4 Interleaved DAC block diagram [9]. ............................................................................................ 43 Figure4-5 Image replicas of the first DAC (a ), Image replicas of the second DAC (b) and Image replicas of the Interleaved DACs (c) [21]. ................................................................................................................. 44 Figure 4-6 Return-to-Zero Effect[21] .......................................................................................................... 45 Figure 5-1The block diagram of the designed DDFS. .................................................................................. 47 Figure 5-2 The Block Diagram of Flash ADC ................................................................................................ 47 Figure 5-3 The comparator of ADC ............................................................................................................. 47 Figure 5-4 The block diagram of sine weighted DAC. ................................................................................ 49 Figure 5-5 The Current Cell of Current Steering DAC ................................................................................. 50 Figure 5-6 The implemented System .......................................................................................................... 51 Figure 5-7 Return to Zero, using discharge transistors ............................................................................... 52 Figure 5-8 The generated triangle and sine waves with FCW=1. ............................................................... 53 Figure5-9 The output spectrum of 1.75 GHz output frequency. ................................................................ 54 Figure5-10 The SFDR versus FCW ............................................................................................................... 54 Figure5-11 The sine wave generated with FCW=2, MHz and 3.2 GHz sampling frequency. .... 55 Figure 5-12 The sine wave generated with FCW=2, MHz and 6.4 GHz sampling frequency. ... 56 Figure 5-13 The output spectrum of DDFS MHz output frequency with 3.2 GHz sampling frequency. .................................................................................................................................................................... 57 Figure 5-14 The spectrum of MHz, with 6.4 GHz sampling frequency .................................... 58

Figure 5-15 The output spectrum of DDFS at Nyquist frequency (1.6 GHz) with 3.2 GHz sampling frequency. ................................................................................................................................................... 59 Figure 5-16 The Nyquist frequency output spectrum with 6.4 GHz sampling frequency. ......................... 60

Table of Tables
Table 5-1 The simulation results of this work ............................................................................................. 61 Table 5-2 The simulation results of previous works ................................................................................... 62 Table 5-3 The measurement results of previous works.............................................................................. 63

Chapter1 Introduction

1.1

Motivation

A direct digital frequency synthesizer (DDFS) uses digital signal processing to generate frequency and phase tunable output signals. The generated output frequency is a division of the reference clock frequency. The division factor is set in a binary tuning word [5]. The DDFS has the advantages of fast frequency switching, fine frequency resolution, direct digital phase and frequency modulation in the digital domain and low phase noise. DDFS has a variety of applications from instrumentations and measurements to modern digital communication systems. For example, they can be utilized as a clock generator, which produces output frequencies

with N the resolution of its phase accumulator. This characteristic is useful for the systems that need multiple clock frequencies with no integer relationship between them and they need to be changed rapidly and frequently [5]. In modern communication systems, DDFS seems to be an alternative to phase-locked loops (PLL). Fast switching speed is becoming more and more important in todays wireless communication systems, such as in spread spectrum communication systems. The limitation of the tuning speed of the PLL comes from the produced delay due to its internal feedback [1]. Aside from these advantages, DDFS is only capable of producing the exact integer division of the reference clock frequency when the FCW is 2 to the power of an integer. However, PLL has the ability to lock its output to the input phase of a reference clock. Moreover, PLL is capable of producing higher output frequencies. In order to take advantages of both PLL and DDFS, some applications use a hybrid frequency synthesizer, combining PLL and DDFS [5]. Moreover, conventional direct digital frequency synthesizers are considered power hungry systems due to the use of ROM look up table in their architecture [2]. Consequently, ROM-Less architectures has been introduced [2] [3]. The first approach in ROM-Less DDFS architecture was to use all thermometer sine-weighted DAC [4]. However, this approach needed a huge number of current cells. Therefore, to decrease the number of current cells segmentation algorithm for nonlinear DAC was proposed [12]. The segmentation of nonlinear DAC is more complicated than the linear ones and this architecture suffers from more complexity. The second approach in ROM9

Less DDFS design is to use the triangle to sine wave conversion. This method uses the parabolic approximation, and utilizes the exponential current-voltage relationship of the transistors to implement it electronically. This method shows a moderate precision in triangle to sine wave conversion [3]. In the DDFS design, the most important performance parameters are sampling rate, power consumption and spectral purity. However, a new figure of merit was introduced in [2] to also take in to account the amplitude resolution information. In order to achieve high sampling rates and high synthesized frequencies, the direct digital synthesizers are mostly designed in indium phosphide (InP) HBT, silicon germanium (SiGe) HBT and SiGe BiCMOS technology [3]. The effort in this project was to design a DDFS with multi-GHz sampling rate in 65nm CMOS technology, with high spectral purity. Interleaving with return to zero (RTZ) technique has been used to achieve a high bandwidth.

1.2

Thesis Organization

The organization of this thesis is as follow. In chapter two, the principles of the DDFS will be discussed through explaining the conventional DDFS architecture and the functionality of each block. Moreover, ROM-less architectures including the ones using nonlinear DAC and triangle to sine wave converter will be introduced. In chapter three, the error sources of the DDFS including the phase truncation error, the phase to amplitude conversion error, the introduced errors due to the nonlinearities of the DAC and the DDFS phase noise will be discussed. Chapter four will cover the limitations of DAC for having a wide bandwidth. In this chapter DAC interleaving principle and its different approaches will also discussed. In chapter five, the designed architecture in this project will be discussed and it will be followed by high level and transistor level simulations. Moreover, the results of the previous works with different architectures of DDFS will also be presented. The Verilog-A codes used for high level blocks including the phase accumulator and complementor can be found in Appendix A.

10

1.3
ADC

List of Acronyms
Analog-to-Digital Converter Bipolar complementary metal-oxide-semiconductor Clock Complementary metal-oxide-semiconductor Co-ordinate digital computer Decibel Digital-to-Analog Converter Direct Digital Frequency Synthesizer Delay-flip-flop Differential Nonlinearity Frequency Control Word Frequency-Shift Keying Greatest Common Divisor Third Order Distortion

BiCMOS CLK CMOS CORDIC dB DAC DDFS DFF DNL FCW FSK GCD

INL LSB LUT MSB MSK PAC

Integral Nonlinearity Least Significant Bit Look-up table Most Significant Bit Minimum-Shift Keying Phase to Amplitude Converter
11

PLL ROM RTZ SNR SFDR TSC ZOH

Phase Locked Loops Read-only memory Return-to-Zero Signal to Noise Ratio Spurious Free Dynamic Range Triangle to Sine Converter Zero Order Hold

12

Chapter 2 DDFS Principles and Architectures As it was stated earlier, Direct Digital Frequency Synthesizer, DDFS, uses digital signal processing to generate frequency and phase tunable output signals. In order to change the frequency of the output signal, frequency control word (FCW) or the frequency of the reference clock can be changed. In this chapter the DDFS principles are described through explaining conventional DDFS architecture. Also, the most common DDFS architectures will be presented.

2.1

Conventional DDFS

The block diagram of a conventional DDFS is shown in figure 2-1. The DDFS consists of a phase accumulator, a phase to sinusoid amplitude converter (PAC) and a digital to analog converter (DAC) followed by a filter. The phase accumulator consists of a counter and a register. The register restores the frequency control word (FCW), which is the jump size of the counter. With each clock cycle, the over flow of the counter is added to the FCW. The result of this counting is the production of the phase information of the sine wave. The output of the phase accumulator will be fed to PAC, which converts the phase information of the sine wave to amplitude. The discrete-time, discrete-amplitude information of the sine will be converted to analog by passing through a DAC. The final block of the system is an ant-aliasing filter. The functionality of each block is described in more details in the following sections.
FCW Phase Accumulator CLK Phase to Amplitude Converter Digital to Analog Converter Filter

Figure 2-1 The Block Diagram of conventional DDS.

13

2.1.1 The Phase Accumulator

The phase accumulator is basically a counter which has the responsibility of generating the phase information of the sine wave. In order to understand how the frequency is synthesized using a phase accumulator, consider the phase wheel in figure 2-2.

M = Jump Size

N 8 12 16 20 24 28 32

Number of points: 256 4096 65535 1046576 16777216 268435456 4294967296

Figure 2-2 Digital phase wheel [5].

14

Each point on the phase wheel is correspondent to an equivalent phase of the sine wave. A complete rotation of the phase wheel with constant speed will generate one complete period of a sine wave. In every clock cycle, the over flow of the counter is added to the FCW which is stored in the phase accumulator register. Consequently, FCW determines how fast the counter travels around the phase wheel. As a result of a higher jump size, the counter completes one rotation around the phase wheel faster, and consequently a higher output frequency will be synthesized. The resolution of the phase accumulator (N) determines how many phase points the phase wheel contains, and consequently it determines the resolution of the synthesized output frequency. For example, if N is taken to be 32, then the FCW of 00000001 will result the counter to overflow after reference clock cycles (a complete rotation) and gives the lowest possible output frequency. The FCW of 01111111 will result the counter to overflow after only two reference clock cycles (a complete rotation). The relation between the reference clock frequency output frequency the FCW and resolution of the phase accumulator is given in equation 2-1. Equation 2-1 = ,

According to Nyquist theorem, we need at least two samples per cycle in order to reconstruct the sine wave; consequently, the highest output frequency that we can achieve is equal to The frequency resolution of the synthesizer ( Equation2-2 As the phase accumulator is not able to complete multi bit addition in a short clock period, in order to run the DDFS in high speeds, pipelined phase accumulator is usually used. A pipelined phase accumulator is shown in the figure 2-3 [1]. is found when the FCW is set to one: .

15

As it can be understood from the above, all the signal processing operations which are needed for synthesizing and tuning the output frequency of the DDFS, is done in digital domain. This is why the direct digital synthesizers are so attractive for digital modulation techniques, such as FSK and MSK.

DFF Adder clk clk Adder clk clk clk

DFF clk DFF clk

DFF

DFF

DFF clk clk Adder

1s Com plime ntor

Adder clk

Figure2-3 Pipelined Phase Accumulator [18].

16

2.1.2 The phase to amplitude converter

After the phase information is generated by the phase accumulator, it will be fed to the phase to amplitude converter, which is a ROM look up table in the conventional DDFS. The look up table contains the amplitude information correspondent with each of the phase points of the phase wheel. In order to avoid a very large look up table, it is common to use only a fraction of the most significant bits of the phase accumulator information In order to produce a sine wave. In this case we say that the DDFS is truncated from k bits to j bits, for example from 32 bits to 12 bits. The truncation results in spurs in the output spectrum of the DDFS, which will be discussed in the next chapter. However, 12 bits still results in a large look up table. A large look up table decreases the speed of the synthesizer and increase the power consumption and die area, moreover a high resolution DAC will be needed to design. Therefore, a tremendous work has been done to reduce the size of the look up table. A very basic one is to use the quarter wave symmetry of the sine wave. The block diagram of this method is shown in the figure 2-4 [1]. In this case only the amplitude information of the 0 to /2 of the sine wave is stored in the ROM, and the two most significant bits of the phase accumulator output are used to distinguish the quarter of the sine wave. The most significant bit illustrates the sign of the sine wave amplitude and the second most significant bit is used to determine weather the amplitude is increasing or decreasing. Other ROM compression techniques include the Sunderland architecture, Nicholas architecture, polynomial approximation and CORDIC algorithm. In the Sunderland architecture the large look up table is divided in to two smaller memories. The Nicholas architecture has improved the Sunderland architecture and hence has achieved a higher ROM compression. In the Polynomial approximations, the coefficient of the polynomial is stored in the ROM. In this method the interval of [0, is divided in smaller divisions and the sine/cosine is produced in for each of

them. The CORDIC algorithm has its advantage over ROM when the needed accuracy is more than 9 bits. Using this algorithm the needed hardware is not growing exponentially when the output word size is increasing. For more information about this methods please refer to [1].
17

MSB 2 MSB
nd

Phase Accumulator

Complementor

/2 sine look up table

Complementor

2 /2 0 0

Figure 2-4 Logic to exploit quarter wave symmetry [1].

2.1.3 The Digital to Analog Converter

As it is shown in the figure 2-1, the discrete-time, discrete-amplitude information of the sine wave is fed to a digital to analog converter to be converted to a continuous-amplitude, continuous-time sine- wave. The current steering DACs are the best choice for high speed applications because of their fast switching speed. They can be implemented in binary weighted, thermometer coded and segmented architectures. The segmented architecture combines the binary weighted and thermometer coded architectures to take advantage of the benefits of both architectures. It uses thermometer coded for its most significant bits (MSB) and binary weighted for its least significant (LSB) bits. The binary weighted, thermometer coded and segmented architectures are shown in the figures 2-5, 2-6 and 2-7 respectively. As it can be seen in the figure 2-5, in the binary weighted architecture, each current source is as twice as much of the previous one. According to the digital input code a combination of the current sources will be switched to the output. This architecture has the advantage of small area and low power consumption. However, it suffers from differential nonlinearity (DNL) and the presence of
18

glitches, degrades its dynamic performance. On the other hand, thermometer coded architecture has more complexity and higher power consumption, but it has improved DNL, low glitches and small switching errors. In this architecture, all the current sources are equal. The digital input code is first fed to a thermometer decoder, and the thermometer code turns on the switches accordingly. Definitions and sources of the DAC nonlinearities will be presented in the next chapter. The segmented architecture uses the thermometer coded for its most significant bits, which are more responsible for the dynamic performance, and binary weighted for its least significant bits. A dummy decoder should be used for the binary weighted part to compensate for the delay of the thermometer decoder of the thermometer decoded part [9]. The considerations on how the resolution of each of architectures should be chosen in the segmented current steering DACs can be found in [19]. It has to be noted that in the DDFS the dynamic performance of the DAC plays a significant role in the spectral purity of the output spectrum, which will be discussed in more details in the next chapter.

4I

2I

Figure 2-5 N bit binary weighted current steering DAC.

19

Figure 2-6 N bit thermometer coded current steering DAC.

.. Thermometer Decoder Switch Driver

.. Decoder Dummy

Switch Driver

Unary Switches

Binary Switches

Unary Current Sources

Binary Current Sources

Figure 2-7 N bit segmented current steering DAC

20

2.1.4 Anti-aliasing Filter

As it will be discussed in more details in the next chapter, the DDFS is a sampling system. Therefore, there will be images at the frequencies of the output frequency and of the output spectrum, with

the sampling clock. As the result of the zero order hold function.

functionality of the DAC, the amplitude of the images are weighted by the

For most applications, these images are undesirable. In order to remove these images, a filter by an inverse function called anti-aliasing filter is used at the end of the system. Ideally,

this filter should have unity response over the Nyquist bandwidth and zero beyond that. However, designing such a filter is not practical; consequently, some percentage of available bandwidth will be unusable. Therefore, the synthesized output frequency of DDFS is usually limited to less than 3/8 of sampling frequency [2]. Figure 2-8(a) shows the spectrum of the DDFS, taking in to account only the image replicas. Figure 2-8 (b) and (c) show the effect of the ideal and non ideal filter on the output spectrum of the synthesizer. The design of this filter is beyond the scope of this thesis.

21

Amplitude

Frequency

(a)

Amplitude Ideal filter response

No aliases Frequency
Amplitude No aliases Frequency
/2

(b)

Amplitude Realistic filter response

Supressed aliases Frequency

Amplitude No aliases Frequency
/2

(c)

Figure 2-8 Frequency response of DDFS (a) Ideal anti-aliasing filter (b), Realistic anti-aliasing filter (c) [5].

22

2.2

ROM-Less Direct Digital Synthesizers

As it was stated earlier, the ROM look up table is the speed, power and area bottleneck of direct digital synthesizers. Although a tremendous work has been done to compress the ROM look up table, direct digital synthesizers using this method still have high power consumption and limitations in higher frequency operations [3]. Consequently, ROM-Less architectures has been introduced. The two most common ones are described briefly in the following section.

2.2.1 Direct digital synthesizer using a sine weighted DAC

In order to reduce the power consumption of direct digital synthesizers, ROM-Less architectures based on sine weighted DACs has been proposed [4]. The block diagram of DDFS using a sine weighted DAC is shown in the figure 2-9. In this architecture the sine/cosine mapping and the digital to analog conversion are performed in a same block, called sine weighted DAC. The design challenges of the sine weighted DAC is mostly the same with the linear DAC. The main difference between the sine weighted DAC and linear DAC is that in the linear DAC the current sources are identical with each other or they are a power of two weighted. However, in the sine weighted DAC the current sources are weighted according the amplitude of the sine wave [2]. In this architecture, for each phase of the sine wave the sine weighted DAC switches the corresponding amount of current to the output. The most two significant bits are used to exploit the quarter wave symmetry of the sine wave. Initially, these architectures used all thermometer sine weighted DACs. In order to reduce the number of DAC cells, segmentation techniques were proposed [12]. Segmentation techniques for nonlinear DACs are more complicated than for linear ones, and these architectures suffer from complexity when the resolution is high [3].

23

MSB 2 FCW
nd

MSB

Phase Accumulator

Complementor

Nonlinear DAC

CLK

Figure 2-9 DDFS Block Diagram using sine weighted DAC [2].

2.2.2 Direct digital synthesizer using triangle to sine wave converter

The block diagram of a DDFS using triangle to sine wave converter is shown in the figure 2-10. This architecture uses the most significant bit to exploit the half wave symmetry of the sine wave; consequently, it decreases the truncation error. The output of the complementor will then fed to a linear DAC. The linear DAC produces a triangle wave which contains the analog phase information of the sine wave. The triangle wave is then converted to a sine wave using an analog sine-mapping methodology. This methodology uses the parabolic approximation, which is implemented electronically by using the exponential current-voltage relationship of the transistors [3] [18]. Figure 2-11 shows the schematic and transfer function of the triangle to sine wave converter [18]. This architecture has a simple and low power structure and shows a moderate precision in triangle to sine wave conversion [3].

24

MSB FCW Phase Accumulator Complementor Linear DAC Triangle to Sine Converter

CLK

Figure 2-10 DDFS Block Diagram using triangle to sine wave converter [3].

Output signal Transfer function

Analog triangle from DAC (a)

(b)

Equation2-3: Equation2-4: Equation2-5:

-1

Figure 2-11 TSC schematic (a), TSC transfer function (b) [18].

25

Chapter 3 Noise Analysis of DDFS output spectrum

The direct digital frequency synthesizer has four sources of spurs, which is shown in the figure 3-1. These error sources include the truncation error of the phase accumulator, the phase to amplitude conversion error, the errors due to the nonlinearity of the DAC and also the phase noise. In this chapter these error sources and their effect on the output spectrum of the DDFS are discussed.

FCW

Phase Accumulator

Phase to Amplitude Converter

Digital to Analog Converter

Reference Clock

Reference Clock Spurs Noise Phase Truncation Spurs Angle to Amplitude Error Spurs Nonlinearity of the DACs Spurs

Figure3-1 DDFS Spur Sources [1].

3.1

Spurious related to the phase truncation error

As it was stated earlier, in order to have fine frequency resolution we would like to increase the resolution of the phase accumulator. However, this would result in large circuits that are needed to convert the phase data to amplitude data. Therefore, the output of the phase accumulator is usually truncated from N bits in to P bits. This truncation will result in a phase error between the generated phase by the accumulator, and the phase that is used by the PAC for amplitude generation; consequently, there will be an error in the generated amplitude. This error is periodic
26

in the time domain and hence shows itself as spurs in the frequency domain [5]. The periodic nature of the error is due to the fact that after sufficient rotation of the phase wheel the accumulator phase and the truncated phase will coincide and there will be no phase error. The pattern will continue as the phase accumulator continues to count. However, certain frequency control words result in the maximum level of the phase truncation spurs while some result in no error. The control words that yield the maximum spurs level should satisfy the following equation [5]: Equation3-1
(FCW, )=

Where, GCD denotes the greatest common divisor between the two variables in the parentheses. Hence, any control word with 1 in the bit position of and 0 in all other least significant

bit positions will result in the maximum truncation spurs level. Moreover, the control word that yield to no truncation error should satisfy the following equation [5]: Equation3-2
(FCW, )=

Hence, any control word with 1 in the bit position of

and 0 in all other least significant

bit positions will result in no phase truncation spurs. The generated spurs due to the phase truncation are the most significant spurs, if we consider the DAC ideal. They will be mixed by the DDFS output frequency, and will generate spurs at multiples of the output frequency, which is calculated by the following equation [1] [2]: Equation3-3

27

3.2

Spurious related to the DACs finite resolution

The finite resolution of the DAC and consequently the finite number of quantization levels of the DAC will result in an error, called the quantization error. The quantization error is basically the difference between the amplitude of the reconstructed sine wave and the ideal sine wave, which is due to the limited resolution of the. This error will show itself as spurs in the output spectrum of DDFS. The quantization error can be decreased by increasing the resolution of the DAC. The relationship between the resolution of the DAC and the amount of quantization distortion can be quantified with the following equation [5]: Equation3-4 1.76 + 6.02P

Where, P is the number of bits of the DAC and SQR is the ratio of the signal power to quantization noise power. It should be noted that this equation does not provide any information about the total SFDR of the system, and only considers the spurs due to the quantization error.

3.3

Spurious related to the nonlinearities of the DAC

The most dominant spurs in the output spectrum of the DDFS is the spurs related to the nonlinearities of the DAC. Both static and dynamic nonlinearities will be discussed in the following section; however, in high sampling rates circuits the dynamic nonlinearities play the significant role and being statically linear is the prerequisite for the DAC to have a good dynamic linearity [6].

3.3.1 Static performance

The static specifications of a digital to analog converter include offset error, gain error, integral nonlinearity (INL) and differential nonlinearity (DNL). These errors will result a nonlinear
28

relation between the actual output level produced by the DAC and the ideal output level that the designer expects; consequently, there will be harmonic distortions at the output spectrum of the digital to analog converter. Figure 3-2 shows the ideal and actual transfer functions of a three bit DAC, together with the correspondent static nonlinearities, which is briefly discussed in the following section.

Analog Output

Ideal Straight Line Actual transfer function

1 LSB DNL

INL

Ideal transfer characteristic

Offset

Digital Input 000 001 010 011 100 101 110 111

Figure 3-2 Transfer Characteristic of a DAC [20].

Offset error: offset error is the shift in the transfer function of the DAC on the vertical axis, and it shows that for an input value of zero, the DAC will output an analog value, not equal to zero. Gain error: In the transfer function of the DAC, the difference between the actual slope and the ideal slop is defined as the gain error. The gain error is not of a big concern when a single converter is being used, because rather than the absolute accuracy, the relative accuracy is of concern [6].

29

Monotonicity: The monotonicity of a digital to analog converter is its ability to decrease or increase in the same direction of its input signal. Integral nonlinearity (INL) and differential nonlinearity (DNL): If we consider a line that passes through the end points of the transfer function of the DAC, the integral nonlinearity (INL) would be the maximum deviation between that line and the actual analog output of the DAC. The differential nonlinearity (DNL) is the difference between the actual step size and the ideal one least significant bit step size in the transfer function of the DAC. These errors are shown in the figure 3-2. The differential nonlinearity can be given in terms of least significant bit step sizes with the normalized form according to the following equation [20]: Equation3-5 In the above formula, and are the analog outputs corresponding to two successive

codes of the converter. Moreover, the integral nonlinearity can be given as the accumulation of previous differential nonlinearity errors according to the following equation [20]: Equation3-6 In the above formula, and = are the actual and ideal analog outputs of the converter.

Mostly, transistor mismatch in the current source of the DAC cells and the finite output impedance of the current sources are responsible for INL and DNL [6]. Care has to be taken when designing the current cells to have as much matching as possible, to meet the static specifications. This can be done by using sufficient gate area for current source transistors, short distance between the transistors and equal environments by using dummy transistors [7]. Moreover, there have been introduced some techniques, such as dynamic element matching, calibration technique and trimming to overcome the matching problem of the DAC. However, as these techniques introduce more complicated circuits and consequently more parasitic capacitance, they do more harm than good in high frequencies [7]. The finite output impedance of the DAC current sources will also result in distortion in the output spectrum of the DAC. Figure 3-3 shows a thermometer coded DAC. The current sources are considered ideal with current value of and finite output impedance of . N corresponds to total number of current

30

sources and n is equal to the digital input code. With different input codes, different number of current sources will be connected in parallel with the output load and consequently, the total

effective load impedance will be dependent on the input signal [7]; hence, the output voltage will be signal dependant which will produce distortion in the DACs output spectrum. The produced output voltage correspondent to the digital input word (n) in the figure 3-3 is equal to [7]: Equation3-7 }

For full swing condition (n=N) the expression for the third order distortion can be written as [7]: Equation3-8 As it can be seen from the above formula, for having a low third order distortion, a high output impedance from each current source is needed. In low frequencies this can be achieved by using cascade transistors; however, for high frequencies this is not a sufficient solution, as will be discussed in the next section.

31

Figure 3-3 Thermometer DAC with finite output current source impedance [7].

3.3.2 Dynamic performance

The dynamic errors of the digital to analog converter include glitches, settling time and feed through effects. These errors are shown in the figure 3-4. Dynamic errors have a significant impact on the performance of the DAC and they even become more critical for higher output frequencies and sampling rates. These errors are presented in the following section.

Analog Output

Glitch

Clock Feedthrough Ideal Transition

Settling Time Time

Figure 3-4 DACs full scale transition [20].

32

Glitches: Glitches happen as a result of an unmatched switching time between different bits, which can be due to skew between bits in the digital part or the timing mismatch in the switches of the DAC. The result is a signal dependant error from the inputs to the output of the DAC during the code transitions. For example, consider the case that the input code is changing from 0111 to 1000. If the switching time of all the current cells do not be synchronized, it is possible that we get the analog converted of 111 for a very short period in the output; consequently, a glitch will be occurred in the output. Figure2-3 shows this situation. This phenomenon is much severe in high frequencies. Careful layout and using thermometer decoding can be used to degrade this effect. Settling time: is defined as the time which is needed for the analog output to settle between the accepted error band of its final value and is due to the parasitic capacitances of the circuit. The settling time should be kept as small as possible to have a low distortion on the analog output signal. Feed through effects: feed through effects have two sources in a DAC cells. The first one is the feed through of the digital signal through or of the switch transistors, which actually results in distortion in the Nyquist bandwidth of the output spectrum, since its a code dependant error. This error can be minimized by a careful layout and switches sizing. The second one is the feed through of the clock to the analog output, which also can be reduced by minimizing the size of the switches and hence reducing the capacitive coupling of the switches to the output. All the dynamic nonlinearities associated with the switches can be addressed by using return to zero (RTZ) technique, which can be implemented both with analog or digital solutions. In analog return to zero technique the output of the current cells is forced to zero when the clock is low and their current is switched to the output only when the clock is high; consequently, the switching transients do not appear in the DACs output. As it was stated earlier, finite output impedance of the DAC will also result in dynamic nonlinearities. A current cell of a current steering DAC is shown in Figure3-5. In the previous part it was assumed that the output impedance of the current sources are purely resistive. However, at higher frequencies this impedance is modeled as the resistor in parallel with the effective output capacitance [7]:

33

Equation3-9

Accordingly, the third order distortion can be calculated as [7]: Equation3-10 Where, N is the number of current sources. As it can be seen, higher frequencies will result in higher third order harmonics. Moreover, it can be seen in the above equation that the frequency of the DAC is limited due to the minimum achievable amount of . This is one of the limiting

factors for designing high speed DACs, which will be discussed in more details in section the next chapter. As it can be understood from the above explanations, sizing the transistors properly plays an important role in both static and dynamic performances of current steering DACs. For current source (M2) the high output impedance and matching is of concern. Therefore, large sized transistors together with cascade transistors (M1), with both M1 and M2 working in the saturation region, is the desirable choice. However, in order to reduce the parasitic capacitances at the sources of the switches, the cascade transistors (M1) should be just large enough to be able to support the current. For switches (M) we would like to have small on resistance and minimum feed through effect. As the switches work with high gate-source voltage, minimum sized

transistors can be chosen for them [7].

34

Digital Circuit s

Digital Circuit s

M1 Biasing Circuits M2

Figure 3-5 The Current Cell of Current Steering DAC

3.3.3 Output spectrum of the digital to analog converter

The output spectrum of a DAC is shown in the figure 3-6. As it can be seen, the output spectrum consists of harmonics and image replicas. Harmonics rise from the DACs nonlinearities, as it was discussed previously. They will be mixed between the clock and the signal and will result in spurious components at the locations of , for integer values of m and n [9]. Image

replicas rise from the sampling characteristics of the DAC. Taking in to account the Poisson summation, the frequency domain of an ideal sampled signal is written as: Equation3-11 ,with the )

the sampling frequency. Consequently, the output spectrum will be the summation of . It also should be noted that the

the fundamental signal and all the images locating at

amplitude of these images are decreasing in time. This is because of the zero order hold (ZOH) behavior of the DACs response in the time domain. As the DAC samples the input in every clock cycle, the analog output will have a zero order hold function, with the Sinc function as its Fourier transform. The time domain ZOH function and frequency domain Sinc function is shown in the figure 3-7. The amplitude of the Sinc function decreases in time, which leads to the
35

decrease of the amplitude of the images. It should be noted that the harmonics do not follow the Sinc function and it is not possible to predict their magnitude [5]. According to the Nyquist theorem at least two samples is required per cycle, in order to reconstruct the desired output waveform.

Signal

Image Replica Nonlinearity Hold Distortion

Figure 3-6 Image replicas and nonlinearities in a DAC [9]

-2/ Time Domain

2/

Frequency Domain

Figure 3-7. The ZOH and Sinc function of DAC

36

SFDR and SNR are the most common terminologies that are used to describe the performance of the output spectrum of the DAC. SFDR stands for spurious free dynamic range and is the ratio between the signal power and the strongest spurious component in the output spectrum. SNR stands for signal to noise ratio and is the ratio between the signal power and the total power of the summation of all spectral components, excluding the harmonics. The SNR of an N bit DAC is approximately given by [9]: Equation 3-12

Where, PN is the power of the total noise produced by the noise of the circuit (including the thermal noise and flicker noise) and the quantization noise. the lower limit of the SNR is contributed by the quantization noise[20]. The SFDR is calculated as: Equation 3-13 SFDR= 10log (PS/PH)

Where, PH is the power of the strongest distortion component.

3.4

The phase noise of the DDFS

The dominant contributor to the DDFS phase noise is the phase noise of the reference clock. In fact, because DDFS is a divider of the sampling clock, the purity of its output spectrum is directly affected by the purity of its reference clock. However, DDFS has a great advantage over PLL regarding to its phase noise. This is because PLL multiplies the phase noise of the reference clock in its feedback loop, but DDFS is a feed forward system, which its output is a fractional division of the reference clock; consequently, the phase noise which presents in the output spectrum of DDFS decreases by 20 log (N), where N is the division ratio. Moreover, as DDFS is a sampling system and the time interval between the samples are important, and the jitter of the reference clock will have an important role on the output spectral purity.

37

Chapter 4 DAC Interleaving

Interleaving has shown promising impacts on expanding the usable bandwidth of analog to digital converters. Consequently, interleaving the digital to analog converters also became an interesting approach for increasing their high sampling rate performance. In interleaved ADCs the same input signal is fed to all sub ADCs, which are sampled at multiple phases of the clock. However, because of the zero order hold response of digital to analog converters, this approach is not as straight forward as ADCs for them. DAC interleaving categorized in two groups, data interleaving and hold interleaving [9]. In this chapter, after discussing the performance limitations of the digital to analog converters for high sampling rates and wide bandwidth, different methods of interleaving DACs will be briefly described and this will be followed by discussing the interleaving and return to zero technique used in this project and its influence on the output bandwidth.

4.1

DAC limitations for high frequency performance

High frequency performance of digital to analog converters is limited for the following three main reasons [9]: 1) As it was stated in the previous chapter, DAC has a zero order hold behavior in the time domain and consequently a Sinc frequency response with a null located at result in amplitude distortion for high frequency generated signals. 2) According to the Nyquist theorem the applicable bandwidth of the digital to analog converters is limited to /2. This will

3) As it was mentioned in the last chapter, the expression for the third order distortion is equal to: Equation4-1

38

With

the output impedance equal to: Equation4-2 ) degredation. In and

Consequently, it can be seen that increase of the frequency will result in the other words, the requirement on the consequently on

will give us a requirement on the

. When the frequency increases, the required value of

will decrease and it

will be harder to achieve [7].

4.2

Different approaches for DACs interleaving

Interleaving of digital to analog converters is categorized in two different groups of hold interleaving and data interleaving, this gives us different approaches for interleaving the DACs. In the following section, each approach is described briefly.

4.2.1 Hold Interleaved DACs

The block diagram of hold interleaving DAC is shown in the figure 4-1. In the hold interleaved DACs, the same data is used for all sub DACs, each clocked at time shifted version of the sampling clock, meaning that each digital data is sampled by each phase of the sampling clock. It was shown in [13] that this technique will lead to cancelling and lowering the aliases of the DAC by choosing the phase shifts of the sampling clock for each DAC correctly. However, this approach does not give significant advantages for wide band applications.

39

1 a 2 b 3 c 4 d

DAC1 1
3

=
a 3

DAC2
b

2 1

2 3 4 2 1 2 3 4

+ DAC3
c

DAC4

Figure 4-1 Hold Interleaving DAC.

4.2.2 Data Interleaving DACs

Data interleaving approach is shown in the figure 4-2. This approach was developed to suppress the Nyquist images so that the produced frequencies near Nyquist could be used without stringent requirements on the filter [14]. This suppression is done by having the Nyquist images with 180 phase shift, and yet the fundamentals with the same phase. However, this approach requires the sampling rate of each DAC to be N .

40

1 a 2

= DAC1

/4

DAC2
1

3 2

2 3 4 2 1 2 3 4

b DAC3 c

DAC4 d

/4

Figure4-2 Data Interleaved DAC

4.2.3 Data and Hold Interleaving DACs

The block diagram of data and hold interleaving DACs are shown in the figure 4-3. In this approach each DAC is fed with the interleaved samples of the signal and each DAC samples at interleaved time instants. Consequently, the first N-1 image replicas and nonlinearity sours are cancelled, and the wide band operation will be achieved [9].

41

1 a 2 b 3 c 4 d

DAC1

= a

1 a 2 b + b

DAC1

DAC2

DAC2 + DAC3 c

DAC3 c DAC4 d

4 d

DAc4

3 2 1

2 3 4 2 1 2 3 4

Figure4-3 Data and Hold Interleaving [9]

4.3

The Interleaving and Return to Zero approach used in this project

The block diagram of both data and hold interleaving DAC used in this project is shown in the figure 4-4. As it can be seen from the figure, each DAC works at interleaved phases of the clock and holds its output for the entire period of the clock. Consequently, if we consider that the second DAC is working on the phase shifted clock of the first DAC, the frequency domain components of the first and second DAC can be written as the following equations with taking in to account the effect of Sinc function on the amplitudes [9]:

42

Equation 4-3

DAC(I):

Equation 4-4

DAC(II):

DAC (I)

Digital inputs

DAC (II)

Figure4-4 Interleaved DAC block diagram [9].

As it can be seen from the above formulas, the images of the two DACs have the same sign for even values of k, while having opposite signs for odd values. Consequently, the images with odd values of k cancel each other when the outputs of the two DACs are added, (the analog addition is done by return to zero technique). Therefore, the resulting spectrum will be like a single DAC running with twice sampling rate and it will be possible to generate output frequencies beyond the Nyquist frequency of the individual DACs. This is shown in figure 4-5. However, since the zero order hold function of each DAC is not changing with this technique and they will have a null at which is the new Nyquist frequency, the usable bandwidth will not improve as much. , the return to zero technique as an analog switch is used. With

In order to push this null to 2

return to zero technique, each DAC is only active for the half of the clock cycle, so the sinc function will have its null at 2 which is shown in the figure 4-6. Consequently, it can be

concluded that two interleaved DACs with return to zero technique is equivalent to a single DAC which is running with twice sampling rate [9] [21].
43

f (b)

(a)

f (c

Figure4-5 Image replicas of the first DAC (a), Image replicas of the second DAC (b) and Image replicas of the Interleaved DACs (c) [21].

However, it should be noted that in time interleaved digital to analog converters time alignment plays an important role. The cancellation of the images will not happen properly and unwanted spikes within the Nyquist band will occur if there will be any deviation from the ideal half sample time delay. Moreover, the two DACs must be balanced in terms of their amplitude. Correction algorithm for amplitude balance and time alignment might be applied to the system by the use of calibration filters if needed. The design of this filter is beyond the scope of this thesis, and aligned input clocks have applied to each block [9].

44

Figure 4-6 Return-to-Zero Effect[21]

45

Chapter 5 Designed Direct digital frequency synthesizer

5.1 System Overview

A four bit direct digital frequency synthesizer is designed in 65nm CMOS technology. In order to increase the bandwidth and sampling rate of the system interleaving with return to zero technique described in the previous chapter is used. Moreover, instead of the conventional digital thermometer decoder, a simple combination of a binary weighted DAC and a Flash ADC is used. This combination cuts the number of sine weighted current cells in half, with taking advantage of oversampling. Oversampling is known to put more requirements on the system and also using more power consumption. However, since the synthesized output frequency of the DDFS is restricted to be less than 3/8 of the sampling clock, due to limitations of the filter design in the real implementation [2], this drawback does not show a strong impact in our application. It also should be mentioned that the mismatch and dynamic nonlinearities of the binary weighted DAC such as glitches, will not affect the output spectrum of the synthesizer, since they will be tolerated by the comparators of the Flash ADC. However, the primarily purpose for choosing this architecture was to reach to a different contribution. The Block diagram of the designed DDFS is shown in the figure 5-1. The Phase Accumulator and the Complementor are behaviorally modeled in Verolg-A. The Verilog-A codes can be found in Appendix A. This system exploits the half wave symmetry of the sine wave by using the most significant bit of the phase accumulator; consequently, the sine weighted DAC only needs to produce the corresponding currents for the phases over the range of 0 to . When the most significant bit turns to 1, the complementor inverts its input digital bits, so that a decreasing ramp will be achieved. The output of the complementor will be the input to a binary weighted DAC. The binary weighted DAC produces the analog information of the phases of the sine wave. The analog phase information of the sine wave will be the input to a flash ADC, so that the thermometer representation of the phase information is achieved. The block diagram of a 2 bit flash ADC is shown in the figure 5-2. The Flash ADC is known to be used in applications with tens of GHz sampling rates since all the conversion is done in one clock cycle. The Flash ADC converts the analog input to a thermometer code. Usually the thermometer code is fed to a thermometer to binary decoder to be converted to a digital binary code, which is not the case in
46

our system. As for the N bit flash ADC

comparators are needed, usually their resolutions

are restricted to maximum 8 bits. The circuit shown in the figure 5-3 followed by buffer is used as the comparator of the ADC. The produced thermometer codes will then fed to a sine weighted DAC, and turns on the correspondent number of cells. The currents of these cells are added together and a sine wave is produced at the output.

MS B FCW Phase Accumulator Complementor Binary Weighted DAC Flash ADC Sine weighted DAC (thermometer) Filter

CLK

Figure 5-1The block diagram of the designed DDFS.

Vdd Vdd R R

R R

Figure 5-2 The Block Diagram of Flash ADC

Figure 5-3 The comparator of ADC

47

The reference voltages of the flash ADC is calculated according to the following formula [11]:

Equation 5-1 Equation 5-2

= =

Figure 5-4 shows the block diagram of sine-weighted DAC. The currents of the sine weighted DAC is calculated as:

Equation 5-3

] ]

48

Figure 5-4 The block diagram of sine weighted DAC.

The circuit of one current cell of the sine weighted DAC is shown in the figure 5-5. In order to achieve high spectral purity it is important that the output current of each of the current cells be as precise as possible. In order to decrease the impact of voltage variation of the drain-source of the current sources on the output current, long channel transistors have been used. Moreover, as for linear DAC, flip flops are used before the switches of the current cells, so that all the currents are switched to the output synchronized. The load resistor is selected 25, to avoid the problem of the headroom in the interleaved system.

49

Digital Circuits

Digital Circuits

M2 Biasing

Circuits
M1

Figure 5-5 The Current Cell of Current Steering DAC

Figure 5-6 shows the system level implementation using the interleaving approach. As it was discussed in more details in the previous chapter, when the output spectrum of two interleaved DACs are added with each other, the odd images and harmonics of the spectrums of each DAC cancel each other, consequently the resultant spectrum will be like the spectrum of one DAC with twice sampling rate and each DAC can produce output frequencies beyond their Nyquist frequency. However, as the zero order hold function of each DAC will not change with interleaving, to widening the bandwidth the return to zero should be used. With return to zero each DAC is only active for its half clock cycle, consequently, the null of the Sinc function will be pushed to the 2 (with the sampling rate of each DAC) from The return to zero can be

done by injecting zeros to the input of binary weighted DAC for each half clock cycle of the sampling frequency or by discharging the switch transistor of the current cells, which is shown in the figure 5-7.

50

1 3 5 7

1 3

5 7

RTZ Data FCW

DAC

Flash ADC

Sine DAC

Phase Accumulator

Complementor MUX
4 2 6

CLK

RTZ Data
1 3 5 7

DAC

Flash ADC

Sine DAC

4 6

2 4

Figure 5-6 The implemented System

51

Biasing Circuits

M3 M4

Biasing Circuits

CLKB

Digital Circuits

Digital Circuits

CLK

M5

M6

Biasing Circuits

M2

M1

Figure 5-7 Return to Zero, using discharge transistors

5.2

High Level Simulation Results

The architecture described in the previous section was first simulated behaviorally in Verilog-A, with Cadence Virtuoso design tool. The phase Accumulator was designed for 4 bits. With 3 bit flash ADC and sine weighted DAC and 4 GHz sampling clock frequency, the frequency resolution of in the Nyquist bandwidth is achieved. Equation 5-4 = 250 MHz

52

Figure 5-8 shows the triangle and sine waves generated with FCW=1. Figure 5-9, shows the output spectrum of the synthesized frequency for FCW= 7, resulting in 1.750 GHz output frequency. Equation 5-5 The image replica ( ) of Equation 5-6 The SFDR in the Nyquist-Band is equal to: Equation 5-7 75.3 (dB) - 9.25 (dB) = 66.05 (dB) = 4 GHz= 1.75 GHz

is shown in the spectrum. = = 4GHz- 1.75 GHz= 2.25 GHz

This design is followed by a simple low pass RC filter. Figure 5-10 shows the SFDR versus different control words .As it can be seen from this figure, the SFDR is highest for the low synthesized frequencies (73 dB) and decreases to (64 dB) for near Nyquist synthesized frequency.

Figure 5-8 The generated triangle and sine waves with FCW=1.

53

SFDR= 66 dB (1.75 GHz, -25.39) dB

2.25 GHz, -11.38 dB)

Figure5-9 The output spectrum of 1.75 GHz output frequency.

Figure5-10 The SFDR versus FCW

54

5.3

Transistor Level Simulation Results

The described system was designed and implemented in 65 nm CMOS technology, with 4 bit phase accumulator and 3 bit flash ADC and Sine Weighted DAC. The DDFS has been sampled with 3.2 GHz and 6.4 GHz clock frequencies. With 3.2 GHz the synthesizer was able to synthesize outputs in 8 levels with each level 200 MHz. Obviously, with 6.4 GHz sampling frequency the frequency resolution was 400 MHz. Figures 5-11 and 5-12 illustrates the generated sine-waveforms for FCW=2, with 3.2 GHz and 6.4 GHz sampling frequencies respectively.

Figure5-11 The sine wave generated with FCW=2,

MHz and 3.2 GHz sampling frequency.

55

Figure 5-12 The sine wave generated with FCW=2,

MHz and 6.4 GHz sampling frequency.

Figure 5-13 shows the output spectrum of DDFS with 400 MHz output frequency and 3.2 GHz clock frequency. In the output spectrum the worst case spurs in the Nyquist Bandwidth is the third harmonic. The DDFS showed the SFDR of 60 dB. The first image replica at 2.8 GHz is also shown in the figure.

Equation5-8 Equation 5-9 Equation 5-10 =

85.62(dB)- 25.39(dB)= 60.23 (dB) = 3.2 GHz= 400 MHz = 3.2GHz- 400 MHz= 2.8 GHz

56

(Synthesized Frequency: 400 MHz, -25.39 dB) SFDR=60dB B)

(Image Replica: 2.8 GHz, -56.03dBdB)

(Third Harmonic: 1.2 GHz, -85.62dB)

Figure 5-13 The output spectrum of DDFS

MHz output frequency with 3.2 GHz sampling frequency.

57

Figure 5-14 shows the output spectrum of DDFS with 800 MHz output frequency and 6.4 GHz clock frequency. In the output spectrum the worst case spurs in the Nyquist Bandwidth is the second harmonic. The DDFS showed the SFDR of 45 dB.

Equation 5-11 Equation 5-12

75(dB)- 30(dB)= 45 (dB) = 6.4 GHz= 800 MHz

(Synthesized Frequency: 800 MHz, -30.52dB) SFDR= 45(dB) (Second Harmonic: 1.6 GHz, -75 dB)

Figure 5-14 The spectrum of

MHz, with 6.4 GHz sampling frequency

58

Figure 5-15 shows the output spectrum of DDFS at Nyquist output frequency and 3.2 GHz clock frequency. The DDFS showed the SFDR of 58 dB.

(Synthesized Frequency: 1.6 GHz, -34.6 dB)

SFDR= 58(dB)

Figure 5-15 The output spectrum of DDFS at Nyquist frequency (1.6 GHz) with 3.2 GHz sampling frequency.

59

Figures 5-16 shows the output spectrum of Nyquist output frequency of 3.2 GHz with 6.4 GHz clock frequency. In this synthesized frequency, the DDFS shows the SFDR of 40 dB.

(Synthesized Frequency: 3.2 GHz, -39.36 dB) SFDR= 40(dB)

Figure 5-16 The Nyquist frequency output spectrum with 6.4 GHz sampling frequency.

As the phase accumulator is behaviorally modeled with Verilog-A, the power consumption of the system could not be measured precisely. However, the power consumption without the phase accumulator was 80 mW.

60

The simulation results of this work can be found in table 5-1.

Table 5-1 The simulation results of this work

Specification Technology Clock Frequency

This Work 65 nm CMOS 3.2 GHz 6.4 GHz

DAC Amplitude Resolution SFDR (Nyquist Frequency) =3.2 GHz =6.4 GHz SFDR ( SFDR ( =3.2 GHz, =6.4 GHz, = 400 MHz) = 800 MHz)

3 bits

58 dB 40 dB 60 dB 46 dB 1.2 V

Power Supply

61

Table 5-2 shows the published transistor level simulation results for DDFS in different technologies. As it can be seen, the best achieved SFDR is 44 dB with 4 GHz sampling frequency in 90nm CMOS technology.

Table 5-2 The simulation results of previous works

Specification Technology Maximum Clock Frequency DAC Amplitude Resolution SFDR(Nyquist Range) Power Consumption Power Efficiency Power Supply

[15] 350 nm CMOS 2 GHz

[16] 180 nm CMOS 1 GHz

[17] 90 nm CMOS 4 GHz

7 bits

8 bits

7 bits

35 dBc

20dB

44 dB

820 mW 0.41 W/GHz 1.8 V

271mW 0.271 W/GHz 3.3 V

462mW 0.116 W/GHz 1.2 / 2.8 V

62

Table 5-3 shows the published measurements results for DDFS in different technologies and with different architectures. The difference in the power consumption of the nonlinear DAC architecture and the architecture using TSC converter does worth the attention.

Table 5-3 The measurement results of previous works

Specification Technology Maximum Clock Frequency DAC Amplitude Resolution SFDR(Nyquist Range) Power Consumption Power Supply DDFS Architecture

[3] 350 SiGe BiCMOS 5 GHz

[2] 0.13 SiGe BiCMOS 8.6GHz

[18] 0.18 CMOS 1 GHz

8 bits

10 bits

8 its

45.7 dB

33 dB

44dB

460 mW 3.3 V TSC Converter

4.8W 3.3 V Nonlinear DAC

50 mW 1.8 V TSC Converter

63

Future Work In this project a 4 bit direct digital frequency synthesizer was designed in 65nm CMOS technology. Interleaving with return to zero has been used in order to increase the bandwidth and synthesized frequencies of the synthesizer. The designed synthesizer was simulated using Cadence design tool. With 3.2 GHz sampling rate, simulation results showed the SFDR of 60 dB for 400 MHz synthesized frequency. This SFDR decreased to 58 dB for Nyquist synthesized frequency. With 6.4 GHz sampling frequency the synthesizer showed the SFDR of 40 dB for 800 MHz and 3.2 GHz synthesized frequencies respectively. In order to make it possible to have better comparison with measurement results of the previous works provided in table 5-3, it is likely to increase the amplitude resolution of the nonlinear DAC to at least 7 or 8 bits and run the Monte Carlo simulations. Moreover, simulations should be run for taking in to account the process variations. As it was mentioned in the text, the phase accumulator and the complementor are behaviorally modeled in Verilog- A in this project. However, CMOS technology digital blocks also show limitations for working with high frequencies. In [17] CML logic blocks have been used to make the digital blocks run with 4 GHz sampling frequencies. However, CML logics increase the power consumption of the system. Therefore, for designing high sampling rate DDFS, limitations of the digital blocks should also be considered. Nonidealities of the time interleaved DACs, with the most important ones the gain mismatch and time mismatch between the channels is another important aspect to be considered in the proposed synthesizer. As it was stated in the text, any deviation from the ideal half sample time delay will result in imperfect cancellation of the images and spikes will be occurred in the output spectrum of DDFS. In our design ideal clocks have applied to the system with 30ps rise time and fall time. Correction algorithm for amplitude balance and time alignment might be applied to the system by the use of calibration filters if needed.

64

References [1]. Direct Digital Synthesizer, Theory, Design and Applications. Jouko Vankka / Nov 2000 [2]. An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-weighted DAC/ IEEE Journal of Solid-States Circuits/February 2010 [3]. A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35-um / IEEE Journal of Solid-States Circuits/September 2011 [4]. Design of Low-Power Rom-Less Direct digital Frequency synthesizer using nonlinear Digital-to-Analog Converter/ IEEE Journal of Solid-States Circuits/ October 1999 [5]. A technical tutorial on Digital Signal Synthesis/ Analog Devices/1999 [6]. Basic Principles of Digital-to-Analog Conversion / Behzad Razavi [7]. A 12 Bit GS/s DAC With IM3 < -60 dBc Beyond 1 GHz in 65nm CMOS / IEEE Journal of Solid-States Circuits/September 2009 [8]. A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero / IEEE Transactions on Circuits and Systems-II/January 2011 [9]. Systematic Analysis of Interleaved Digital-to-analog Converters/ IEEE Transactions on Circuits and Systems-II/December 2011 [10]. Analog Devices/ Analog Dialogue, Single Chip Direct Digital Synthesis vs. the Analog PLL by Jim Surber and Leo McHugh [11]. Direct Digital Frequency Synthesis by Analog Interpolation / IEEE Transactions on Circuits and Systems-II/ November 2006 [12]. Segmented SineWave Digital-to-Analog Converters for Frequency Synthesizer / IEEE ISCAS 2001

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[13]. On the attenuation of DAC aliases through multiphase clocking / IEEE Transactions on Circuits and Systems-II / March 2009 [14]. Parallel-path Digital-to-Analog Converters for Nyquist Signal Generation / IEEE Journal of Solid-States Circuits/ July 2004 [15]. 2 GHz 8-Bit CMOS Rom-Less Direct Digital Frequency synthesizer / IEEE Int. Symp. Circuits and Systems / 2005 [16]. A High-Speed Rom-Less Direct Digital Frequency Synthesizer realized by a Segmented Nonlinear-DAC / IEEE Region 10 Conference / 2007 [17]. A 4 GHz Direct Digital Frequency Synthesizer utilizing a nonlinear sine-weighted DAC in 90 nm CMOS / IEEE Asia Pacific Conference on Circuits and Systems [18]. A Low-Power Direct Digital Frequency Synthesizer Using an Analogue-Sine-Conversion Technique/ IEEE ISLPED /2011 [19]. A 10-bit 500-Msamples/s CMOS DAC in 65 nm/ IEEE Journal of Solid-States Circuits/September 1998 [20]. Current Steering Digital to Analog Converters: Functional Specifications, Digital Basics and Behavioral Modeling. [21].DAC Interleaving in Ultra-High-Speed Arbs http://www.evaluationengineering.com/articles/200912/dac-interleaving-in-ultra-high-speedarbs.php

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Appendix A
`include "constants.vams" `include "disciplines.vams" module digital_input_4(out0, out1, out2, out3, , cout, codeout, clk, enable,reset);

output out0; electrical out0; output out1; electrical out1; output out2; electrical out2; output out3; electrical out3; output cout; electrical cout; output codeout; electrical codeout; input clk; electrical clk; input enable; electrical enable; input reset; electrical reset; // parameter description parameter real millivolt = 0.001; parameter real vlogic_high= 1.2; parameter real vlogic_low= 0; parameter real vtrans_clk= 0.6; parameter real vtrans_reset= 0.6; parameter real vtrans_enable= 0.6; parameter real tdel= 0; parameter real trise= 1f; parameter real tfall= 1f; //local integer variables integer reset_flag; integer count; 68

integer code; integer d[0:4]; integer i; parameter integer step= 1; integer decrease; analog begin @ (initial_step) begin for (i=0; i<5; i=i+1)begin d[i]=0; end count=0; end if (V(reset) < vtrans_reset) begin reset_flag =1; count=0; end

@ (cross( V(clk) - vtrans_clk, +1)) begin

if (V(enable) > vtrans_enable) begin reset_flag=0; begin count=count+step; end code=count%16; if(code > (8 + decrease)) begin code = code - decrease; end for (i=4; i>=0;i=i-1) begin if (code>15) begin d[i]=1; code=code-16; end else begin d[i]=0; end 69

code= code*2; end

end end V(out0) <+transition (vlogic_high*d[0]*!reset_flag, tdel, trise,tfall); V(out1) <+transition (vlogic_high*d[1]*!reset_flag, tdel, trise, tfall);

V(out2) <+transition (vlogic_high*d[2]*!reset_flag, tdel, trise, tfall); V(out3) <+transition (vlogic_high*d[3]*!reset_flag, tdel, trise, tfall); V(cout) <+ transition (vlogic_high*d[0]*d[1]*d[2]*d[3], tdel, trise,tfall); V(codeout) <+ transition (millivolt*code); end endmodule Based on Verilog-A written for comparator in the vhdllib of cadence. include "constants.h" // sigin: (val,flow) // sigref: reference to which 'sigin' is compared (val,flow) // sigout: // // INSTANCE parameters // sigout_high = maximum output of the comparator (val) // sigout_low = minimum output of the comparator (val) // sigin_offset = subtracted from 'sigin' before comparason to sigref (val) // comp_slope = determines the sensitivity of the comparator [] comparator output (val,flow)

module comparator(sigin, sigref, sigout); input sigin, sigref; output sigout; electrical sigin, sigref, sigout; parameter real sigout_high = 1.2; parameter real sigout_low = 0; 70

parameter real sigin_offset = 0;

analog begin

@ ( initial_step ) begin if (sigout_high <= sigout_low) begin $display("Range specification error. sigout_high = (%E) less than sigout_low = (%E).\n", sigout_high, sigout_low ); $finish; end end

V(sigout) <+1.2 * (sigout_high - sigout_low) * tanh(comp_slope*(V(sigin, sigref)- sigin_offset)) + (sigout_high + sigout_low)/2; end endmodule

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