OFDM Reference design

Reference Design Structure

The design consists of the following components: MAC Application: top-level C code implementing a wireless MAC protocol. WARPMAC framework: Low-level PHY control and MAC primitives, implemented in C code OFDM PHY: FPGA implementation of the OFDM physical layer, built in System Generator Support Peripherals: Other peripheral cores in the FPGA (timer, radio bridges, etc.)

The OFDM Reference Design provides a foundation on which to build a wide variety of wireless research applications. The list below includes the applications we have developed and tested. We will expand this list as more applications are implemented. Wired-Wireless Bridge: implements a bridge between a WARP node's Ethernet interface and OFDM PHY. CSMA Link: implements a link between two WARP nodes using a carrier sensing multiple access (CSMA) MAC protocol. WARPnet Example: an example top-level application which works with the WARPnet Measurement Framework to run PER and BER tests.

OFDM Reference Design - Wireless/Wired Bridge

This simple application uses the OFDM Reference Design to build a wired-to-wireless bridge. It utilizes two WARP nodes, each connected via Ethernet to a separate PC. Every packet received on the WARP node's Ethernet interface is transmitted over the air. Every packet received over the air is copied to the node's Ethernet interface. This bridging "tricks" the two PCs into believing they are connected directly over Ethernet. In this application, the WARP nodes have no MAC or IP addresses. Both nodes run the same program. There is no medium access control protocol; every packet is transmitted wirelessly immediately, and no retransmissions or ACKs are generated.

Requirements
2 WARP SISO or MIMO kits 2 PCs with Ethernet interfaces

Setup
1. Connect each WARP node directly to the Ethernet interface of the PCs 2. Configure the PC Ethernet interfaces with IP address on the same subnet (10.0.0.1 and 10.0.0.2, for example) 3. Generate the FPGA configuration file for the design using the OFDM Reference Design project and the noMAC software project 4. Configure both WARP nodes using the same download.bit 5. When it's working, the PCs will be able to ping each other, stream video (using VLC, for example), or any other point-to-point network application

Benchmarks

Detailed benchmarks are available for the latest (v14) reference design's noMac implementation.

Code:

Code
The code for this application is provided in noMAC.c. The default OFDM Reference Design project includes noMAC as a software project.

xtending the OFDM Reference Design

The OFDM Reference Design is intended to serve as a starting point for wireless research projects. The design is open-source at all layers- the OFDM PHY, supporting peripherals, WARPMAC code and example application code. Any aspect of the design can be customized to build novel wireless applications. The Reference Design is distributed as a project for Xilinx Platform Studio. This XPS project integrates the hardware and software components of the design. You will need to be comfortable with XPS to customize this design. Our tutorials and workshop materials are a good starting point if you're new to XPS.

Building the XPS Project

In order to modify the XPS project, you will need to re-build the hardware design on your PC. Unfortunately, this is required even if you don't make any hardware changes (XPS is not very good about creating portable projects). After re-building the hardware, you can iterate on software changes quickly. The hardware build usually lasts around 60 minutes on a fast (2x3GHz) machine with lots (4GB) of RAM. It will take considerably longer on slow/low memory machines.

Linker Script
After building the project locally, you will need to generate a linker script for each software project you wish to use. In XPS, choose Software->Generate Linker Script. We recommend assigning your code and data sections to internal memory. This allows programming the node with just the download.bit file without using a bootloader. The heap and stack can safely be assigned to external memory. To use just the internal memory for code and data, make sure your script settings match those shown below. It is critical that no code sections be assigned to the memory block xps_bram_if_cntlr_2. This memory block is used for packet buffers. The PHY writes to this memory directly and will corrupt any code/data written there by software.

OFDM Reference Design - CSMA Link

This application uses the OFDM Reference Design to build a wired-to-wireless bridge implementing the CSMA MAC protocol for the over-the-air link. It utilizes two WARP nodes, each connected via Ethernet to a separate PC. Every packet received on the WARP node's Ethernet interface is transmitted over the air, addressed to the other WARP node. Every packet received over the air is copied to the node's Ethernet interface. This bridging "tricks" the two PCs into believing they are connected directly over Ethernet. This application implements the same basic function as the Bridge application, but uses a more sophisticated protocol for wireless medium access.

Requirements
2 WARP SISO or MIMO kits (analog board in slot 4 optional) 2 PCs with Ethernet interfaces

Setup
1. Set the DIP switches on the WARP nodes to 0 and 1 2. Connect each WARP node directly to the Ethernet interface of the PCs 3. Configure the PC Ethernet interfaces with IP address on the same subnet (10.0.0.1 and 10.0.0.2, for example) 4. Generate the FPGA configuration file for the design using the OFDM Reference Design project and the CSMAMAC source code 5. Configure both WARP nodes using the same download.bit 6. When it's working, the PCs will be able to ping each other, stream video (using VLC, for example), or any other point-to-point network application

Code
The code for this application is provided in csmaMac.c. The default OFDM Reference Design project includes CSMAMAC as a software project.

Protocol
This application uses our CSMA implementation. See the CSMAMAC page for a full description of the state machine and overview of the code.

Timing
The values below correspond to OFDM Reference Design v14

The basic packet exchange which defines the maximum throughput for CSMA is DATA-ACKDATA. The timing of this exchange in our implementation is illustrated below. Please note the figure is not drawn to scale.

This figure assumes the following parameters: SISO antenna configuration 2 OFDM symbols for channel training per packet 24 byte MAC header at QPSK (2 OFDM symbols) Full rate modulation of QPSK (12 bytes per OFDM symbol) or 16-QAM (24 bytes per OFDM symbol) 1484 byte payloads (1470 byte IP datagram + 14 byte Ethernet header) This figure includes a random backoff period imposed after a node receives an ACK. This period is designed to prevent two fully-backlogged nodes from simultaneously attempting to transmit a new packet immediately after the previous DATA-ACK exchange completes. The backoff imposes a wait of an integral number of slot durations (a slot is 22s in v14), with the slot count drawn randomly from [0,7]. Given this timing, the average minimum period for transmitting a new full-length DATA packet is 1263s (for QPSK full rate) or 775s (for 16-QAM full rate), implying a peak data throughput of 9.31Mbps for QPSK and 15.2Mbps for 16-QAM.

Benchmarks
Detailed benchmarks are available for the latest (v14) reference design's CSMA implementation.

OFDM Reference Design v15.0 (2010-Aug-11)

The code and models for this design correspond to svn rev 1580 for the FPGA v1 design and svn rev 1585 for the FPGA v2 design.

Note: The PHY is functionally identical for FPGA v1 and v2. The v2 design uses HDL for 10 multipliers (in the Tx scaling and Rx coarse CFO correction blocks) instead of DSP48's. The V2Pro version of the PHY uses too many multipliers for the V4FX100 FPGA, but the V4 FPGA has more than enough logic to realize the extra multiplications in fabric. Download the full XPS projects: Virtex-II Pro (WARP FPGA Board v1.2): OFDM_ReferenceDesign_FPGAv1_public_v15.0.zip (100MB) Virtex-4 (WARP FPGA Board v2.2): OFDM_ReferenceDesign_FPGAv2_public_v15.0.zip (100MB) Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386). Hardware Changes Rebuilt the Tx pilot insertion logic, to interleave pilots in time and space for Alamouti mode. Rebuilt the Rx phase estimation and tracking systems to improve phase error and CFO performance. Rebuilt the Rx correlator to improve packet detection performance, especially in Alamouti mode with two Tx antennas Fixed random payload generator (it previously results in invalid checksums) Added random payload capture logic, to write random payloads to a packet buffer for offloading via Ethernet for BER processing Built a real CRC-16 calculator for the header checksums (reduces chances of checksum collisions) Fixed bug in AGC core, which (very rarely) resulted in bogus DC offset correction values being applied for many packets in a row Upgraded to clock_board_config_v1_05_a, adding support for run-time selection of local or off board clock sources. Software Changes Added support for the WARPnet Measurement Framework, including a new top-level application (WARPNET_EXAMPLE). Updated warpphy/warpmac to reflect changes to registers in the PHY. Using the Design Same as v14.0 (see below).

OFDM Reference Design v14.1 (2010-Jan-08)

The code and models for this design correspond to svn rev 1400. This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386). Download the full XPS project: Virtex-II Pro (WARP FPGA Board v1.2): OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip (87 MB) Virtex-4 (WARP FPGA Board v2.2): OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip (87MB) Hardware Changes Updated the version of the Radio Bridge and Radio Controller cores to v1.22.a Added the MGT Protector core to the Virtex-4 design to make sure the MGT tiles are always powered on. This is a requirement of the Virtex-4 (see 'Designing with MGTs' in Virtex-4 User Guide). Software Changes No software changes Using the Design Same as v14.0. See below.

OFDM Reference Design v14.0

The code and models for this design correspond to svn rev 1400. This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386). Download the full XPS project: Virtex-II Pro (WARP FPGA Board v1.2): OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip (88 MB) Virtex-4 (WARP FPGA Board v2.2): OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip (89MB)

FPGA Board Version Notes The OFDM Reference Design uses very similar hardware designs for the two versions of the WARP FPGA Board (v1 and v2). The primary difference is the use of a soft Ethernet MAC in

the Virtex-II Pro FPGA and hard TEMAC in the Virtex-4. The custom WARP peripherals (OFDM transceiver, AGC, timer, radio controller, etc.) are identical in both projects. The software projects are also very similar across boards. The same source files are used for both versions. A few #ifdef statements are used in WARPMAC to include/exclude boardspecific code at compile time. The primary difference is support for user I/O. The project for the FPGA Board v1 uses an xps_gpio core as an interface to the LEDs, hex displays, buttons and switches. The FPGA Board v2 project uses the custom warp_v4_userio core and driver for the user I/O. WARPMAC provides a single API for user I/O, so MAC-level code can be fully portable between FPGA Board versions. Hardware Changes Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP). Software Changes Updated WARPMAC to use new Ethernet hardware Updated WARPMAC with new user I/O code for FPGA Board v2. One code file works for both versions, using just a few !#ifdef to compile the correct code. Using the Design The included download-csmamac.bit file implements CSMAMAC; download-nomac.bit implements NOMAC. Both are ready to download to WARP SISO or MIMO Kits. The included download-csmamac.ace or download-nomac.ace can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface. The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default: P/p : Increase/decrease the packet detection energy threshold by 100 D/d : Increase/decrease the packet detection required minimum energy duration by 1 C/c : Increase/decrease the carrier sensing energy threshold by 100 F/f : Increase/decrease the 2.4GHz center frequency by 1 channel S/s : Use SISO via the radio in slot 3/2 A : Use Alamouti 2x1 (2 transmit antennas, selection diversity between 2 receive antennas) 1/2/4/6 : Use BPSK/QPSK/16-QAM/64-QAM for the full-rate modulation scheme for all transmitted payloads You can add other commands to tweak your own parameters in uartRecv_callback function The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.

The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets.