slide 1 of 26

University of Toronto
D.A. Johns, K. Martin, 1997
Nyquist-Rate A/D Converters
David Johns and Ken Martin
University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)
slide 2 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
A/D Converter Basics
(1)
Range of valid input values produce the same output
signal quantization error.
A/D
V
in
V
ref
B
out
V
ref
b
1
2
1
b
2
2
2
b
N
2
N
+ + + ( ) V
in
x =
where
1
2
--- V
LSB
x
1
2
---V
LSB
< <
\ .
| |
01
00
10
11
0 1/2 1/4
V
LSB
V
ref
---------- 1/4 1 LSB = = B
out
V
in
V
ref
--------
3/4 1
slide 3 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Analog to Digital Converters
Low-to-Medium
Speed,
High Accuracy
Medium Speed,
Medium Accuracy
High Speed,
Low-to-Medium
Accuracy
Integrating Successive
approximation
Flash
Oversampling
(not Nyquist-rate)
Algorithmic Two-step
Interpolating
Folding
Pipelined
Time-interleaved
slide 4 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Integrating Converters
Low offset and gain errors for low-speed applications
Small amount of circuitry
Conversion speed is 2
N+1
times 1/T
clk
(Vin is held constant during conversion.)
Control
logic
Counter
b
1
b
2
b
3
b
N
Clock
f
clk
1
T
clk
----------- =
S
2
S
1 V
in

V
ref
S
1
S
2
\ .
| |
R
1
C
1
V
x
B
out
Comparator
slide 5 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Integrating Converters
Count at end of T
2
is digital output
Does not depend on RC time-constant
Time
V
x
T
1
Phase (I) Phase (II)
V
in1

V
in2

V
in3

T
2
(Three values for three inputs)
(Constant slope)
slide 6 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Integrating Converters
Notches the input frequencies which are multiples of 1/T
1
10
100
0
10
20
30
60
120
180 240 300
20 dB/decade slope
H f ( )
(dB)
Frequency (Hz)
(Log scale)
slide 7 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Successive-Approximation Converters
Sample
Start
Stop
No
Yes
No
Yes
b
i
1 = b
i
0 =
Signed input
V
in
V
D/A
>
V
in
V
D/A
, 0 i , 1 = =
V
D/A
V
D/A
V
ref
2
i 1 +
+ V
D/A
V
D/A
V
ref
2
i 1 +
( )
i i 1 +
i N
Makes use of binary search algorithm
/Requires N steps for N-bit converter
Successively tunes a signal until
within 1 LSB of input
Medium speed
Moderate accuracy
slide 8 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
DAC Based Successive-Approximation
Adjust until within 1 LSB of
Start with MSB and continue until LSB found
D/A mainly determines overall accuracy
Input S/H required
S/H
D/A converter
Successive-approximation register
(SAR) and control logic
b
1
b
2
b
N
B
out
V
D/A
V
in
V
ref
V
D/A
V
in
slide 9 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Charge Redistribution A/D
C C 2C 4C 8C 16C
1. Sample mode
C C 2C 4C 8C 16C
2. Hold mode
C C 2C 4C 8C 16C
3. Bit cycling
SAR
SAR
SAR
b
1
b
2
b
3
b
4
b
5
s
3
s
1
s
2
b
1
b
2
b
3
b
4
b
5
s
3
s
1
s
2
b
1
b
2
b
3
b
4
b
5
s
3
s
1
s
2
V
x
0
V
x
V
in
=
V
x
V
in

V
ref
2
----------- + =
V
in
V
ref
V
in
V
ref
V
in
V
ref
slide 10 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Charge Redistribution A/D
McCreary, 75
Combines S/H, D/A converter, and difference circuit
Sample mode: Caps charged to , compar reset.
Hold mode: Caps switched to gnd so
Bit cycling: Cap switched to . If cap left
connected to and bit=1. Otherwise, cap back to gnd
and bit=0. Repeat times
Cap bottom plates connected to side to minimize
parasitic capacitance at . Parasitic cap does not cause
conversion errors but it attenuates .
V
in
V
x
V
in
=
V
ref
V
x
0 <
V
ref
N
V
ref
V
x
V
x
slide 11 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Algorithmic (or Cyclic) A/D Converter
Sample V = V
in
, i = 1
Start
V > 0
V 2(V V
ref
/4) V 2(V + V
ref
/4)
i i + 1
i > N
Stop
No
Yes
No
Yes
b
i
1 = b
i
0 =
Signed input
Operates similar to successive-
approx converter
Successive-approx halves ref voltage
each cycle
Algorithmic doubles error each cycle
(leaving ref voltage unchanged)
slide 12 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Ratio-Independent Algorithmic Converter
McCharles, 77; Li, 84
Small amount of circuitry reuse cyclically in time
Requires a high-precision multiply by 2 gain stage
S/H
S/H X2
Cmp
Vref /4
Vref /4
Vin
Shift register
Out
Gain amp
slide 13 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Ratio-Independent Algorithmic Converter
Does not rely on cap matching
Sample input twice using C
1
; hold first charge in C
2
and

re-combine with first charge on C
1
Cmp
Verr
C1
Q1
C2
1. Sample remainder and cancel input-offset voltage.
Cmp
Verr
C1
Q1
C2
2. Transfer charge Q
1
from C
1
to C
2
.
Q1
Cmp
Verr
C1
Q2
C2
3. Sample input signal with C
1
again
Q1
Cmp
Verr
C1
Q1+Q2
C2
4. Combine Q
1
and Q
2
on C
1
, and connect C
1
to output.
Vout = 2 Verr
after storing charge Q
1
on C
2
.
slide 14 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Flash (or Parallel) Converters
Peetz, 86; Yoshii, 87; Hotta, 87; and Gendai, 91
V
ref
V
in
(2
N
1) to N
encoder
N digital
outputs
Over range
Comparators
R
R
R
R
R
R
R
V
r1
V
r2
V
r3
V
r4
V
r5
V
r6
V
r7
R
2
----
R 2
High-speed
Large size and power hungry
2
N
comparators
Speed bottleneck usually large cap
load at input
Thermometer code out of comps
Nands used for simpler decoding
and/or bubble error correction
Use comp offset cancellation
slide 15 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Issues in Designing Flash A/D Converters
Input Capacitive Loading use interpolating arch.
Resistor-String Bowing Due to I
in
of bipolar comps
force center tap (or more) to be correct.
Signal and/or Clock Delay Small arrival diff in clock
or input cause errors. (250MHz 8-bit A/D needs 5ps
matching for 1LSB) route clock and V
in
together with
the delays matched [Gendai, 1991]. Match capacitive
loads
Substrate and Power-Supply Noise and 8-
bit, 7.8 mV of noise causes 1 LSB error shield clocks
and use on-chip supply cap bypass
Flashback Glitch at input due to going from track to
latch mode use preamps in comparators and match
input impedances
V
ref
2 V =
slide 16 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Flash Converters Bubble Errors
Thermometer code should be 1111110000
Bubble error (noise, metastability) 1111110100
Usually occurs near transition point but can cause gross
errors depending on encoder
Can allow errors in lower 2 LSB but have MSBs encoder
look at every 4th comp [Gendai, 91]
(2N1) to N
encoder
N digital
outputs
V
in
V
ri

[Steyaert, 93]
slide 17 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Reduced Auto-Zeroing
Tsukamoto et al, ISSCC/96
Spalding et al, ISSCC/96
Reduce the auto-zero portion of conversion
auto zero when not performing conversion
add one more comparator and ripple up auto-zero
Advantages
Lower power less current drawn from ref string
More speed more time for conversion
Disadvantage
1/f noise not rejected as much
slide 18 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Two-Step A/D Converters
High-speed, medium accuracy (but 1 sample latency)
Less area and power than flash
Only 32 comparators in above 8-bit two-step
Gain amp likely sets speed limit
Without digital error correction, many blocks need at least
8-bit accuracy
4-bit
A/D
4-bit
D/A
16
First 4 bits
Vin
Gain amp
V
1
V
in
V
q
MSB
4-bit
A/D
LSB
Lower 4 bits
b
1
b
2
b
3
b
4
, , , ( ) b
5
b
6
b
7
b
8
, , , ( )
slide 19 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Digital Error Correction
Relaxes requirements on input A/D
Requires a 5-bit 2nd stage since V
q
increased
Example, see [Petschacher, 1990].
S/H1
4-bit
A/D
S/H2
4-bit
D/A
8 S/H3
Error
correction
D
8 bits
Digital delay
4 bits
5 bits
Vin
Gain amp
(4-bit accurate)
(8-bit accurate)
(5-bit accurate)
(5-bit accurate)
(8-bit accurate)
(8-bit accurate)
V
1
V
in
V
q
MSB
5-bit
A/D
LSB
slide 20 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Interpolating A/D Converters
V
ref
1 V =
V
in
R
R
R
R
0.75 V
0.5 V
0.25 V
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
latch
Digital
logic
b
1
b
2
b
3
b
4
(Overflow)
Input
amplifiers
Latch
comparators
V
1
V
2
V
3
V
4
V
2a
V
2b
R
R
R
R
R
R
R
R
V
2c
R
R
R
R
R
R
R
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Goodenough, 1989
Steyaert, 1993
Kusumoto, 1993
Use input amps to
amplify input around
reference voltages
Latch thresholds less
critical
Less cap on input (faster
than flash)
Match delays to latches
Often combined with
folding architecture
slide 21 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Interpolating Converters
V
in
1.0
(Volts)
(Volts)
0.75 0.5 0.25 0
0
5.0
Latch threshold
V
1
V
2
V
2a
V
2b
V
2c
9
I
1
I
2a
I
2b
I
2
9
3 3
3 3
3 3
(Relative width sizing shown)
(All lengths same)
current interpolation
slide 22 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Folding A/D Converters
Folding
block
Folding
block
2-bit
MSB A/D
converter
Latch
Latch
Latch
Latch
Digital
logic
V
in
b
1
b
2
b
3
b
4
V
1
V
2
V
3
V
4
V
in
V
1
V
in
V
2
V
in
V
3
V
in
V
4
Threshold
Threshold
Threshold
Threshold
Folding block responses
1
(Volts)
(Volts)
V
r
4
16
------
8
16
------
12
16
------
16
16
------ , , ,
)
`

=
V
r
3
16
------
7
16
------
11
16
------
15
16
------ , , ,
)
`

=
V
ref
1 V =
V
r
2
16
------
6
16
------
10
16
------
14
16
------ , , ,
)
`

=
V
r
1
16
------
5
16
------
9
16
------
13
16
------ , , ,
)
`

=
4
16
------
8
16
------
12
16
------
1 0
0
3
16
------
7
16
------
11
16
------
15
16
------
2
16
------
6
16
------
10
16
------
14
16
------
1
16
------
5
16
------
9
16
------
13
16
------
1
Folding
block
Folding
block
Reduce number of
latches using folding
Save power and area
Similar concept to 2-step
Folding rate of 4 shown
for 4 bit converter
slide 23 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Folding Circuit
I
b
I
b
I
b
I
b
V
in
V
out
R
1
R
1
V
r1
V
r2
V
r3
V
r4
V
in
V
out
V
CC
V
EE
V
CC
V
BE

V
CC
V
BE
I
b
R
1

V
r1
V
r2
V
r3
V
r4
(b)
(a)
Q
1 Q
2
V
a
V
b
slide 24 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Folding with Interpolation
Folding
block
Folding
block
2-bit
MSB A/D
converter
Latch
Latch
Latch
Latch
Digital
logic
V
in
b
1
b
2
b
3
b
4
V
1
V
2
V
3
V
4
V
in
V
1
V
in
V
2
V
in
V
3
V
in
V
4
Threshold
Threshold
Threshold
Threshold
Folding-block responses
1
(Volts)
(Volts)
V
r
3
16
----- -
7
16
------
11
16
------
15
16
------ , , ,
)
`

=
V
ref
1 V =
V
r
1
16
------
5
16
----- -
9
16
------
13
16
------ , , ,
)
`

=
4
16
------
8
16
------
12
16
------
1
0
0
3
16
------
7
16
------
11
16
------
15
16
------
2
16
------
6
16
------
10
16
------
14
16
------
1
16
------
5
16
------
9
16
------
13
16
------
R
R
V
4
V
4
V
4
R
R
Folding usually used
with interpolation
Reduces input cap (
Without interp, same
input cap as flash
[van Valburg, 1992]
[van de Grift, 1987]
[Colleran, 1993]
slide 25 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Pipelined A/D Converters
D
1
Q
1
D
N-2
Q
N-1
D
N
Q
N
D
1
Q
1
D
1
Q
1
D
N-2
Q
N-1
1-bit
DAPRX
1-bit
DAPRX
1-bit
DAPRX
1-bit
DAPRX
V
in
N

1
-
b
i
t

s
h
i
f
t

r
e
g
i
s
t
e
r
Analog pipeline
(DAPRX - digital approximator)
b
1
b
2
b
N
b
N 1
S/H
2
Cmp
V
ref/4
V
ref/4
V
i1
V
i
b
i
slide 26 of 26
University of Toronto
D.A. Johns, K. Martin, 1997
Time-Interleaved A/D Converters [Black, 80]
Use parallel A/Ds and multiplex them
Tone occurs at fs/N for N converters if mismatched
Input S/H critical, others not perhaps different tech for input S/H
S/H
S/H
S/H
S/H
S/H
N-bit A/D
N-bit A/D
N-bit A/D
N-bit A/D
Dig.
mux
Digital
output
f
2
f
3
f
4
f
1
f
0
V
in