Introduction to Xilinx System Generator Part I

Evan Everett and Michael Wu ELEC 433 - Spring 2013

Outline
Introduction System Fixed Fixed

to FPGAs and Xilinx System Generator

Generator basics point binary numbers point arithmetic times

Sample Tips

for building models

FPGA Basics: Architecture

FPGA Basics: Architecture

Slice Slice Slice Slice

Congurable Logic Blocks

Switch Matrix

Multiplier Block RAM

Digital Clock Manager

I/O Buffers

FPGA Basics: Architecture

Congurable Logic Block
Slice
LUT

Slice
MUX

Register

Switch Matrix

Slice Slice Slice

MUX

Register

LUT

Misc Logic

Lookup Tables (LUTs) implement any 4-input logic function

FPGA Basics: Glossary

LUT: lookup

table

MUX: multiplexer MULT: embedded Slice: atomic DSP

multiplier

logic block containing 4 LUTs and 8 ip ops

Slice: slice containing an adder, accumulator and multiplier logic block

CLB: congurable BRAM: block

random access memory

FPGA Basics: Resources

Example Resources for Xilinx Virtex family FPGAs
Device 18 Kb Slices DCMs Mults BRAMs 8 12 12 12 232 160 768 2,160 232 376 832 1,760 I/O 852 768 720 600

Virtex-2 Pro 23,316 XC2VP50 Virtex-4 42,176 XC4VFX100 Virtex-6 LX240T 37,680

Virtex-7 63,400 XC7VX415T

FPGA Basics: Resources

Example Resources for Xilinx Virtex family FPGAs
Device 18 Kb Slices DCMs Mults BRAMs 8 232 232 376 832 1,760 I/O 852 768 720 600

Virtex-2 Pro 23,316 XC2VP50

Virtex-4 42,176 12 160 XC4VFX100 v3 uses this chip Virtex-6 37,680 12 768 LX240T Virtex-7 63,400 XC7VX415T 12 2,160

How do we target these resources?

Hardware

description languages (HDL) like Verilog/VHDL allow designers to specify at a higher level than logic gates will use an even higher level tool called System Generator programming environment within Matlabs Simulink

We

Graphical

System Generator Basics

System

Generator provides two key tools for building your model generator: model ! HDL

Blocks

Hardware Simulink

provides a test environment for your design test vectors with MATLAB or Simulink blocks

Generate Visualize Leverage Simulation

and analyze output of design MATLAB expressions within design

and hardware will match bit true and cycle true

System Generator
MATLAB Simulink
fir(10,0.2) sin(0:1024./pi)

SysGen

Xilinx Blocks

VHDL

Generate

Bit T r

ue

System Generator Example

Simulink Blocks

Xilinx Blocks

Simulink Blocks

Simulink Xilinx

blocks are your signal sources and sinks

blocks are your to-be-synthesized FPGA design

System Generator Example

System Generator Blocks

These

will be realized in hardware

System Generator Example

System Generator Token

Congures

simulation & hardware parameters

Relates sample period to hardware clock Used to synthesize model Sets target FPGA device for model

System Generator Example

Simulink Blocks
Must

be outside System Generator gateways for data sources & analysis

Operate on oating point values Source: continuous-time oating point constant Sink: signal vs. time scope

Good

System Generator Example

Gateway Blocks
Convert Top-level Must

between oating and xed point values ports in HDL model

set precision & sample rate in Gateway In

System Generator Basics

Every

model needs a System Generator token start and end with Gateway blocks : double to xed point conversion : xed point to double conversion
System Generator

Models Any

Simulink blocks can be used outside gateways for data sources and output analysis

Good Only

Xilinx blocks can be used inside gateways treats gateways as top-level ports

Synthesis