VLSI Technology (Oxidation)

OXIDATION The oxidation of silicon is necessary throughout the modern integrated circuits fabrication process. The SiO2 layer has several uses as given below:(i) To serve mask against implant or diffusion of dopants into silicon (ii) To provide surface passivation (iii) To isolate one device from another (iv) To acts as component in MOS structure (v) To provide electrical isolation of multilevel metallization process There are several techniques used for the formation of oxide layer such as thermal oxidation, wet anodization, vapor-phase technique and plasma anodization. The choice of oxidation technique depends on our purpose. When the interface between the oxide and silicon requires low-charge density thermal oxidation has been the preferred technique. Growth Mechanism of Oxide Layer Since a silicon surface has a high affinity for oxygen, an oxide layer rapidly forms when silicon is exposed to an oxidizing ambient. The chemical reaction which takes place during thermal oxidation of silicon in oxygen or water vapor is given by the below equation 1 and 2 respectively. Si (solid) + O2 SiO2 (solid) (1) Si (solid) + 2H2O SiO2 (solid) (2) The mechanism of growth of oxide layer on the surface of silicon involves the sharing of valence electrons between the silicon and oxygen; the silicon oxygen bond structure is covalent. During the course of oxidation process, the Si-SiO2 interface moves into the silicon. Its volume expands, however so that the external SiO2 surface is not coplanar with the original silicon surface. Based on the densities and molecular weights of Si and SiO2, we can show that for growth of an oxide of thickness d a layer of silicon with a thickness of 0.44d is consumed.

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VLSI Technology (Oxidation)

Oxidation Kinetics The kinetics of silicon oxidation is described by the Deal and Groves model. This model is valid for the temperatures between 700 to 1300oC, partial pressures between 0.2 to 1.0 atm (perhaps higher) and oxide thickness between 300 to 20,000 Ao for water and oxygen ambient. The below figure shows the silicon substrate covered by an oxide layer that is in contact with the gas phase.

Figure: Basic model for thermal oxidation Here, three processes undergo and they are as follows:(1) The oxidizing species are transported from the bulk of the gas phase to gas-oxide interface with flux F1. (2) The oxidizing species are transported across the existing oxide toward the silicon with flux F2. (3) The oxidizing species react at the Si-SiO2 interface with the silicon with flux F3. For steady state F1=F2=F3 The gas phase F1 can be linearly approximated by assuming that the flux of oxidant from the bulk of the gas phase to the gas-oxide interface is proportional to the difference between the oxidant concentrations in the bulk of gas CG and the oxidant concentration adjacent to the oxide surface CS. F1 = hG (CG CS) ---------------- (1) Where hG = gas phase mass transfer coefficient. To relate the equilibrium oxidizing species concentration in the oxide to that in the gas phase, we invoke Henrys law C0 = HS and C* = HG Where C0 = equilibrium concentration in the oxide at the outer surface C* = equilibrium bulk concentration in the oxide S = partial pressure in the gas adjacent to the oxide surface
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VLSI Technology (Oxidation)

G = partial pressure in the bulk of gas H = Henrys constant Using Henrys law along with the ideal gas law equation (1) can be written as F1 = h (C* - C0) Where h= hG/HKT is the gas phase mass transfer coefficient. (Note: Henrys law is valid only in the absence of dissociation effects at the gas -oxide interface. This implies that the species moving through oxide is molecular) The flux of this oxidizing species across the oxide follows the Ficks law at any point d in the oxide layer. Following the steady state assumption, F2 must be the same at any point within oxide, resulting in F2 = D (C0 - Ci)/d0 --------------------(2) Where, D = diffusion coefficient Ci = oxidizing species conc. In the oxide adjacent to the oxide-silicon interface d0 = thickness of oxide The flux at the Si-SiO2 interface is given by F3 = ksCi --------- (3) Where ks is the rate constant of chemical surface reaction Using steady state condition i.e. F1=F2=F3, the equation can be solved simultaneously to obtain expressions for Ci and C0. There are two limiting cases arises during oxidation depending upon diffusivity. Case 1: When diffusivity is very small, Ci-0 and C0 - C*. It is called as diffusion controlled case. In this the rate of oxidation depends on supply of the oxidant to the surface. Case2: When diffusivity is very large, Ci = C0. It is called reaction-controlled case because an abundant supply of oxidant is provided at the Si-SiO2 interface. The oxidation rate is controlled by the reaction rate constants ks and Ci. To calculate the rate of oxide growth rate, we define N1as the number of oxidant molecules incorporated into a unit volume of the oxide layer. Assuming that the oxide has 2.2 X 1022 SiO2 molecules/cm3 and one O2 molecule is incorporated into each SiO2 molecule. So, N1 = 2.2 X 1022 cm-3 for dry oxygen. Considering the presence of oxide initially from a previous step that is d0 = di at t = 0 the following equation is generated. d20 + Ad0 = B (t + ) ----(3) where A = 2D [1/ks + 1/h] ----(4) B = 2DC*/N1 ------ (5) = d2i + Adi/ B --- (6) Here, represents a shift in time co-ordinate to account for the presence of the initial oxide layer di. On solving equation (3) for d0 we get
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VLSI Technology (Oxidation)

d0/(A/2) = [1 + (t + )/(A2/4B)]1/2 1 ---- (7) equation (7) gives results for two limiting cases ----1. For long oxidation times, when t >> and t >> A2/4B d20 = Bt ---------- (8) where B is parabolic rate constant. Equation (8) is known as parabolic law and process is said to be diffusion controlled. 2. For short oxidation times when (t + ) << A2/4B d0 = B (t + )/A ------------ (9) where B/A = linear rate constant equation (9) is known as linear law and process is said to be reaction controlled.

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VLSI Technology (Oxidation)

High Pressure Oxidation
Oxidation in high pressure steam produces a substantial acceleration in the growth rate. High pressure oxidation of silicon is practically attractive because the thermal oxide layers can grow at relatively low temperatures in run times comparable to typical high-temperature and 1 atm conditions. Low temperature operating conditions also minimize the lateral diffusion, which is of great importance as device dimensions get smaller. Another advantage is that oxidationinduced defects are suppressed. For high temperature high pressure oxidation the oxidation time is significantly reduced. The high pressure oxidation technique has been used mostly in bipolar applications, although some companies have applied it to MOS products. Below figure shows the oxide thickness versus time data for steam oxidation at various pressures and 9000C. The substantial acceleration in the oxidation rate caused by the increased pressure is apparent.

Fig: Oxidation thickness versus oxidation time for pyrogenic steam at 9000C

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VLSI Technology (Oxidation)

The data shown above is analyzed using linear parabolic model. Linear pressure dependence was observed for both linear and parabolic rate constants. From the kinetics of oxidation we find that the parabolic rate is given by B = 2DC*/N1 which shows that B is directly proportional to C*, which in turn proportional to the partial pressure of oxidizing species in the gas phase. Oxidation in high pressure steam produces a substantial acceleration in the growth rate. A similar kinetics study for dry high-pressure oxide has been reported. Oxide thickness versus oxidation time for various pressures and 9000 C is shown below.

Fig: Oxidation thickness versus oxidation time for Dry O2 at 9000C As in the case of high-pressure steam oxidation a change in activation energy at 9000 C was observed. For thin pressure oxide, temperatures of 700 to 8000 C, pressure of 10-20 atm and short oxidation times are necessary. In analyzing kinetics of oxidation at elevated pressure several complications arise:(i) Continuous variation in pressure during pressurization (ii) Slightly variable pressurization times (iii) Small temperature variations that occur during pressurization and during the early part of the oxidation at full pressure.
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VLSI Technology (Oxidation)

(iv) (v) Varying partial pressure of steam during depressurization Thickness variations from run to run and across wafer.

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VLSI Technology (Oxidation)

Plasma Oxidation
The plasma oxidation process offers the possibility of growing high-quality oxides at temperatures even lower than those achieved with the high-pressure technique. This process has all the advantages associated with low-temperature processing such as minimized movement of previous diffusions and suppression of defect formation. Anodic plasma oxidation can grow reasonably thick oxides (on the order of 1m) at low temperature (<6000C) at growth rate up to about 1 m/h. Plasma oxidation is low-temperature vaccum process, usually carried out in a pure oxygen discharge. The plasma is produced either by a high-frequency discharge or DC electron source. Placing the wafer in a uniform density region of the plasma and biasing it positively below the plasma potential allows it to collect active charged oxygen species. The growth rate of oxide typically increases with increasing substrate temperature, plasma density and substrate dopant concentration. The mechanism involved with plasma oxidation is not fully understood. Uncertainty exists as to whether the oxide grows by the inward migration of oxygen species or by other more complicated mechanisms. The quality of oxide grown by this process can be good as that of thermally grown silicon dioxide.

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VLSI Technology (Oxidation)

Oxide Properties
1. Masking Property: A predeposition of dopant by ion implantation, chemical diffusion or spin-on techniques typically results in a dopant source at or near the surface of the oxide. A SiO2 layer can provide a selective mask against the diffusion of dopant atoms at elevated temperatures. At high temperatures, diffusion in the oxide must be slow enough with respect to diffusion in the silicon that the dopants do not diffuse through the oxide in the masked region and reach the silicon surface. The oxide thickness used for masking common impurities in conventional device processing is 0.5 to 0.7 m thick. The impurity masking properties result when the oxide is partially converted into silica impurity oxide glass phase and prevents the impurities from reaching the SiO2-Si interface. The values of diffusion constants for various dopants in SiO2 depend on the concentration, properties and structures of the SiO2. 2. Oxide Charges: The Si-SiO2 interface contains a transition region. Various charges and traps are associated with the thermally oxidized silicon, some of which are related to the transition region. A charge at the interface can induce a charge of the opposite polarity in the underlying silicon, thereby affecting the ideal characteristics of the MOS device. The below figure shows general types of charges.

Qit (Interface-trapped Charges): Located at the Si-SiO2 interface, Qit have energy states in the silicon-forbidden bandgap and can interact electrically with the underlying silicon.
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VLSI Technology (Oxidation)

These charges are thought to result from several sources, including structural defects related to the oxidation process, metallic impurities, or bond-breaking process. To neutralize these charges a low-temperature hydrogen anneal (450oC) is used. Qf (Fixed Oxide charges): Located in the oxide within approximately 30oA of the SiSiO2 interface. Qf cannot be charged or discharged. Its density ranges from 1010/cm2 to 1012/cm2, depending on oxidation and annealing conditions as well as orientation. Qf is related to the oxidation process itself. The value of this charge can be determined using the following equation: Qf/q = (-VFB + MS)C0/q = (-VFB + MS )s/qd0 Where VFB is flat band voltage, MS is metal semiconductor work function difference, d0 is oxide thickness, C0 is oxide capacitance and s is dielectric permittivity. Qf values for <100> oriented silicon are less than those for <111>silicon. Qm (Mobile ionic charges): These charges are generated because of alkali ions such as sodium, potassium and lithium in the oxide as well as to negative ions and heavy metals. Densities of these charges are range from 1010/cm2 to 1012/cm2 or higher and are related to processing materials, chemicals, ambient, or handling. Since alkali ions can be present at various places in the oxide, the MOS capacitor is subjected to a temperature-bias stress effect which is compared to the standard C-V plot. Common techniques used to minimize this charge include cleaning the furnace tube in chlorine ambient, getting with phosphosilicate glass and using masking layers such as silicon nitride. Qot (Oxide trapped charges): These charges may be positive or negative, due to holes or electrons trapped in the bulk of the oxide. This charge, associated with defects in the SiO2, may result from ionizing radiation, avalanche injection or high currents in the oxide. It can be annealed out by low-temperature treatment. Densities ranges from 109/cm2 to 1013/cm2. 3. Oxide Stress High stress on the film can contribute to wafer warpage, film cracking and defect formation in the underlying silicon. Room temperature measurements following thermal oxidation of silicon show SiO2 to be in a state of compression on the surface. Stress values of 3 X 109 dyn/cm2 are reported, with the stress attributed to the differences in thermal expansion of Si and SiO2. Viscous (shear) flow of thermally grown SiO2 occurs at temperatures as low as 9600C, evidenced by the inability of the oxide-silicon structure to remain thermally warped above that temperature. During device processing, windows are cut into the oxide, resulting in a complex stress distribution. Exceedingly high stress levels can occur at these discontinuities. Such
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VLSI Technology (Oxidation)

stress would typically be relieved by plastic flow or other stress-relief mechanisms. The stress reduction is further accomplished by shear components which average the load over adjacent areas.

Oxidation Induced Defects

There are mainly two types of defects arises due to oxidation which is given below: 1. Oxidation-induced stacking faults: Thermal oxidation of silicon can produce stacking faults lying on <111> plane. These planar faults are structural defects in the silicon lattice that extrinsic in nature and are bounded by partial dislocations. The growth mechanism may involve the coalescence of excess silicon atoms in the silicon on nucleation sites, such as defects grown in during crystal growth. As a result of the oxidation process, excess interstitial silicon is present near the Si-SiO2 interface. A small fraction these silicon atoms flow into the bulk silicon. The silicon interstitial super-saturation in the silicon determines the stacking fault growth. Because of stacking faults in the silicon many problems arises into the device made up of it. Examples include degraded junction characteristics in the form of increased reverse leakage current and storage time degradation in MOS structures. These problems arise when stacking faults are electrically active as the result of being decorated with impurities. The decoration occurs both in the stacking fault itself and on the bounded dislocations. The growth of oxidation induced stacking faults is a strong function of substrate orientation, conductivity type, and defect nuclei present. Observations shows that the growth rate is greater for <100> than <111> substrates. The below figure shows growth of oxidation-induced stacking faults with respect to temperature for 3hr of dry oxidation.

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VLSI Technology (Oxidation)

The above figure has two regions: (a) Growth region (b) Retrogrowth region In the retrogrowth region, stacking faults formation is suppressed while preexisting stacking faults shrink. The addition of HCl to the ambient can also suppress stacking fault formation. The activation energy in the growth region is 2.3 eV independent of surface orientation and ambient (dry or wet). Shorter length stacking faults are usually bulk-nucleated stacking faults intersecting the surface. The length-to-depth ratio of the surface-oxidation stacking fault is approximately 3 to 10.

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VLSI Technology (Oxidation)

For comparable oxide thickness shorter stacking faults are grown when the oxidation temperature is lower. For oxides as thick as 1m, stacking fault formation is completely suppressed when temperature is reduced below 950oC. Shrinkage of preexisting stacking fault can also be accomplished by high-temperature inert ambient treatment, for example N2 with activation energy of 2.3 eV. Experimental observations shows that at comparable temperature and time, the oxidation stacking fault is greater for steam ambient than for dry ambient. This suggests that oxidation rate strongly influences the point-defect mechanism responsible for stacking fault growth. The below equation is proposed model in which the oxidation rate is controlling parameter in oxidation stacking fault length. dl/dt = K1[dTox/dt]n K2 where l = stacking fault length Tox = oxide thickness t = time n = power dependence K1 = related to growth mechanism and defect generation at Si-SiO2 interface. K2 = related to retrogrowth mechanism 2. Selective oxidation of silicon represents an important part of IC processing. Oxide isolation is preferred to junction isolation. Stress along the edge of an oxidized area, especially in recessed oxides (i.e. where the silicon has been trenched prior to oxidation to produce a reasonably planar surface), may produce severe damage in the silicon. Such defects results in increased leakage in nearby devices. The stress generated by the growing oxide, whose volume is over twice that of the consumed silicon, must be relieved without damaging the silicon. Various parameters have been examined for recessed isolation process, with the conclusion that the oxidation temperature must be sufficiently high to allow the stress in the oxide to be relieved by viscous flow. High temperature ( 950oC) will prevent stress induced defect formation in recessed structure.

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