Materials innovations are driving device performance

Paul R. Besser, Fellow

Solid State Technology Webcast December, 2013

Agenda

1 2 3

The need for materials innovation Examples of materials innovations Challenges with new materials

A collaborative approach

Paul Besser, SST Webcast 2013

Agenda

1 2 3

The need for materials innovation Examples of materials innovations Challenges with new materials

A collaborative approach

Paul Besser, SST Webcast 2013

Market needs drive new requirements:

Performance, Power, Cost (PPC)
Higher data rates, longer battery life High resolution screens

Communication

Computing

Consumer

The Convergence is Here

Multicore processors Thinner form factors

Navigation

Imaging

Video

Power

Performance*

Cost/Area

A4

A5

A6

A7
4

Paul Besser, SST Webcast 2013

The impact of scaling

Paul Besser, SST Webcast 2013

Driving the leading-edge process roadmap

Production
* In collaboration with ST

Development

Path-Finding
6

Paul Besser, SST Webcast 2013

Agenda

1 2 3

The need for materials innovation Examples of materials innovations Challenges with new materials

A collaborative approach

Paul Besser, SST Webcast 2013

Innovations in silicon manufacturing

new materials enable innovation
11 Elements

+4 Elements +45 Elements (Potential)

Paul Besser, SST Webcast 2013

Innovations are driven in three areas

Improving Device Performance

Scaling Dimensions

Evolving Connectivity

Economics and Environmental Friendliness Collaboration is Essential to Success

Paul Besser, SST Webcast 2013

Improving performance is about shrinking and expanding

Improving performance (data access speed, battery

life, etc) is much more than just shrinking the dimensions of the processor.
Novel materials innovations = device performance

MIM CAP II TSVs MIM CAP AIR GAP Porous LK Cu Alloys Sel Metal caps Porous LK New Cu BM Cu Alloys Eless Cu MIS Dual Si2 Fin FET Multiple EWF Si-50%Ge Ge MOS SiGe channel Si-P

improvements

BEOL

Low-K ESL Ultra Low-K ULK Cap CPI FTEOS ILD Al Wires TiSi2 Bulk Si CVD W MOCVD TiN CoSI2 FTEOS ILD Cu Barriers Cu wiring SOI ILD Cu caps ALD W NiPtSi Si Strain Low K ILD CoWP cap Stress Liner Si-Ge Eless Cu High K Metal Gate Gate First Si orientation

Eless Cu Cu Contact Dual Si2 ALD Metals Replacement Metal Gate Stress Liner Si-C

Contacts

Device

Channel

350

250

180/130

90

65 /45

45/32

28/20

14/beyond
10

Technology Node (nm)

Paul Besser, Semicon West 2013
Paul Besser, SST Webcast 2013

Device Options: Planar and FinFET

FinFET uses vertical surfaces for channels, forming a double gate

Planar (on SOI)

drain gate source STI

FinFET (on SOI)

drain

SOI SiO2 (BOX)

substrate substrate

Fin SiO2
source

Paul Besser, Semicon West 2013

Slide courtesy of Witek Maszara

11

Device performance: planar to FinFET

Density Scaling Gate Pitch Scaling Contact Width Scaling Contact Resistance Increase
(Active power needs to increase)

Gate Length Scaling

Ioff Increase
(Stand-by power increase)

FinFETs

Slide courtesy of Witek Maszara

12

Source-Drain engineering: stress

Selective epi of SiGe replacing Si fin in S/D area adds stress to

PMOS FinFET channel.

Stress benefit saturates for fin recess ~20nm below STI surface
3D modeling

S/D Epi

Fin Height=30nm Fin width=14nm

Fin

Slide courtesy of Witek Maszara

13

Migration from planar to FinFETs was enabled with novel materials

In the last few years, the transistor migrated from SOI + Gate First

metal gate to FinFET + RMG, for improved performance.

While both integrations utilize NiPtSi, CVD TiN,

ALD HK, and W contacts, additional novel materials innovations enable this transition.

2011
High K Metal Gate Gate First CVD W NiPtSi CVD TiN

ALD Metals High K Replacement Metal Gate FinFET Si-Ge SiGe Channel CVD W NiPtSi CVD TiN

2013

Paul Besser, Semicon West 2013

Paul Besser, SST Webcast 2013

14

Development of a manufacturable process requires a fundamental understanding of technology interactions

Example = BEOL
Metal/via patterning and etch: straight and smooth sidewalls tapered line and via profile residuals at via bottom Metallization challenges: Cu barriers must be thin, continuous, low resistivity ALD barriers reduce line resistance Void-less Cu fill Pre-clean prior to barrier metal deposition Cu grain size and texture control Dielectric challenges: Lower k dielectrics: poorer mechanical stability moisture sensitive Topography and planarity from CMP Cap layer deposition process and material type Reliability: BTS, TDDB, EM, SM
Paul Besser, SST Webcast 2013 15

Agenda

1 2 3

The need for materials innovation Examples of materials innovations Challenges with new materials

A collaborative approach

Paul Besser, SST Webcast 2013

16

Are materials changes easy?

Historically, materials changes have been challenging. Examples:
While there have been many selective deposition processes

researched, only 3 selective processes have made it into volume manufacturing: salicides, selective epi Si-Ge, and CoWP metal caps
Case study1 : SiLK SiLK is a low-K polymeric insulator which was investigated as a low-K dielectric for microprocessors. Spin-on dielectrics are challenged by thermal expansion issues, stressmigration and other reliability issues In the end, SiLK was dropped. Case study 2: NiSi (next slide) NiSi was under development by for >4 years before NiPtSi was HVM.

Paul Besser, Semicon West 2013

Paul Besser, SST Webcast 2013

17

Example: challenges with material changes

NiSi was in development by for >4 years before NiPtSi was inserted into HVM
NiSi advantages: Lower Rs, lower thermal budget, formation on Si-Ge, linewidth independent NiSi challenges: Fast diffusion and NiSi2 is stable phase (and will form!)

Pt additions increase silicide Rs, but also limit metal rich phases, alter silicide texture,

retard NiSi2 formation, and delay agglomeration

S. Thompson et al., IEEE IEDM, 3.2.1 (2002)

250

Ni-Si
Resistance (arb. units)
200
Metal Rich Phases

150 100

NiSi

NiSi2

CoSi Co2Si

J. Patton et al, ISSM (2004)

CoSi2

50

Co-Si
0 100 200 300 400 500 600
o Temperature ( C)

700

800

900

Nickel Silicide Technology, C. Lavoie, C. Detravenier and P.R. Besser, in Silicide Technology for Integrated Circuits (2005)
Paul Besser, SST Webcast 2013 18

Diffracted Angle (2q)

Agenda

1 2 3

The need for materials innovation Examples of materials innovations Challenges with new materials

A collaborative approach

Paul Besser, SST Webcast 2013

19

Materials innovations require early collaboration between tool suppliers, materials suppliers, and GLOBALFOUNDRIES
Research Development Materials Supply (substrates, resists, gases, abatement, slurry, targets, precursors, chemicals, and packaging matls) Unit process Integration HVM tooling (Chambers, Platforms, Productivity) Electrical testing, Yield HVM
Paul Besser, SST Webcast 2013 20

Engaging early, deeply, openly, and comprehensively

Collaborative Innovation Tapping global talent Jointly develop new technologies and manufacturing solutions Focused on shared success Time to Everything!

Summary
Materials innovations drive

performance improvements in the microelectronics industry, creating faster and smaller devices that use less energy and are more reliable.
Materials innovations present

cost

value

technological and economical challenges.

Leading-edge nodes are seeing an

explosion of new materials.

Only collaboration can these materials

innovations which drive performance and reliability be introduced seamlessly at an affordable cost and on time.

Paul Besser, SST Webcast 2013

21

Thank you

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