Reg. No.

Question Paper Code :

31212

Common to M.E. Applied Electronics/M.E. Computer and Communication/ M.E. VLSI Design Elective

252079 ASIC DESIGN (Regulation 2010) Time : Three hours

40

Answer ALL questions.

1.

What are the rules to be followed to find equivalent resistance of MOS transistors connected in series/parallel?

2. 3. 4. 5. 6. 7. 8. 9.

Enlist any four essential characteristics of FPGA of reconfigurable gate arrays. List different types of antifuses used in FPGAs. Differentiate DC & AC input cells in programmable ASIC. List few files created in the synthesis process of ACTEL device. What are the features of EDIF? What are the data formats supported in verilog? What are the types of simulation? Distinguish between Global and Detailed routing.

84

01 8

10.

What is the need for DRC in ASIC design?

40

18

PART A (10 2 = 20 marks)

18

M.E./M.Tech. DEGREE EXAMINATION, JUNE 2011.

40
Maximum : 100 marks

PART B (5 16 = 80 marks) 11. (a) (i) (ii)

Design a CMOS combinational cell to implement the function AOI (2, 11). (8) Find the logic area of the cell OAI (22) with a logic ratio of 3. Or (8)

(b)

(i)

Design CMOS logic gates for the following functions (1) (2)
Y = (A + B + C ) + D
Y = A + CD + B .

18

(ii)

Implement two input XOR cell using two input multiplexer.

40

12.

(a)

(i) (ii)

Write short notes FAMOS.

40
Or Or 2

(iii) A 32 bit off-chip bus operating at 5 V and 66 MHz clock rate is driving a capacitance of 25 pf/bit. Each bit is estimated to have a toggling probability of 0.25 at each clock cycle. Determine the power dissipation. (4) (12) (4)

(b)

(i) (ii)

Implement the function Y = AB + CD + B + C using Actel 2 logic cell. (10) With a neat circuit diagram explain the Xilinx Xc 4000 I/O block. (6)

13.

(a)

(i) (ii)

40

Briefly explain about half-gate ASIC synthesis in Xilinx. Write a technical note on PLA tools.

18

What are the different types of ASIC I/O cells?

01 8

(b)

Explain in detail the following : (i) Actel Act Interconnect Architecture Derive Elmores delay for the given RC circuit at node 5. (8 + 8)

(ii)

84

1
(4) + (4) (4) (10) (6)

31212

14.

(a)

Explain the following in VHDL logic synthesis. (i) (ii) Initialization and reset Combinational logic synthesis

40

(iii) Memory synthesis in VHDL and Verilog. Or (b) (i) (ii)

Discuss the procedure for path oriented decision making (PODEM) algorithm. (8) Find the test vector detecting the fault at pin 6 stuck-at-D in the following circuit. (8)

15.

(a)

Write short notes on : (i) (ii) Clock routing

Left-Edge algorithm.

18
Or 3

40
(8) + (8) (b) Briefly explain iterative partitioning improvement using Kernighan-lin algorithm.

84

01 8

40

18

(4) (6) (6)

31212