UNIVERSITY OF CALIFORNIADAVIS DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING EEC180ADIGITAL SYSTEMS I

FALL 2010

EXAM II

STUDENT INFORMATION
Name ID Number

INSTRUCTIONS
The exam is closed book and notes. A single double-sided cheat sheet is allowed. Print your name and your ID number. There are four problems in the exam. Solve all of them and show your work. If you need more space for your solution, use the back of the sheets.

EXAM GRADE
Problem 1 2 3 4 Total Maximum Points 25 25 25 25 100 Student Score

UC Davis

Hussain Al-Asaad

1. ARITHMETIC CIRCUITS (15 + 10 = 25 POINTS)

Let X be a 3-bit twos complement number represented by X2X1X0 and let Y be a 9-bit twos complement number represented by Y8Y7Y6Y5Y4Y3Y2Y1Y0. 1.1 Design a gate-level circuit C that computes the function Y = X 4 . Minimize the number of gates in your design. Assume that the input combination X2X1X0 = 100 will never appear at the inputs of C. Moreover, you can assume that the literals and their complements are available.
2

1.2 Suppose that we have an 8-bit adder (shown below), show how we can implement the function Y = 48 X + 47 .

c8

a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 c s7 s6 s5 s4 s3 s2 s1 s0 0

UC Davis

Hussain Al-Asaad

2. FLIPFLOPS (5 + 6 + 6 + 8 = 25 POINTS)
Consider a new type of a positive edge-triggered flip-flop that we call the AB flip-flop. The + characteristic equation of the AB flip-flop is Q = AQ + B . Moreover, the mode AB = 11 is not allowed. 2.1 Complete the table below.

A A B CLK Q Q 0 0 1 1

B 0 1 0 1

Mode

Not allowed (Forbidden)

2.2 Complete the excitation table of the AB flip-flop. Q 0 0 1 1 Q+ 0 1 0 1 A B

2.3 Implement the AB flip-flop using an RS flip-flop and logic gates.

2.4 Using AB flip-flops, design a counter that counts 2, 1, 0, and repeat.

UC Davis

Hussain Al-Asaad

3. ADDERS AND COUNTERS (10 + 15 = 25 POINTS)

3.1 Draw the state diagram of the counter shown below.
1 1 1 1

a
FA

a
FA

a
FA

a
FA

b
0

cout s cin D3
D flip-flop

cout s cin D2
D flip-flop

cout s cin D1
D flip-flop

cout s cin D0
D flip-flop

Q3

Q2

Q1

Q0

UC Davis

Hussain Al-Asaad

3.2 By using four D flip-flops and four full adders only (components shown below), design a 4bit binary counter with two inputs U (up) and D (down) that works as follows: 1. If U = 1, the counter counts up. 2. If D = 1, the counter counts down. 3. If U = 0 and D = 0, the counter hold its state. Assume that the input combination (U = 1, D = 1) is considered a dont care. Moreover, assume that the literals and their complements are available. Show the schematic of your design.
U D

a
FA

D
D flip-flop

cout s cin

4-bit up-down binary counter Q3 Q2 Q1 Q0

UC Davis

Hussain Al-Asaad

4. COUNTING SEQUENCE IDENTIFICATION (25 POINTS)

Suppose that we know the following information about the counter shown below: The state 7 must be on the counting sequence of the counter. For every state on the counting sequence other than state 7, the next state must be larger than the current state. Z Y X T2 Q2 Q2
Clock

f(X,Y,Z)

T1

Q1 Q1

D0

Q0 Q0

Q2

Q1

Q0

Design the combinational circuit C using the minimum number of logic gates, so that the counter produces the largest counting sequence. Also, draw the resulting state diagram of the counter (Use the order of Q2Q1Q0 in labeling the states). Is the resulting counter self starting?

UC Davis

Hussain Al-Asaad