Ao-90265ba Pci Card

AO-90265
PCIIO-II:
Data Interface FPGA for
Generation II of PCI I/O Card.
(MO-12899 & MO-13022)

Revision BA

Spec No.: Division: Burny
Author: SSH Rev: BA
File name: AO-90265BA.doc Date: 13 NOV 2001

This document is the property of Cleveland Motion Controls, Inc. and is furnished as confidential information only.
It must not be copied, traced or reproduced in any manner nor submitted to any outside parties for any purpose without
our written permission. Any use of this document without written permission of Cleveland Motion Controls, Inc. is a
violation of our exclusive rights.
PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).

Page 2 of 46 AO-90265BA
REVISION HISTORY

Rev ECO Author Date Description of Change
AA Pre1 --- SSH 30-OCT-2001
Preliminary draft of specification.
Started with base design of PCIIO-1 (MO-12068)
revision 1.9.
Delete GPIO banks A, B and C with I/O control lines.
Add two more quadrature encoder inputs -- 7 & 8.
Add new value to quadrature encoder index registers.
Add two more analog outputs.
Change ADC interface to dedicated SPI interface and
registers for each channel.
Change generic SPI interface for use with one device.
Add PC16552 UART lines, with chip selects and
interrupts.
Change outputs that drive the optos from active high to
active low.
Rearrange register addresses.
AA Pre 2 --- SSH 13-NOV-2001 Change DUART to SC28L92 from Philips.
AA Pre 3 --- DJM 20-Dec-2001
Updated changes to add in the 16550 cells and updating
the register map to reflect design changes in
implementation. System clock rate now sourced from
the PCI controller 33MHz output
AA Pre 4 --- SSH 7-Jan-2002
Change GP3 register to EIP1 and relocated to 0x4A.
Created EIP0 at 0x48. Moved ADC and DAC Control
registers to fit in EIP0 and EIP1. Updated address map.
AA Pre 5 --- SSH 23-Jan-2002
Change RELAYYOFF pin to open-drain with internal
pull-up. Put in missing FPGA pin-out.
AA Pre 6 --- SSH 07-Feb-2002
Add register 0x7A and pin descriptions for general-
purpose bi-directional I/O.
AA Pre 7 --- DJM 15-Mar-2002 Updated register map including the sub counters
AA Pre 8 --- SSH 25-Jun-2002
Update register 0x40 WC(5:0) read back value and
change 0x4C DRC(6:0) to DRC(5:0).
AA Pre 9 --- SSH 21-Sep-2002
Reorder ADC registers to make FPGA coding simpler.
Remove selection number of ADC in 0x4E register.
General revisions and added detail.
AA Pre 10 --- SSH 24-Sep-2002
Per input from Morelli:
More detail for ADC registers when NADC < 7.
Remove UART scratch registers to save gates.
AA --- SSH 20-Jan-2003 Release as version 2.0
BA CLE2427 SSH 30-Jan-2003
Corrected glitches on ADC outputs caused when the
application software updated the register currently being
written out by the firmware (version 2.1 not released).
Changed GPO22 to ignore resets by ESTOP and
watchdog timeouts. This output is used to select RS232
or RS422 from the application software.
Released as version 2.2.



TABLE OF CONTENTS
PAGE
Overview............................................................................................................................................................4
Typical PCIIO-II Card Block Diagram..............................................................................................................5
PCIIO-II Block Diagram....................................................................................................................................6
PCIIO-II Pin Descriptions (208 pins).................................................................................................................7
Bus Interface (33 pins) ..................................................................................................................................7
System Control (5 pins).................................................................................................................................9
I
2
C Bus Interface (2 pins) ............................................................................................................................10
SPI Bus Interface (5 pins)............................................................................................................................10
Quadrature Encoder Inputs (24 pins)...........................................................................................................11
Serial ADC Interface (4 pins) ......................................................................................................................12
Serial DAC Interface (6 pins) ......................................................................................................................12
General Purpose Bi-directional (8 pins) ......................................................................................................13
General Purpose Outputs (32 pins)..............................................................................................................13
General Purpose Inputs and Buffer Chip Enables (7 pins) ..........................................................................14
SRAM Interface (3 pins) .............................................................................................................................14
DUART Interface (10 pins) .........................................................................................................................14
Unused (4 pins)............................................................................................................................................15
JTAG Port (4 pins) ......................................................................................................................................15
Special Pins (9 pins) ....................................................................................................................................15
Power Supplies (52 pins).............................................................................................................................16
PCIIO-II Register Descriptions ........................................................................................................................18
Quadrature Encoder Count Registers ..........................................................................................................18
Quadrature Encoder Index Registers ...........................................................................................................20
Configuration and Control Registers...........................................................................................................24
Digital Analog Converter (DAC) Data Registers ........................................................................................29
Analog Digital Converter (ADC) Data Registers ........................................................................................30
SPI Bus Interface Registers .........................................................................................................................32
General Purpose Input (GPI) Data Registers...............................................................................................32
General Purpose Input/Output (GPIO) Interface Registers .........................................................................33
General Purpose Output (GPO) Data Registers...........................................................................................33
Quadrature Encoder Sub-Count Registers...................................................................................................34
DUAL 16550 UARTs ......................................................................................................................................40
UART0........................................................................................................................................................40
UART1........................................................................................................................................................43
Battery Backed SRAM Description .................................................................................................................45
SRAM Address Space .................................................................................................................................45
PCIIO-II Card Address Map ............................................................................................................................46
Package ............................................................................................................................................................46


Overview
The PCIIO-II chip is designed using modern high density field programmable gate array (FPGA) technology,
high level hardware description language, and logic synthesis. It provides: a programmable periodic interrupt
source; eight 24-bit quadrature encoders; an SPI bus; dedicated serial DAC interface capable of controlling
up to eight 16-bit DACs; dedicated serial, 8-channel, 12-bit ADC interface and over 80 bits of general
purpose I/O. The PCIIO-II also provides for the control signals for a 128-kbyte battery backed SRAM and
has two integrated 16550 UART.s. When combined with a PCI bridge chip the PCIIO-II creates a low cost,
reliable PCI bus based data acquisition and control card.

Typical PCIIO-II, Data Interface For Generation-II PCI Card FPGA
Card Block Diagram

Optical Isolation

PCI
Bridge
Chip

PCIIO-II FPGA
Isolated
+5V
Supply
PCI Connector

DAC & ADC
Parallel I/O
Connector
Intra -Cabinet
I/O Connector
(Legacy)
Silicon
Serial #
&
Temperature
Sensor
Battery
Backed
SRAM
128Kx8
Dual
UART
2.5V
Supply
Serial-1
(TTL)
Connector
Serial-2
(TTL)
Connector
Primary I/O Connector
Axes 1-4
Secondary I/O Connector
Axes 5-8
Keypad
Interface
Circuit
Membrane
Keypad
Connector

USB Connector
5-Wire
Touch Screen
Connector
Isolated +/-15V
Supplies In
Inter-Board
Connector
5V & 3.3V
PCI Supplies
Touch Screen
Controller
Circuit

PCIIO-II, Data Interface For Generation-II PCI Card FPGA Block
Diagram

Local Bus
Interface

Serial Bus
(SPI and I
2
C)
Interface

Serial DAC
Interface

General Purpose
Outputs

Quadrature
Encoder Interface

General Purpose
Inputs

IEEE 1149.1
Boundary Scan

Timer

Clock Generation

SRAM
Timing &
WE generation

Serial ADC
Interface

DUART


PCIIO-II, Data Interface For Generation-II PCI Card FPGA Pin
Descriptions (208 pins)
The FPGA uses low-level, 3.3V, TTL signaling. Unless otherwise noted all pins are 5V TTL logic level
compatible. Minimum valid input high voltage is 2.0V, maximum valid input low voltage is 0.8V. Output
drive capability for high output is -24 mA at 2.4V and for low output is 24 mA at 0.4V; however, currents
should be kept to minimum to reduce ground bounce within the part.
For the Type field, I is input, O is output, OZ is tristate output, OD is open drain output, IO is bi-directional,
and P is power. All pins which have the letter N as the final character in the pin name are considered to be
active low.
For pins with internal pull up or down resistors, the values may range from 50K to 100K.
Bus Interface (33 pins)
The CPU Bus Interface is designed to connect directly to the local bus created by a PCI bridge chip.
Name Pin Type Description
A7 3 I Bus Address Bit 7
These input pins are connected to the bus address.
D15 42 IO Local Bus Data Bit 15
These bi-directional pins are connected to the CPU data bus.
BHEN 15 I Byte High Enable
This active low input pin indicates that the byte corresponding to D[15:8]
should be accessed.
BLEN 16 I Byte Low Enable
This active low input pin indicates that the byte corresponding to D[7:0]
should be accessed.
CSN 10 I Chip Select
This active low input is the chip select for the PCIIO-II, it is connected to
a chip select generated by the PCI bridge.
ADSN 14 I Address Strobe

This active low input pin is the local bus address strobe which indicates
the start of new bus cycle, asserted during the first clock of a bus access.
LWR 17 I Local Bus Write/Read
This input pin is high for bus write cycles, low for bus read cycles.
LRDYN 47 O Local Bus Ready
This active low output pin indicates that the PCIIO-II, Data Interface For
Generation-II PCI Card FPGA is ready to complete the requested bus
cycle.
LIRQ1 46 O Local Bus Interrupt Request 1
This active high output is the PCIIO-II, Data Interface For Generation-II
PCI Card FPGA interrupt request.
LIRQ2 43 O Local Bus Interrupt Request 2
This active high output is the DUART interrupt request.
LRESETN 75 I Local Bus System Reset
This active low input is the master reset signal for the PCIIO-II, Data
Interface For Generation-II PCI Card FPGA.
LCLK 77 I Clock Input
This is the clock for use by the PCIIO-II, Data Interface For Generation-
II PCI Card FPGA, it must be a fixed frequency and is used to determine
the bus timing, interrupt and watchdog timing, SPI, DAC and ADC serial
port timing, and the quadrature encoder data filter timing. A 33.3 MHz
frequency is assumed in this document.

System Control (5 pins)
These pins perform special functions required by the system.
RELAYOFF 69 OD Relay Off Output
This active high signal is used to indicate when the relay to the external
machine should be turned off. This output is active if a watchdog
timeout occurs or the main system controller is in a stop state waiting for
the user to cycle the STOPPBN pin. This pin is forced active by
LRESETN or chip configuration and will remain active until a write is
performed to the Watchdog & Serial Number Control Register. This pin
has an internal pull up resistor.
STOP 192 I Stop
This active high input indicates an abnormal condition in the system and
causes the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to
hold all of its registers in the reset state until a low to high transition is
seen on the STOPPBN input. This pin has an internal pull up resistor.
STOPPBN 191 I Stop Push Button
A low to high transition on this pin is required to clear error conditions in
the chip.
QSMS 48 I Quadrature Sync Master/Slave
This input pin selects slave (low) or master (high) mode for the
quadrature synchronization pin.
QSYNC 140 IO Quadrature Synchronization
The direction of this active high pin is determined by the QSMS pin. In
master mode the quadrature encoder latch signal generated by the
interrupt timer is output onto this pin. In slave mode the internal
quadrature latch signal comes in from this pin (the internal interrupt timer
can still generate an interrupt, but it is not used to latch the quadrature
encoders).


I
2
C Bus Interface (2 pins)
This interfaces allows I
2
C devices to be accessed under software control. The PCIIO-1 used this for an
X24001 EEPROM that is now obsolete. The PCIIO-II, Data Interface For Generation-II PCI Card FPGA
card uses this interface for a DS1624 Digital Thermometer with EEPROM.
SCLN 58 O Serial Clock
This active low output pin connects to an inverter to drive an I
2
C two-
wire bus clock line.
SDA 57 IO Serial Data
This bi-directional pin connects directly to the data bus of I
2
C devices.
SPI Bus Interface (5 pins)
This interface allows the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to communicate with a
device that uses the Serial Peripheral Interconnect (SPI) bus.
Note: The PCIIO-1 supported two SPI devices. One was the 8-channel ADC and the other was a front panel
device (currently not in use). With the PCIIO-II, Data Interface For Generation-II PCI Card FPGA, only one
generic SPI device is supported. The ADC interface is now a dedicated sub-system.
SPIDON 139 O Serial Data Out
This active low output pin is the transmitted data to the SPI device.
SPIDI 135 I Serial Data In
This input pin is the received data from the SPI device.
SPICLKN 136 O Serial Clock
This active low output pin is the clock to the SPI device.
SPICSN 138 O Serial Chip Select
This active low output pin is the chip select for the SPI device.
RESETN 49 O Reset
This active low output is the reset for any devices which require it. It is
controlled by software.

Quadrature Encoder Inputs (24 pins)
This interfaces allows up to 8 quadrature encoders to be connected to the PCIIO-II, Data Interface For
Generation-II PCI Card FPGA. The counter clock rate is programmable, and the resolution or each encoder is
20 bits. Index pulse is defined as a rising edge on QExCHA while QExIDX is high. If the IDXMODE bit is
set, index is defined as a rising edge on QExIDX followed by a rising edge on QECHA. The quadrature
encoder counter will count up on a rising edge on QExCHA while QExCHB is low, a rising edge on B while
A is high, a falling edge on A while B is high, or a falling edge on B while A is low. The counters will count
down on a rising edge of B with A low, a rising edge on A with B high, a falling edge on B with A high, or a
falling edge on A with B low.
Additionally, each encoder input pins is registered so that it can be used as a general-purpose input pin or for
advanced encoder troubleshooting and testing. Encoder inputs for channels 1-4 are registered in EIP0 and
inputs for channels 5-8 are registered in EIP1.
QE1CHA 168 I Quadrature Encoder 1 - Channel A (EIP0, bit 0)
QE1CHB 167 I Quadrature Encoder 1 - Channel B (EIP0, bit 1)
QE1IDX 166 I Quadrature Encoder 1 - Index (EIP0, bit 2)
These inputs are for quadrature encoder 1. To prevent them from floating
when unconnected, these pins should have an external pull up/down
resistor.

resistor.

resistor.

resistor.

QE5IDX 187 I Quadrature Encoder 5 Index (EIP1, bit 2)
resistor.


resistor.

resistor.

resistor.
Serial ADC Interface (4 pins)
This interface allows the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to communicate with a
MAX1202 Analog-to-Digital converter that uses a Serial Peripheral Interconnect (SPI) bus interface. The
interface is tailored to continuously cycle through the ADC channels at the highest possible conversion rate
timing.
ADCDON 86 O Serial Data Out to ADC
This active low output pin is the transmitted data to the ADC device.
ADCDI 87 I Serial Data In from ADC
This input pin is the received data from the ADC device.
ADCCLKN 83 O Serial Clock to ADC
This active low output pin is the clock to the ADC device.
ADCCSN 84 O Serial Chip Select
This active low output pin is the chip select for the ADC device.
Serial DAC Interface (6 pins)
This interface allows up to (4) serial interface dual DACs to be connected to the PCIIO-II, Data Interface For
Generation-II PCI Card FPGA.
SDCLKN 148 O Serial DAC Clock
This active low output provides the clock to the serial DACs.
SDDATAN 149 O Serial DAC Data
This active low output provides the data to the serial DACs.
SDSELAN 141 O Serial DAC Select A
This active low output provides the channel select to serial DACA,
channels 1 and 2.
SDSELBN 142 O Serial DAC Select B

This active low output provides the channel select to serial DACB,
channels 3 and 4.
SDSELCN 146 O Serial DAC Select C
This active low output provides the channel select to serial DACC,
channels 5 and 6.
SDSELDN 147 O Serial DAC Select D
This active low output provides the channel select to serial DACD,
channels 7 and 8.
General Purpose Bi-directional (8 pins)
GPIO6 206 IO General Purpose I/O bit 6
These bi-directional pins are available for use as input or output pins as
needed. These pins have a weak (~50K) internal pull-up.
GPIODIR 185 I GPIO Direction
This active high input pin causes the GPIO pins to become inputs.
General Purpose Outputs (32 pins)
GPO31 134 O General Purpose Output 31

These output pins are used as general purpose outputs.
General Purpose Inputs and Buffer Chip Enables (7 pins)
These pins are used to control the enables of external 74HCT224 or 74LS224 type buffers, each chip enable
is assumed to be connected to a pair of octal buffer devices to form a 16 bit input port which drives the local
bus when enabled.
GPICS0N 59 O General Purpose Input Port Chip Select 0
These active low output pins are fully decoded chip selects (including
strobe timing) for external 16 bit wide input port buffers.
UIP0 193 I User Input Pin 0
This is a 4-bit general-purpose user input. These inputs have internal
pull-ups.
SRAM Interface (3 pins)
This optional interface allows a single 8 bit wide static RAM chip to be connected to the PCIIO-II, Data
Interface For Generation-II PCI Card FPGA chip. The address base and size of the SRAM is programmable
in the PCI bridge chip.
SRAMCSIN 18 I SRAM Chip Select In
This active low input is the chip select input for an optional external
SRAM chip. This pin is driven by the PCI bridge chip.
SRAMCSN 44 O SRAM Chip Select
This active low output is the chip select output for an optional external
SRAM chip.
SRAMWEN 45 O SRAM Write Enable
This active low output is the write enable for an optional external SRAM
chip.
DUART Interface (10 pins)
The following pins are for the dual integrated U16550 cells. The cells support only the CTS/RTS and OUT1
modem pins.
RXDATA0 81 I UART RX data UART0
RXDATA1 82 I UART RX data UART1
This is the RX data for the dual UARTs. If the UART(s) are not used
then the pin needs a pull-up.
CTS0N 62 I Clear to send UART0

CTS1N 63 I Clear to send UART1
This is the clear to send modem control signal for the integrated dual
16550s. If the UARTs are not used then the inputs need a pull-up.
TXDATA0 73 O UART TX data UART0
TXDATA1 74 O UART TX data UART1
This is the TX data for the dual UARTs.
RTS0N 70 O Ready to send UART0
RTS1N 71 O Ready to send UART1
This is the ready to send modem output for the integrated dual 16550s.
OUT1N0 67 O OUT1N output UART0
OUT1N1 68 O OUT1N output UART1
This is the modem OUT1 output for the dual 16550s.
Unused (4 pins)
These pins are not connected in the FPGA.
NC1 55 U No Connect
NC2 56 U No Connect

GCLK0 80 I Global Clock 0 or User Input
GCLK2 182 I Global Clock 2 or User Input

JTAG Port (4 pins)
This is an industry standard IEEE1149.1 (JTAG) boundary scan test access port.
TDI 159 I JTAG Test Data Input
TDO 157 OZ JTAG Test Data Output
TMS 2 I JTAG Test Mode Select
TCLK 207 I JTAG Clock
These pins provide an industry standard IEEE1149.1 (JTAG) Boundary
Scan port. The TDI and TCLK pins should be grounded if this interface is
not used.
Special Pins (9 pins)
These pins are reserved and should not be connected unless otherwise noted.
M0 52 I Mode 0
M1 50 I Mode 1
M2 54 I Mode 2
These pins are grounded for normal (master serial configuration) FPGA
configuration.
DONE 104 IO Done
PROGN 106 I Program
DIN 153 I Program Data In
CCLK 155 O Program Clock
INITN 107 IO Program Memory Initialization
DOUT 154 O Data Out

These pins are used during PCIIO-II, Data Interface For Generation-II
PCI Card FPGA configuration, see the FPGA chip documentation for
details.
Power Supplies (52 pins)
These pins provide power and ground connectivity to the chip. All V
CCINT
pins must be connected to the same
2.5V power supply. For 5V tolerant TTL I/O, all V
CCO
pins must connect to the same 3.3V power supply.
V
CCINT
1 13 P V
CCINT
V
CCINT
2 28 P V
CCINT
V
CCINT
3 38 P V
CCINT
V
CCINT
4 66 P V
CCINT
V
CCINT
5 76 P V
CCINT
V
CCINT
6 91 P V
CCINT
V
CCINT
7 118 P V
CCINT
V
CCINT
8 128 P V
CCINT
V
CCINT
9 143 P V
CCINT
V
CCINT
10 171 P V
CCINT
V
CCINT
11 186 P V
CCINT
V
CCINT
12 196 P V
CCINT
V
CCINT
is 2.5V +/- 5% power supply voltage.
V
CCO
1 12 P V
CCO
V
CCO
2 26 P V
CCO
V
CCO
3 39 P V
CCO
V
CCO
4 53 P V
CCO
V
CCO
5 65 P V
CCO
V
CCO
6 78 P V
CCO
V
CCO
7 92 P V
CCO
V
CCO
8 105 P V
CCO
V
CCO
9 117 P V
CCO
V
CCO
10 130 P V
CCO
V
CCO
11 144 P V
CCO
V
CCO
12 156 P V
CCO
V
CCO
13 170 P V
CCO
V
CCO
14 184 P V
CCO
V
CCO
15 197 P V
CCO
V
CCO
16 208 P V
CCO
V
CCO
is 3.3V +/- 5% power supply voltage.
GND1 1 P Ground
GND2 11 P Ground
GND3 19 P Ground
GND4 25 P Ground
GND5 32 P Ground
GND6 40 P Ground
GND7 51 P Ground
GND8 64 P Ground
GND9 72 P Ground
GND10 79 P Ground
GND11 85 P Ground
GND12 93 P Ground
GND13 103 P Ground
GND14 116 P Ground
GND15 124 P Ground
GND16 131 P Ground

GND17 137 P Ground
GND18 145 P Ground
GND19 158 P Ground
GND20 169 P Ground
GND21 177 P Ground
GND22 183 P Ground
GND23 190 P Ground
GND24 198 P Ground
Power supply ground.

PCIIO-II, Data Interface For Generation-II PCI Card FPGA Register
Descriptions
This section describes the registers in the PCIIO-II, Data Interface For Generation-II PCI Card FPGA, which
can be accessed by software. Bit numbers are shown above the register field graphic and the bit values loaded
into the register upon reset is shown below. Fields marked undefined will return random values when read.
Note:
1) All registers should be accessed using 16 bit transfers.
2) The Base address is defined by the address assigned to the PCI card by the PCI bridge master
plus the base address configuration of chip select 0 (CS0) of the PCI bridge chip. CS0 base address
is currently configured to 0x0 and the range limited to 256 bytes (0xFF).
3) When reading the Quadrature Encoder Count and Index registers, the Low Word must be read
first, and this read must be followed by a read of the High Word. Reading the High Word first, or
reading the Low Word without reading the High Word next may cause the Quadrature Encoders
to malfunction.
4) When reading the Encoder Sub-Count registers -- for each channel the Denominator Low word
must be read first, followed by a read of the Denominator High Word, followed by a read of the
Numerator Low Word and then followed by a read of the Numerator High Word. Reading the
Sub-Count registers in any other order will return incorrect data. For example, read Base + 0x80,
0x82, 0xA0 and 0xA2 for encoder channel 1; then go on to another four registers for another
channel, if needed.
Quadrature Encoder Count Registers
Base + 0x00 RO Q1L: Quadrature Encoder 1 Count Low Word
This register contains the lower 16 bits of the latched count for quadrature encoder 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1(15:0)
15:0 Q1(15:0) Quadrature Encoder 1 Lower 16 bits
Base + 0x02 RO Q1H: Quadrature Encoder 1 Count High Word
This register contains the upper 8 bits of the latched count for quadrature encoder 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q1(23:16)
3:0 Q1(19:16) Quadrature Encoder 1 Upper 4 bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q2(15:0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q2(23:16)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q3(15:0)
Base + 0x0A RO Q3H: Quadrature Encoder 3 Count High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q3(23:16)
Base + 0x0C RO Q4L: Quadrature Encoder 4 Count Low Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q4(15:0)
Base + 0x0E RO Q4H: Quadrature Encoder 4 Count High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q4(23:16)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q5(15:0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q5(23:16)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q6(15:0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q6(23:16)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q7(15:0)
Base + 0x1A RO Q7H: Quadrature Encoder 7 Count High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q7(23:16)
Base + 0x1C RO Q8L: Quadrature Encoder 8 Count Low Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q8(15:0)
Base + 0x1E RO Q8H: Quadrature Encoder 8 Count High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Q8(23:16)
Quadrature Encoder Index Registers
Base + 0x20 RO Q1IL: Quadrature Encoder 1 Index Low Word
This register contains the lower 16 bits of the latched index for quadrature encoder 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1I(15:0)
15:0 Q1I(15:0) Quadrature Encoder 1 Index Lower 16 bits

Base + 0x22 RO Q1IH: Quadrature Encoder 1 Index High Word
This register contains the upper 8 bits of the latched index for quadrature encoder 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1N Undefined Q1I(23:16)
3:0 Q1I(19:16) Quadrature Encoder 1 Index Upper 4 bits
15 Q1N Quadrature Encoder 1 New Index Value bit.
This bit is set every time a Quadrature Encoder 1 Index register value is
latched and is cleared after every read of the register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q2I(15:0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q3I(15:0)
Base + 0x2A RO Q3IH: Quadrature Encoder 3 Index High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Base + 0x2C RO Q4IL: Quadrature Encoder 4 Index Low Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q4I(15:0)
Base + 0x2E RO Q4IH: Quadrature Encoder 4 Index High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q5I(15:0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q6I(15:0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q7I(15:0)
Base + 0x3A RO Q7IH: Quadrature Encoder 7 Index High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base + 0x3C RO Q8IL: Quadrature Encoder 8 Index Low Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q8I(15:0)
Base + 0x3E RO Q8IH: Quadrature Encoder 8 Index High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Configuration and Control Registers
The registers in this section allow the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to be
configured for operation, allow the silicon serial number to be read, the temperature to be read and the
interrupt to be acknowledged.
Base + 0x40 RW WCR: Watchdog & I
2
C Bus Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS TB WC(5:0) SC SD SE TO RST WTD(2:0)
pin 0 ? ? ? ? ? ? 0 pin 0 0* 0 0* 0* 0*
* These bits are reset by the hardware reset pin only and are not reset by a time out.
Note: The RELAYOFF pin is active after chip reset or configuration and will remain active, ignoring
transitions on the STOPPBN pin, until after the first write to this register has been performed. This allows
normal operation in situations where the STOPPBN pin glitches on power up.
2:0 WTD(2:0) Watchdog Timer Duration
These bits set the watchdog timer duration. Once a non-zero value is
written, the timer becomes enabled and this field cannot be changed.
000 = Watchdog not enabled.
001 = 250 s time out
010 = 1 ms
011 = 2 ms
100 = 5 ms
101 = 10 ms
110 = 20 ms
111 = 50 ms
3 RST Front Panel Reset
This bit is sets the RESETN pin to control the front panel reset. A 0
sets the RESETN pin active to hold the front panel controller in reset. A
1 releases the front panel from reset. Note that on system reset the front
panel is held in reset.
4 TO Time Out
This bit is set when the watch dog timer trips. All PCIIO-II, Data
Interface For Generation-II PCI Card FPGA ports are held in their reset
state and the RELAYOFF pin will be active until the time out is cleared
by a low to high transition on STOPPBN.
5 SE Serial Bus Data Output Enable
This bit controls the direction of the serial bus data pin. Write 1 to
cause the data pin to drive out (and the SD bit to control it), write 0 to
cause the data pin to become an input (which is read using the SD bit).
6 SD Serial Bus Data
When the SE bit is 1 this bit controls the SDA pin. Reading this bit
always returns the state of the SDA pin.
7 SC Serial Bus Clock
This bit controls the SCLN pin, write 1 for force the clock low, write
0 to force the clock high.
13:8 WC(5:0) Watchdog Command
Write 101001 to kick the watchdog to prevent time out.
Writing any other value while the watchdog is enabled will cause an
immediate time out. Depending on the FPGA implementation, these may
read back as all 0s or all 1s.

14 TB Time Base
This bit toggles LCLKfrequency/166 times per second (every 5
microseconds with the 33.3 MHz LCLK).
15 MS Master / Slave
This pin indicates the quadrature encoder synchronization pin mode, 1
for master, 0 for slave. See the QSMS pin for additional information.
Base + 0x42 RW ICR: Interrupt Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELAY
DISABLE
IA T IN(4:0) RELAY
OFF
STOP STOPPBN IP(4:0)
0 ? ? 0 0 0 0 0 pin pin pin 0 0 0 0 0
15 RELAYDISABLE Relay Disable
Write 1 to disable the external relay by forcing the RELAYOFF pin
high. Write 0 to enable the external relay to follow the normal error
conditions. Note that enabling the external relay does not force it on. All
other error conditions must be satisfied before the RELAYOFF pin will
go low to turn on the external relay.
14 IA Interrupt Acknowledge
Write 1 to acknowledge an interrupt, it is not necessary to write a 0
after writing the 1. Note that reading this bit gives a random result.
3 T Test Mode Enable.
This bit is used for manufacturing test only, when set it causes the GPO
pins to float. (Formerly GPIODIR bit 3 for PCIIO-1).
12:8 IN(4:0) Interrupt Number
This value is read only, and is incremented each time an interrupt is
requested. It may be used to detect missed interrupts.
7 RELAYOFF RELAYOFF
This bit reflects the RELAYOFF pin value.
6 STOP STOP
This bit reflects the STOP input pin value.
5 STOPPBN STOPPBN
This bit reflects the STOPPBN input value. A low to high transition will
reset a watchdog timeout.
4:0 IP(4:0) Interrupt Rate
These bits set the interrupt according to the formula LCLK
frequency/(5000 * IP). For the default 10MHz LCLK, IP is interrupt
period in milliseconds. Write 0000 to disable the interrupt.
Base + 0x44 WO STG: Soft Trigger Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undef.
15:0 ST Soft Trigger
A write of any value to this register will force a trigger to the interrupt
quadrature latch to capture the current encoder counter values.
This soft trigger is independent of the interrupt and can work
concurrently with an enabled interrupt.

Base + 0x46 WR QCCR: Quadrature Clock Control Register
This register controls the clock used by the quadrature encoder counters.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID Undefined QCM I RFU
? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? ?
15:8 ID(7:0) Current revision of the PCIIO FPGA, see the Revision History section of
this document for version number details. The ID is stored in BCD
format.
3 QCM Quadrature Count Mode
This bit changes the behavior of the quadrature encoder counters. When
this bit is cleared, the quadrature encoder counters will function as
normal 24-bit up/down counters. When this bit is set, the quadrature
encoder counters will clear on each index pulse. The clearing of the
counters happens whenever the index pulse is high, channel B is high and
there is a transition on channel A.
2 I = IDXMODE When set this bit changes the behavior of the index detection circuit from
index = rising edge on QExCHA during QExIDX high to index = rising
edge on QExIDX followed by rising edge on QExCHA.
1:0 RFU Reserved for Future Use
Formerly QCFR Quadrature Clock Filter Rate in PCIIO-I.
Quad counter filtering of the inputs is fixed to LCLK/8.
(33.3 MHz/8 = 4.16 MHz)
Base + 0x48 RO EIP0: Encoder Input Pin Register 0
This register contains the state of each input pin for encoder channels 1-4.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined E4X E4B E4A E3X E3B E3A E2X E2B E2A E1X E1B E1A
11 E4X Encoder 4 Index
This is the value of the QE4IDX pin.
10 E4B Encoder 4 Channel B
This is the value of the QE4CHB pin.
9 E4A Encoder 4 Channel A
This is the value of the QE4CHA pin.

Base + 0x4A RO EIP1: Encoder Input Pin Register 1
This register contains the state of each input pin for encoder channels 5-8. In also contains the state of the
four user input pins on the FPGA.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIP[3:0] E8X E8B E8A E7X E7B E7A E6X E6B E6A E5X E5B E5A
15:12 UIP[3:0] User Input Pins GPI[3:0]. These bits are the UIP[3:0] pin values.


Base + 0x4C RW DAC Control Register
This register controls the clock used by the DAC interface.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR Undefined NDAC Und. DCR(5:0)
1 ? ? ? ? ? 1 1 ? ? 1 1 1 1 1 1
15 DR DAC Interface Reset
When 1 this bit forces the DAC interface to transmit all zeros to all
DAC channels.
9:8 NDAC Number of DAC chip select outputs.
This value sets the number of AD1866 DAC chips the FPGA supports.
This number is the number of DAC chips minus 1. The DACs need to be
connected to SDSELA SDSELD. Supporting less DAC outputs
increases the rate of change at the DAC output.
Each AD1866 DAC has two channels; therefore, setting NDAC to 11
supports 4 DACs and thus 8 DAC channels.
5:0 DCR(5:0) DAC Clock Rate
This value sets the divide rate for the DAC interface.
DAC Clock = LCLK/[2(1+DCR)]
The DAC Clock range is 16.6 MHz to 260 kHz for the 33.3 MHz LCLK.
Note: The AD1866 can support 13.5 MHz clocks, but the opto-isolation
limits the clock to about 6 MHz.
Base + 0x4E RW ADC Control Register
This register controls the clock used by the DAC interface.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined NADC ST ACR(5:0)
? ? ? ? ? 1 1 1 ? 0 1 1 1 1 1 1
10:8 NADC(2:0) Number of ADC channels
This value is the number of MAX1202 ADC channels minus one that are
monitored. Supporting less channels increases the sample rate of the
remaining ADC inputs.
By design of the MAX1202 and in an effort to reduce the complexity of
the FPGA, channels 0 to N-1 are sequentially monitored in the following
order: 0, 2, 4, 6, 1, 3, 5 and 7. As NADC is reduced below 111,
channels are dropped off the end of the sequence. The sequence is
registered starting at Base + 0x62 and increasing by 0x02. The last
monitored channel is always placed in the Base + 0x60 register.
The ADC registers (starting at Base + 0x60) are named based on
NADC = 111.
6 ST Start Bit
This is the start control of the ADC controller. If set, the ADC controller
will sequentially monitor the specified ADC channel inputs.
5:0 ACR(5:0) ADC Clock Rate
This value sets the divide rate for the ADC interface.
ADC Clock = LCLK/[2(1+ACR)]
The ADC Clock range is 16.6 MHz to 260 kHz for the 33.3 MHz LCLK.
Note: The MAX1202 can only support clocks up to 2 MHz.


Digital Analog Converter (DAC) Data Registers
Base + 0x50 WO DAC1: DAC 1 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15:0 DAC1(15:0) Digital-to-Analog Converter 1 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC2(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC3(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC4(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC5(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Base + 0x5A WO DAC6: DAC 6 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC6(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Base + 0x5C WO DAC7: DAC 7 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC7(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Base + 0x5E WO DAC8: DAC 8 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC8(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Analog Digital Converter (ADC) Data Registers
Note: The order of the ADC channel registers is not sequential. This was done to reduce FPGA complexity.
Base + 0x60 RO ADC7: ADC 7 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined ADC7(11:0)
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
11:0 ADC7(11:0) Analog-to-Digital Converter 7 Data
This is the ADC channel 7 for NADC = 111. The contents of this
register will change based on the value of NADC in the ADC Control
Register (0x4E). The follow table list the contents of this register based
on the value of NADC.
NADC Register Contents
111 ADC Channel 7
110 ADC Channel 5
101 ADC Channel 3
100 ADC Channel 1
011 ADC Channel 6
010 ADC Channel 4
001 ADC Channel 2
000 ADC Channel 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
This is the ADC Channel 0 value for 001 ! NADC ! 111.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
Base + 0x6A RO ADC1: ADC 1 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
Base + 0x6C RO ADC3: ADC 3 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
Base + 0x6E RO ADC5: ADC 5 Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
This is the ADC Channel 5 value for NADC = 111.


SPI Bus Interface Registers
Base + 0x70 RW SPIBCS: SPI Bus Control and Status
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined SCR(5:0) Und. SBB Und. SDS(3:0)
? ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ?
9:8 SCR(5:0) Serial Clock Rate
This value sets the divide rate for the SPI interface clock.
SPI Clock = LCLK/[2(1+SCR)]
The SPI Clock range is 16.6 MHz to 260 kHz for the 33.3 MHz LCLK
6 SBB Serial Bus Busy
When 1 this bit indicates that the serial bus is busy. This bit is set by a
write to the SPID register and cleared when the serial bus transaction is
complete and data from the target is available to be read.
3:0 SDS(3:0) Serial Data Size
1111 = 16 bit, 1110 = 15 bit, etc. Note that 0010 (3), 0001 (2) and
0000 (1 bit) are not valid.
Base + 0x72 RW SPID: SPI Bus Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPID(15:0)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15:0 SPID(15:0) SPI Bus Data
Writing to this register starts a serial bus transaction, the data written will
be shifted out onto the SPI bus output least significant bit first and the
data from the SPI bus inputs will be shifted into this register most
significant bit first. This was done to reduce FPGA complexity.
For data sizes other than 16-bit the low order bits are used.
General Purpose Input (GPI) Data Registers
Note that these registers are implemented by external hardware with only a chip select being provided by the
PCIIO-II, Data Interface For Generation-II PCI Card FPGA.
Base + 0x74 RO GPI0: General Purpose Input Register 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI(15:0)
15:0 GPI(15:0) General Purpose Input Value
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI(31:16)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI(47:32)
General Purpose Input/Output (GPIO) Interface Registers
Base + 0x7A RW GPIO: General Purpose Input/Output
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIODIR Undefined GPIO(6:0)
pin ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1
15 GPIODIR General Purpose I/O Direction
When 0 this bit indicates that the GPIO pins are outputs. This bit is
controlled by an input pin on the chip, when the pin is 1 the GPIO pins
are inputs.
6:0 GPIO(6:0) General Purpose I/O
When read, this register is a direct read of the GPIO pin inputs. Writes
control the GPIO pins only if the GPIODIR is 0. The GPIO bits are set to
all 1s by reset, ESTOP or watchdog timeout.
General Purpose Output (GPO) Data Registers
Base + 0x7C RW GPO0: General Purpose Output Register 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPO(15:0)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15:0 GPO0(15:0) General Purpose Output Pin Control
Writes to this register control the state of the GPO[15:0] pins. This
register is set to all 1s by reset, ESTOP or watchdog timeout.
Base + 0x7E RW GPO1: General Purpose Output Register 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPO(31:16)
1 1 1 1 1* 1* 1* 1* 1 1* 1 1 1 1 1 1
13:0 GPO1(31:16) General Purpose Output Pin Control
Writes to this register control the state of the GPO[31:16] pins. Except as
noted below, this register is set to all 1s by reset, ESTOP or watchdog
timeout.
*Note: Bits 11:8 & 6 (GPO[27:24] & GPO22) are set to 1s by reset
only.

Quadrature Encoder Sub-Count Registers

One way to improve low speed encoder resolution is to do what is some times called "Sub-Count
Interpolation". It requires two additional high speed counters for each encoder channel. The goal is to
measure the distance traversed between the encoder pulses.

One counter (the Denominator) is feed the highest frequency possible (LCLK) and measures the time
between the last two encoder edges observed.
The second counter (the Numerator) is feed the same high frequency input (LCLK) and measures the time
since the last encoder edge was observed.

Time = (counter value) * (LCLK period * 8).
With LCLK = 33.3 MHz, LCLK period = 30 nsec.

For each quadrature encoder channel, both counter values are latched when its quadrature encoder count is
read.
Base + 0x80 RO Q1SDL: Quadrature Encoder 1 Sub-Count Denom. Low Word
This register contains the lower 16 bits of the latched count for quadrature encoder 1 denominator used in
sub-count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1SD(15:0)
15:0 Q1SD(15:0) Quadrature Encoder 1 Sub-Count Denominator Lower 16 bits
Base + 0x82 RO Q1SDH: Quadrature Encoder 1 Sub-Count Denom. High Word
This register contains the upper 16 bits of the latched count for quadrature encoder 1 denominator used in
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1SD(31:16)
7:0 Q1SD(23:16) Quadrature Encoder 1 Sub-Count Denominator Upper 16 bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q2SD(15:0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q2SD(31:16)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q3SD(15:0)
Base + 0x8A RO Q3SDH: Quadrature Encoder 3 Sub-Count Denom. High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q3SD(31:16)
Base + 0x8C RO Q4SDL: Quadrature Encoder 4 Sub-Count Denom. Low Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q4SD(15:0)
Base + 0x8E RO Q4SDH: Quadrature Encoder 4 Sub-Count Denom. High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q4SD(31:16)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q5SD(15:0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q5SD(31:16)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q6SD(15:0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q6SD(31:16)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q7SD(15:0)
Base + 0x9A RO Q7SDH: Quadrature Encoder 7 Sub-Count Denom. High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q7SD(31:16)
Base + 0x9C RO Q8SDL: Quadrature Encoder 8 Sub-Count Denom. Low Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q8SD(15:0)
Base + 0x9E RO Q8SDH: Quadrature Encoder 8 Sub-Count Denom. High Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q8SD(31:16)

Base + 0xA0 RO Q1SNL: Quadrature Encoder 1 Sub-Count Num. Low Word
This register contains the lower 16 bits of the latched count for quadrature encoder 1 numerator used in sub-
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1SN(15:0)
15:0 Q1SN(15:0) Quadrature Encoder 1 Sub-Count Numerator Lower 16 bits
Base + 0xA2 RO Q1SNH: Quadrature Encoder 1 Sub-Count Num. High Word
This register contains the upper 16 bits of the latched count for quadrature encoder 1 numerator used in sub-
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1SN(31:16)
7:0 Q1SN(23:16) Quadrature Encoder 1 Sub-Count Denominator Upper 16 bits
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q2SN(15:0)
Base + 0xA6 RO Q2SNH: Quadrature Encoder 2 Sub-Count Num. High Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q2SN(31:16)
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q3SN(15:0)
Base + 0xAA RO Q3SNH: Quadrature Encoder 3 Sub-Count Num. High Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q3SN(31:16)

Base + 0xAC RO Q4SNL: Quadrature Encoder 4 Sub-Count Num. Low Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q4SN(15:0)
Base + 0xAE RO Q4SNH: Quadrature Encoder 4 Sub-Count Num. High Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q4SN(31:16)
Base + 0xB0 RO Q5SNL: Quadrature Encoder 5 Sub-Count Num. Low Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q5SN(15:0)
Base + 0xB2 RO Q5SNH: Quadrature Encoder 5 Sub-Count Num. High Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q5SN(31:16)
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q6SN(15:0)
Base + 0xB6 RO Q6SNH: Quadrature Encoder 6 Sub-Count Num. High Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q6SN(31:16)

count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q7SN(15:0)
Base + 0xBA RO Q7SNH: Quadrature Encoder 7 Sub-Count Num. High Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q7SN(31:16)
Base + 0xBC RO Q8SNL: Quadrature Encoder 8 Sub-Count Num. Low Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q8SN(15:0)
Base + 0xBE RO Q8SNH: Quadrature Encoder 8 Sub-Count Num. High Word
count calculations.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q8SN(31:16)

DUAL 16550 UARTs
This section is the register map for the dual integrated 16550 UARTS. The integrated UARTs use an
identical register map as the original 16550 device with the exception of the 8 bit register on 16bit
boundaries. For additional information of the 16550 register map, refer to the 16550 data sheet
accompanying this specification.
UART0
Base + 0xC0 RO (DLAB=0) RX Buffer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined RX Data
7:0 RXData(7:0) This is the RX data. A read of this location pops an RX value.
Base + 0xC0 WO (DLAB=0) TX Buffer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined TX Data
7:0 TXData(7:0) This is the TX data. A write of this location pushes a value to the TX
FIFO
Base + 0xC0 RW (DLAB=1) Divider Latch LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Divider
7:0 Divider(7:0) This is LSB of the baud rate divider.

Base + 0xC2 RW (DLAB=0) Interrupt Enable Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined EDSSI ELSI ETBEI ERBFI
? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
3 EDSSI Enable Modem Status Interrupt
2 ELSI Enable RX Line Status Interrupt
1 ETBEI Enable TX Hold Register Empty Interrupt
0 ERBFF Enable RX Data Available Interrupt

Base + 0xC2 RW (DLAB=1) Divider Latch MSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Divider
7:0 Divider(15:8) This is MSB of the baud rate divider.


Base + 0xC4 RO Interrupt ID Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined FE INTID
7:6 FIFO Enable FIFO Enable. 11 in 16550 mode 00 in 16450 mode
3:0 INTID(3:0) Interrupt ID values see 16550 spec

Base + 0xC4 WO FIFO Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined RXT DMA Mode TXFR RXFR FE
? ? ? ? ? ? ? ? 0 0 ? ? 0 0 0 0
7:6 RX Trigger RX FIFO trigger level
3 DMA Mode DMA Mode select (Not Supported because the pins are not available)
2 TXFR TX FIFO reset
1 RXFR RX FIFO reset
0 FE FIFO Enable
Base + 0xC6 RW Line Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined DLAB SB SP EPS PEN STB WLS
? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
7 DLAB Divisor Latch Access Bit
6 SB Set Break
5 SP Stick Parity
4 EPA Even Parity
3 PEN Parity Enable
2 STB Stop Bits
1:0 WLA Word Length

Base + 0xC8 RW Modem Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined LOOP OUT2 OUT1 RTS DTR
? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
4 LOOP Loop Back Mode
3 OUT2 Out 2 Control (Not an external pin)
2 OUT1 Out 1 Control
1 RTS Ready to send Control
0 DTR Data Terminal Ready (Not an external pin)


Base + 0xCA RO Line Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined EIRX TEMT THRE BI FE PE OE DR
7 EIRX Error in RX FIFO
6 TEMT TX Empty
5 THRE TX Hold Register Empty
4 BI Break Interrupt
3 FE Frame Error
2 PE Parity Error
1 OE RX Overrun Error
0 DR RX Data Ready
Base + 0xCC RO Modem Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined DCD RI DSR CTS DDCD TERI DDRS DCTS
7 DCD Data Carrier Detect (No External Pin)
6 RI Ring Indicator (No External Pin)
5 DSR Data Set Ready (No External Pin)
4 CTS Clear to Send
3 DDCD Delta on DCD (No External Pin)
2 TERI Rising on RI (No External Pin)
1 DDRS Delta on DRS (No External Pin)
0 DCTS Delta on CTS
Base + 0xCE RW Scratch Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Scratch
7:0 Scratch(7:0) Scratch Register
Not implemented.

UART1
Base + 0xD0 RO (DLAB=0) RX Buffer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined RX Data
7:0 RXData(7:0) This is the RX data. A read of this location pops an RX value.
Base + 0xD0 WO (DLAB=0) TX Buffer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined TX Data
7:0 TXData(7:0) This is the TX data. A write of this location pushes a value to the TX
FIFO
Base + 0xD0 RW (DLAB=1) Divider Latch LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Divider
7:0 Divider(7:0) This is LSB of the baud rate divider.

Base + 0xD2 RW (DLAB=0) Interrupt Enable Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EDSSI ELSI ETBEI ERBFI
? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
3 EDSSI Enable Modem Status Interrupt
2 ELSI Enable RX Line Status Interrupt
1 ETBEI Enable TX Hold Register Empty Interrupt
0 ERBFF Enable RX Data Available Interrupt

Base + 0xD2 RW (DLAB=1) Divider Latch MSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Divider
7:0 Divider(15:8) This is MSB of the baud rate divider.

Base + 0xD4 RO Interrupt ID Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined FE INTID
7:6 FIFO Enable FIFO Enable. 11 in 16550 mode 00 in 16450 mode
3:0 INTID(3:0) Interrupt ID values see 16550 spec


Base + 0xD4 WO FIFO Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined RXT DMA Mode TXFR RXFR FE
? ? ? ? ? ? ? ? 0 0 ? ? 0 0 0 0
7:6 RX Trigger RX FIFO trigger level
3 DMA Mode DMA Mode select (Not Supported because the pins are not available)
2 TXFR TX FIFO reset
1 RXFR RX FIFO reset
0 FE FIFO Enable
Base + 0xD6 RW Line Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined DLAB SB SP EPS PEN STB WLS
? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
7 DLAB Divisor Latch Access Bit
6 SB Set Break
5 SP Stick Parity
4 EPA Even Parity
3 PEN Parity Enable
2 STB Stop Bits
1:0 WLA Word Length

Base + 0xD8 RW Modem Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined LOOP OUT2 OUT1 RTS DTR
? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
4 LOOP Loop Back Mode
3 OUT2 Out 2 Control (Not an external pin)
2 OUT1 Out 1 Control
1 RTS Ready to send Control
0 DTR Data Terminal Ready (Not an external pin)

Base + 0xDA RO Line Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined EIRX TEMT THRE BI FE PE OE DR
7 EIRX Error in RX FIFO
6 TEMT TX Empty
5 THRE TX Hold Register Empty

4 BI Break Interrupt
3 FE Frame Error
2 PE Parity Error
1 OE RX Overrun Error
0 DR RX Data Ready
Base + 0xDC RO Modem Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined DCD RI DSR CTS DDCD TERI DDRS DCTS
7 DCD Data Carrier Detect (No External Pin)
6 RI Ring Indicator (No External Pin)
5 DSR Data Set Ready (No External Pin)
4 CTS Clear to Send
3 DDCD Delta on DCD (No External Pin)
2 TERI Rising on RI (No External Pin)
1 DDRS Delta on DRS (No External Pin)
0 DCTS Delta on CTS
Base + 0xDE RW Scratch Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined Scratch
7:0 Scratch(7:0) Scratch Register
Not implemented.
Battery Backed SRAM Description
This section describes the battery backed SRAM populated on the PCI card. Although the SRAM registers
are not implemented inside the FPGA, the FPGA does provided buffering of some signals to control proper
local bus timing. These signals include chip select, write enable and ready.
Note:
1) The SRAM should be accessed using 8 bit transfers.
2) The Base1 address is defined by the address assigned to the PCI card by the PCI bridge master
plus the base address configuration of chip select 1 (CS1) of the PCI bridge chip. CS1 base address
is currently configured to 0x20000 and the range limited to 128k bytes (0x1FFFF).
SRAM Address Space
Base1 + 0x00000 through 0x1FFFF.

PCIIO-II, Data Interface For Generation-II PCI Card FPGA Card
Address Map

Package
The PCIIO-II, Data Interface For Generation-II PCI Card FPGA is packaged in an industry standard 208 pin
Plastic Quad Flat Package (PQFP)

FPGA
Registers
(CS0)

A
v
a
i
l
a
b
l
e

L
o
c
a
l

B
u
s

A
d
d
r
e
s
s

S
p
a
c
e

0

Battery
Backed
SRAM
(CS1)
0xFFFFFFF
0
0x00000FF
0x0020000
0x003FFFF

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