In this lecture:

Lecture 6: More Gates and their

Applications
• Exclusive-OR & Exclusive-NOR gates
Dr Pete Sedcole
Department of E&E Engineering
• Functions using logic gates
Imperial College London • Parity circuits – using XOR gates
http://cas.ee.ic.ac.uk/~nps/ • Multiplexer and Demultiplexer circuits
(Floyd 3.6, 6.8 – 6.10)
• The IEEE Standard for logic symbols
(Tocci 4.6 – 4.8, 9.6 – 9.8, 3.15)

E1.2 Digital Electronics 1 6.1 31 October 2008 E1.2 Digital Electronics 1 6.2 31 October 2008

Exclusive-NOR (XNOR)
Exclusive-OR (XOR)

The output of an exclusive- The output of an exclusive-

OR (XOR) function is HIGH NOR (XNOR) function is HIGH
when the inputs are different when the inputs are the same

E1.2 Digital Electronics 1 6.3 31 October 2008 E1.2 Digital Electronics 1 6.4 31 October 2008
 An XNOR gate is
used here to simplify
the circuit
implementation
(4 gates instead of 5)

E1.2 Digital Electronics 1 6.5 31 October 2008 E1.2 Digital Electronics 1 6.6 31 October 2008

Parity generator and checker

Enable/disable circuits

AND and NAND gates can function as enables/disables

E1.2 Digital Electronics 1 6.7 31 October 2008 E1.2 Digital Electronics 1 6.8 31 October 2008
 Design a logic circuit that will allow a data signal (A) to pass through to Merging & inversion circuits
the output only when two control signals (B, C) are both HIGH. If either
control signal is LOW, the output should stay LOW. An OR gate used for a signal merging function:

Data Y A

Data Z B

Design a logic circuit that will allow a data signal (A) to pass through to X
the output only when only one (but not both) of two control signals (B, C)
are HIGH. Otherwise the output should stay HIGH. An XOR gate used for a signal inversion function:
Data

Control

E1.2 Digital Electronics 1 6.9 31 October 2008 E1.2 Digital Electronics 1 6.10 31 October 2008

2-input multiplexer
Multiplexers
• A multiplexer circuit (MUX) is a data selector:
• one of the data inputs is transmitted to the output,
depending on the values of the select inputs

I0 MUX
I1
DATA I2
INPUTS OUTPUT

IN-1

SELECT
E1.2 Digital Electronics 1 6.11 31 October 2008 E1.2 Digital Electronics 1 6.12 31 October 2008
 I0 I1 I2 I3 I4 I5 I6 I7

4-input multiplexer S2
S1 74ALS151
S0 8-input MUX
E

inputs outputs
Z Z
E S2 S1 S0 Z Z
H X X X L H
L L L L I0 I0
L L L H I1 I1
L L H L I2 I2
L L H H I3 I3
L H L L I4 I4
L H L H I5 I5
L H H L I6 I6
L H H H I7 I7
E1.2 Digital Electronics 1 6.13 31 October 2008 E1.2 Digital Electronics 1 6.14 31 October 2008

A MUX used to implement a logic function

f = ABC + ABC + ABC

0 D0
A B C f
0 D1
0 0 0 0
Two 74HC151 0 0 1 0
0 D2
D3
1
(8-input) MUXs 0 1 0 0 1 D4
Y f
0
combined to form 0 1 1 1
0
D5
D6
1 0 0 1
a 16-input MUX 1 D7
1 0 1 0
1 1 0 0 A S2

1 1 1 1
Variables { B
C
S1
S0

E1.2 Digital Electronics 1 6.15 31 October 2008 E1.2 Digital Electronics 1 6.16 31 October 2008
 Another example
Demultiplexers
• A demultiplexer (DEMUX) is a data distributor
• The data input is transmitted to ONE of the data outputs
depending on the values of the select inputs

MUX D0
D1
DATA D2
I DATA
INPUT
OUTPUTS

DN-1

SELECT
E1.2 Digital Electronics 1 6.17 31 October 2008 E1.2 Digital Electronics 1 6.18 31 October 2008

A 1-line-to-4-line DEMUX A 1-line-to-8-line DEMUX

inputs outputs
S2 S1 S0 O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 0 0 0 0 0 0 0 I
0 0 1 0 0 0 0 0 0 I 0
0 1 0 0 0 0 0 0 I 0 0
0 1 1 0 0 0 0 I 0 0 0
1 0 0 0 0 0 I 0 0 0 0
1 0 1 0 0 I 0 0 0 0 0
1 1 0 0 I 0 0 0 0 0 0
1 1 1 I 0 0 0 0 0 0 0

E1.2 Digital Electronics 1 6.19 31 October 2008 E1.2 Digital Electronics 1 6.20 31 October 2008
 • Identical elements can be grouped as an array with
Alternative symbols for gates common control signals
• An example: 4 identical AND gates sharing a single
We have used two forms for drawing gates:
enable signal:
1
IEEE/ANSI standard 1 & >1 =1

EN
Traditional
A1 &
OUT1
B1

A2
• Inputs on the left, outputs on the right B2
OUT2

• The Standard symbols have a qualifier at the top-centre: A3

OUT3
B3
1 Straight through (buffer) A4
OUT4
& AND ≥1 OR B4

=1 XOR ∑ Adder
P Multiplier MUX Multiplexer
E1.2 Digital Electronics 1 6.21 31 October 2008 E1.2 Digital Electronics 1 6.22 31 October 2008

Numbered dependency
Control dependency notation
• Data inputs and outputs can all be numbered
• A number following a control dependency label indicates which
inputs or outputs it affects
Label N am e On assertion ... On de-assertion ... • Example:
EN Enable perm its action prevents action ENABLE G1
G AN D (Gate) perm its action forces output low An array of buffers
INV N2
V OR forces output high perm its action Inputs (1) are ANDed with the
N N OT (Invert) Inverts output N o effect 1
OUT1
ENABLE signal
A1 1 2
S Set forces output high N o effect
Outputs (2) are inverted if INV
R Reset forces output low N o effect
A2 OUT2 signal is asserted (LOW)

E1.2 Digital Electronics 1 6.23 31 October 2008 E1.2 Digital Electronics 1 6.24 31 October 2008
 Active High, Active Low & Asserted
Enable
4-input MUX: IEEE Standard Symbol
EN
Consider some device
Data Inputs
with an “Enable” Outputs
. .
control input . .
. .

MUX
A 0 G0
select inputs
B 1 }
3
• The device is enabled if the Enable input is “asserted” f
0
1
data inputs 2
• What does “asserted” mean? active high 3
– in the active state
– if the signal is labelled EN, then asserted means Enable = 1
– if the signal is labelled EN, then asserted means Enable = 0

active low
E1.2 Digital Electronics 1 6.25 31 October 2008 E1.2 Digital Electronics 1 6.26 31 October 2008