BIST-Based Fault Diagnosis for Read-Only Memories

A Technical Seminar Report Submitted in the Partial Fulfillment of the Requirements for the Award of the Degree of

BACHELOR OF TECHNOLOGY
IN

ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted By P.Vidya Sagar 11885A0424

Under the Guidance of MR. S. RAJENDAR Associate Professor Department of ECE

Department of Electronics and Communication Engineering

VARDHAMAN COLLEGE OF ENGINEERING

(AUTONOMOUS) (Approved by AICTE, Affiliated to JNTUH&Accredited by NBA)

2013 - 14

ACKNOWLEDGEMENTS

The satisfaction that accompanies the successful completion of the task would be put incomplete without the mention of the people who made it possible, whose constant guidance and encouragement crown all the efforts with success. I express my heartfelt thanks to Mr. S. Rajendar, Associate Professor, technical seminar supervisor, for his suggestions in selecting and carrying out the in-depth study of the topic. His valuable guidance, encouragement and critical reviews really helped to shape this report to perfection. I wish to express my deep sense of gratitude to Dr. J. V. R. Ravindra, Head of the Department for his able guidance and useful suggestions, which helped me in completing the technical seminar on time. I also owe my special thanks to our Director Prof. L. V. N. Prasad for his intense support, encouragement and for having provided all the facilities and support. Finally thanks to all my family members and friends for their continuous support and enthusiastic help.

P.Vidya Sagar 11885A0424

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ABSTRACT
This topic presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used to identify permanent failures in embedded readonly memories. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. A built-in self-test (BIST) is a mechanism that permits a machine to test itself.The main purpose of BIST is to reduce the complexity, and thereby decrease the cost and reduce reliance upon external (pattern-

programmed) test equipment. BIST reduces cost in

test-cycle duration,

reduces the complexity of the test/probe setup by reducing the number of I/O signals that must be driven/examined under tester control.

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CONTENTS
Acknowledgements Abstract List of Figures
List of Tables

(ii) (iii) (v)

(vi)

1 2

INTRODUCTION

1 4 4 4 5 6 8 8
10 13 13 16 19

TEST LOGIC ARCHITECHTURE

2.1 Memory Array Organization 2.2 Collection of Diagnostic Data 2.3 Signature Register

3 4

DETERMINISTIC PARTITIONING ROW AND COLUMN SELECTION

4.1 Row Selection 4.2 Column Selection

4.3 Combined Row and Column Selection 4.4 Trellis Selection

5 6

SINGLE CELL FAILURE

APPLICATIONS AND ADVANTAGES

CONCLUSIONS

22

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REFERENCES

23

LIST OF FIGURES

2.1 3.1 4.1 4.2 4.3

4.4 4.5 4.6 4.7 4.8 4.9 5.1 5.2

Memory array architecture and diagnostic environment MIRG-based signature register Row selector Row selector operation Column selector Enhanced column selector Use of three phase shifters Example of column selector Phase shifters for column partitioning
Combined row and column selector

4 6 9 10 11
11 12 12 13 14 14 16 17

Trellis selection Single cell failure diagnosis Simple compactor and its state trajectory

LIST OF TABLES 1.1 4.1 4.2 4.3 4.4

Basic parameters of ROM array
Partition groups for 16-word memory Three faulty rows Column Partitioning

3 9 9 13 15

Correlation in the Trellis Mode

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