Data Sheet

FEATURES
Low power amplifiers provide low noise and low distortion, ideal for xDSL modem receiver Wide supply range: +5 V, 2.5 V to 12 V voltage supply Low power consumption: 4.0 mA/Amp Voltage feedback Ease of Use Lower total noise (insignificant input current noise contribution compared to current feedback amps) Low noise and distortion 2.5 nV/Hz voltage noise @ 100 kHz 1.2 pA/Hz current noise MTPR < 66 dBc (G = +7) SFDR 110 dB @ 200 kHz High speed 130 MHz bandwidth (3 dB), G = +1 Settling time to 0.1%, 68 ns 50 V/s slew rate High output swing: 10.1 V on 12 V supply Low offset voltage, 1.5 mV typical

Dual High Speed, Low Noise Op Amp AD8022

FUNCTIONAL BLOCK DIAGRAM
OUT1 1 IN1 2 +IN1 3 VS 4

AD8022
+ +

8 +VS 7 OUT2 6 IN2 5 +IN2

01053-001

Figure 1.

APPLICATIONS
Receiver for ADSL, VDSL, HDSL, and proprietary xDSL systems Low noise instrumentation front end Ultrasound preamps Active filters 16-bit ADC buffers

GENERAL DESCRIPTIONS
The AD8022 consists of two low noise, high speed, voltage feedback amplifiers. Each amplifier consumes only 4.0 mA of quiescent current, yet has only 2.5 nV/Hz of voltage noise. These dual amplifiers provide wideband, low distortion performance, with high output current optimized for stability when driving capacitive loads. Manufactured on ADIs high voltage generation of XFCB bipolar process, the AD8022 operates on a wide range of supply voltages. The AD8022 is available in both an 8-lead MSOP and an 8-lead SOIC. Fast over voltage recovery and wide bandwidth make the AD8022 ideal as the receive channel front end to an ADSL, VDSL, or proprietary xDSL transceiver design. In an xDSL line interface circuit, the AD8022s op amps can be configured as the differential receiver from the line transformer or as independent active filters.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

100

(pA/ Hz, nV/ Hz)

10

eN (nV/ Hz)
01053-002

iN (pA/ Hz) 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M

10M

Figure 2. Current and Voltage Noise vs. Frequency

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved.

AD8022 TABLE OF CONTENTS

Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 12 Applications..................................................................................... 13

Data Sheet

DMT Modulation and Multitone Power Ratio (MTPR)....... 13 Channel Capacity and SNR....................................................... 13 Power Supply and Decoupling.................................................. 13 Layout Considerations............................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16

REVISION HISTORY
8/11Rev. B to Rev. C Changes to Figure 40 ......................................................................14 Updated Outline Dimensions........................................................16 Changes to Ordering Guide...........................................................16 5/05Rev. A to Rev. B Changes to Format .............................................................Universal Deleted Evaluation Boards Section.............................................. 14 Deleted Generating DMT Section................................................ 14 Changes to Ordering Guide.......................................................... 16 Updated Outline Dimensions....................................................... 16 9/02Rev. 0 to Rev. A Changes to Features ..........................................................................1 Changes to Applications...................................................................1 Changes to Product Description .....................................................1 Changes to Functional Block Diagram ..........................................1 Changes to Figure 1...........................................................................1 Changes to Specifications Table......................................................2 Edits to TPCs 1, 2, 3, 6 ......................................................................5 New TPCs 7, 8....................................................................................6 Edits to TPCs 16, 17, 18....................................................................7 Edits to TPC 19 ..................................................................................8 Edits to TPC 28 ..................................................................................9 Edits to Figure 3...............................................................................11 Edits to Figure 6...............................................................................14 Updated Outline Dimensions........................................................16

Rev. C | Page 2 of 16

Data Sheet SPECIFICATIONS

At 25C, VS = 12 V, RL = 500 , G = +1, TMIN = 40C, TMAX = +85C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth 1 Slew Rate Rise and Fall Time Settling Time 0.1% Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Multitone Input Power Ratio 2 Conditions VOUT = 50 mV p-p VOUT = 50 mV p-p VOUT = 4 V p-p VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p VOUT = 150% of max output voltage, G = +2 VOUT = 2 V p-p fC = 1 MHz fC = 1 MHz G = +7 differential 26 kHz to 132 kHz 144 kHz to 1.1 MHz f = 100 kHz f = 100 kHz Min 110 Typ 130 25 4 50 30 62 200 Max

AD8022

Unit MHz MHz MHz V/s ns ns ns

40

95 100 67.2 66 2.5 1.2 1.5 6 7.25 5.0 7.5

dBc dBc dBc dBc nV/Hz pA/Hz mV mV nA A A dB k pF V dB V V mA mA pF 13.0 5.5 6.1 +85 V mA/Amp mA/Amp dB C

Voltage Noise (RTI) Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Current Input Bias Current

TMIN to TMAX 120 2.5 TMIN to TMAX Open-Loop Gain INPUT CHARACTERISTICS Input Resistance (Differential) Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Output Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
1 2

72 20 0.7 11.25 to +11.75 98 10.1 10.6 55 100 75 +4.5 4.0 TMIN to TMAX VS = 5V to 12 V 40 80

VCM = 3 V RL = 500 RL = 2 k G = +1, RL = 150 , dc error = 1% RS = 0 , <3 dB of peaking

FPBW = Slew Rate/(2 VPEAK). Multitone testing performed with 800 mV rms across a 500 load at Point A and Point B on the circuit of Figure 23.

Rev. C | Page 3 of 16

AD8022
At 25C, VS = 2.5 V, RL = 500 , G = +1, TMIN = 40C, TMAX = +85C, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth 1 Slew Rate Rise and Fall Time Settling Time 0.1% Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Multitone Input Power Ratio 2 Conditions VOUT = 50 mV p-p VOUT = 50 mV p-p VOUT = 3 V p-p VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p, G = +2 VOUT = 2 V p-p VOUT = 150% of max output voltage, G = +2 VOUT = 2 V p-p fC = 1 MHz fC = 1 MHz G = +7 differential, VS = 6 V 26 kHz to 132 kHz 144 kHz to 1.1 MHz f = 100 kHz f = 100 kHz Min 100 Typ 120 22 4 42 40 75 225

Data Sheet

Max

Unit MHz MHz MHz V/s ns ns ns

30

77.5 94 69 66.7 2.3 1 0.8 5.0 6.25 5.0 7.5

dBc dBc dBc dBc nV/Hz pA/Hz mV mV nA A A dB k pF V dB V mA mA pF 13.0 4.25 4.4 +85 V mA/Amp mA/Amp dB C

Voltage Noise (RTI) Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Current Input Bias Current

TMIN to TMAX 65 2.0 TMIN to TMAX Open-Loop Gain INPUT CHARACTERISTICS Input Resistance (Differential) Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short-Circuit Output Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
1 2

64 20 0.7 1.83 to +2.0 98 1.38 to +1.48 32 80 75 +4.5 3.5 TMIN to TMAX VS = 1 V 40 86

VCM = 2.5 V, VS = 5.0 V RL = 500 G = +1, RL = 100 , dc error = 1% RS = 0 , <3 dB of peaking

FPBW = Slew Rate/(2 VPEAK). Multitone testing performed with 800 mV rms across a 500 load at Point A and Point B on the circuit of Figure 23.

Rev. C | Page 4 of 16

Data Sheet ABSOLUTE MAXIMUM RATINGS

Table 3.
Parameter Supply Voltage (+VS to VS) Internal Power Dissipation 1 8-Lead SOIC (R) 8-Lead MSOP (RM) Input Voltage (Common Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range (A Grade) Lead Temperature Range (Soldering 10 sec)
1

AD8022

Rating 26.4 V 1.6 W 1.2 W VS 0.8 V Observe Power Derating Curves 65C to +125C 40C to +85C 300C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8022 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8022 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0 TJ = 150C

Specification is for the device in free air: 8-Lead SOIC: JA = 160C/W. 8-Lead MSOP: JA = 200C/W.

MAXIMUM POWER DISSIPATION (W)

1.5 8-LEAD SOIC PACKAGE

1.0

8-LEAD MSOP 0.5

01053-003

0 50 40 30 20 10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (C)

70

80

90

Figure 3. Maximum Power Dissipation vs. Temperature

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 5 of 16

AD8022 TYPICAL PERFORMANCE CHARACTERISTICS

5 4 3 2 1
(dB)

Data Sheet
5 402 4 VIN = 0.05V p-p VIN = 0.2V p-p

RF 50 VOUT 50

VIN 50

RF = 715

3 2 1
(dB)

VIN 50

453

VOUT 56.2

0 1 2 3 4 5 0.1 1 10 FREQUENCY (MHz) 100 RF = 402 RF = 0

01053-004

0 1 2 3 4 5 0.1 VIN = 0.8V p-p VIN = 0.4V p-p 1 10 FREQUENCY (MHz) 100
01053-007

VIN = 2.0V p-p

500

500

Figure 4. Frequency Response vs. RF, G = +1, VS = 12 V, VIN = 63 mV p-p

0.4 0.3 0.2 0.1 0
(dB)

Figure 7. Frequency Response vs. Signal Level, VS = 12 V, G = +1

5 4 VIN 50 CL 715 715 RS VOUT 56.2 50pF

G = +2 RL = 500
FREQUENCY RESPONCE (dB)

453

3 2 1 0 1 2

0.1 0.2 0.3 0.4 0.5 0.6 100k 1M

30pF 0pF

12V
5.0V
2.5V

3 4 5 0.1 1 10 FREQUENCY (kHz) 100

01053-008

10M FREQUENCY (Hz)

100M

01053-005

500

Figure 5. Fine-Scale Gain Flatness vs. Frequency, G = +2

0.4 0.3 0.2 G = +2 RL = 500

Figure 8. Frequency Response vs. Capacitive Load; CL = 0 pF and 50 pF; RS = 0

140 120 100 G = +1, RF = 402

0
(dB)

FREQUENCY (MHz)

0.1

80 60 40 20 0 G = +2, RF = 715

0.1 0.2 0.3 0.4 0.5 0.6 100k 1M 10M FREQUENCY (Hz) 12V 5.0V 2.5V
01053-006

100M

6 8 10 SUPPLY VOLTAGE (V)

12

14

Figure 6. Fine-Scale Gain Flatness vs. Frequency, G = +1

Figure 9. Bandwidth vs. Supply, RL = 500 , VIN = 200 mV p-p

Rev. C | Page 6 of 16

01053-009

Data Sheet
80 70 60 50
100 90

AD8022
100mV 100ns INPUT

GAIN (dB)

40 30 20 10
10

0 10 5k 10k 100k 1M 10M FREQUENCY (Hz) 100M

01053-010

0%

OUTPUT
01053-013

100mV

500M

Figure 10. Open-Loop Gain vs. Frequency

Figure 13. Noninverting Small Signal Pulse Response, RL = 500 , VS = 2.5 V, G = +1, RF = 0
2.00V
100

180

100ns INPUT

FREQUENCY (Degrees)

90

10 0%

OUTPUT
01053-014

180 5k 10k 100k 1M 10M FREQUENCY (Hz) 100M

01053-011

2.00V

500M

Figure 11. Open-Loop Phase vs. Frequency

Figure 14. Noninverting Large Signal Pulse Response, RL = 500 , VS = 12 V, G = +1, RF = 0

1.00V INPUT
100 90

100mV
100 90

100ns

100ns INPUT

10 0%

10

OUTPUT
01053-012

0%

OUTPUT
01053-015

100mV

1.00V

Figure 12. Noninverting Small Signal Pulse Response, RL = 500 , VS = 12 V, G = +1, RF = 0

Figure 15. Noninverting Large Signal Pulse Response, RL = 500 , VS = 2.5 V, G = +1, RF = 0

Rev. C | Page 7 of 16

AD8022
0.4 0.3 0.2 50 60

Data Sheet

HARMONIC DISTORTION (dB)

70 80 90 100 110 120 130 1k 3RD 2ND

01053-019

SETTLING ERROR (%)

0.1 0 0.1 0.2

+0.1%

0.1%

0.4

20

40

60 TIME (ns)

80

100

120

01053-016

0.3

10k

100k FREQUENCY (Hz)

1M

10M

Figure 16. Settling Time to 0.1%, VS = 12 V, Step Size = 2 V p-p, G = +2, RL = 500
0.4 0.3 0.2 50 60

Figure 19. Distortion vs. Frequency, VS = 12 V, RL = 500 , RF = 0 , VOUT = 2 V p-p, G = +1

HARMONIC DISTORTION (dB)

70 80 90 100 110
01053-020

SETTLING ERROR (%)

0.1 0 0.1 0.2

+0.1%

2ND 3RD

0.1%

01053-017

0.3 0.4

120 130 1k

20

40

60 TIME (ns)

80

100

120

10k

100k FREQUENCY (Hz)

1M

10M

Figure 17. Settling Time to 0.1%, VS = 2.5 V, Step Size = 2 V p-p, G = +2, RL = 500
70 60 20 30

Figure 20. Distortion vs. Frequency, VS = 2.5 V, RL = 500 , RF = 0 , VOUT = 2 V p-p, G = +1

HARMONIC DISTORTION (dBc)

NEGATIVE EDGE 50

40 50 60 70 80 90 100 120 2ND 3RD

SLEW RATE (V/s)

POSITIVE EDGE 40 30 20 10 0 2.5

01053-018

4.5

6.5 8.5 SUPPLY VOLTAGE (V)

10.5

12.5

10 15 OUTPUT VOLTAGE (V p-p)

20

Figure 18. Slew Rate vs. Supply Voltage, G = +2

Figure 21. Distortion vs. Output Voltage, VS = 12 V, G = +2, f = 1 MHz, RL = 500 , RF = 715

Rev. C | Page 8 of 16

01053-021

Data Sheet
0

AD8022

20

HARMONIC DISTORTION (dBc)

10dB/DIV (dBc)

40

67.2dBc

60 2ND

80

120

01053-022

0.5

1.0 1.5 2.0 OUTPUT VOLTAGE (V p-p)

2.5

3.0

102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4 FREQUENCY (kHz)

Figure 22. Distortion vs. Output Voltage, VS = 2.5 V, G = +1, f = 1 MHz, RL = 500 , RF = 0
+V

Figure 25. Multitone Power Ratio: VS = 12 V, RL = 500 , Full Rate ADSL (DMT), Upstream

AD8022
10dB/DIV (dBc)

1/2

715 250 715 500

66.7dBc

1/2

Figure 23. Multitone Power Ratio Test Circuit

01053-023

549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY (kHz)

Figure 26. Multitone Power Ratio: VS = 6 V, RL = 500 , Full Rate ADSL (DMT), Downstream

10dB/DIV (dBc)

66.0dBc

10dB/DIV (dBc)

69.0dBc

01053-024

549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY (kHz)

102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4 FREQUENCY (kHz)

Figure 24. Multitone Power Ratio: VS = 12 V, RL = 500 , Full Rate ADSL (DMT), Downstream

Figure 27. Multitone Power Ratio: VS = 6 V, RL = 500 , Full Rate ADSL (DMT), Upstream

Rev. C | Page 9 of 16

01053-027

01053-026

AD8022

01053-025

100

3RD

AD8022
0 SIDE A 0.5
VOLTAGE OFFSET (mV)

Data Sheet
50 1k 60 SIDE B SIDE A SIDE B VS = 2.5V 56.7
CMRR (dB)

1k 50

1k 1k

1.0

70

1.5 VS = +12V 2.0

01053-028

80

90
01053-031

2.5 60

40

20

20 40 60 80 TEMPERATURE (C)

100

120

140

100 1k

10k

100k FREQUENCY Hz)

1M

Figure 28. Voltage Offset vs. Temperature

4.5 4.0
TOTAL SUPPLY CURRENT (mA)

Figure 31. CMRR vs. Frequency

8.5 8.0 VS = 12V 7.5 7.0 6.5 VS = 2.5V 6.0 5.5 5.0 50

3.5
BIAS CURRENT (A)

3.0 2.5 2.0 1.5 1.0

VS = 12V

VS = 2.5V

01053-029

0 60

40

20

20 40 60 80 TEMPERATURE (C)

100

120

140

50 TEMPERATURE (C)

100

150

Figure 29. Bias Current vs. Temperature

4 3 2 1
VOS (mV)

Figure 32. Total Supply Current vs. Temperature

0

1k
POWER SUPPLY REJECTION (dB)

VIN

1k 1k 1k 500

VOUT

10 20 30 PSRR 40 50 60 70 80 90 100 10k 100k 1M FREQUENCY (Hz) 10M

01053-033

VS = 2.5V

0 1 2
01053-030

+PSRR

3 4 12.5 10.0 7.5

VS = 12V

5.0

2.5

0 VCM (V)

2.5

5.0

7.5

10.0

12.5

100M

Figure 30. Voltage Offset vs. Input Common-Mode Voltage

Figure 33. Power Supply Rejection vs. Frequency VS = 12 V

Rev. C | Page 10 of 16

01053-032

0.5

Data Sheet
0 10
POWER SUPPLY REJECTION (dB)

AD8022
0 10 20
CROSSTALK (dB)

20 30 40 50 60 70 80
01053-034

PSRR

30 40 50 60 70 80 90 100 100k 1M 10M FREQUENCY (Hz)

01053-036

SIDE A OUT

+PSRR

SIDE B OUT

90 100 10k 100k 1M FREQUENCY (Hz) 10M

100M

100M

Figure 34. Power Supply Rejection vs. Frequency VS = 2.5 V

0 10 20
OUTPUT IMPEDANCE ()

Figure 36. Output-to-Output Crosstalk vs. Frequency, VS = 2.5 V

100 31 10 3.16 1 0.316 0.1 0.0316
01053-035 01053-037

30
CROSSTALK (dB)

40 50 60 70 80 90 100 10k 100k

SIDE A OUT

SIDE B OUT

1M FREQUENCY (Hz)

10M

100M

30k

100k

1M 10M FREQUENCY (Hz)

100M

500M

Figure 35. Output-to-Output Crosstalk vs. Frequency, VS = 12 V

Figure 37. Output Impedance vs. Frequency, VS = 12 V

Rev. C | Page 11 of 16

AD8022 THEORY OF OPERATION

The AD8022 is a voltage-feedback op amp designed especially for ADSL or other applications requiring very low voltage and current noise along with low supply current, low distortion, and ease of use. The AD8022 is fabricated on Analog Devices proprietary eXtra-Fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features enable the construction of high frequency, low distortion amplifiers with low supply currents.
+VS

Data Sheet

As shown in Figure 38, the AD8022 input stage consists of an NPN differential pair in which each transistor operates a 300 A collector current. This gives the input devices a high transconductance and therefore gives the AD8022 a low input noise of 2.5 nV/Hz @ 100 kHz. The input stage drives a folded cascode that consists of a pair of PNP transistors. These PNPs then drive a current mirror that provides a differential input to single-ended output conversion. The output stage provides a high current gain of 10,000 so that the AD8022 can maintain a high dc open-loop gain, even into low load impedances.

15 +IN 15 OUTPUT

7.5pF IN 600A

VS

Figure 38. Simplified Schematic

Rev. C | Page 12 of 16

01053-038

Data Sheet APPLICATIONS

The low noise AD8022 dual xDSL receiver amplifier is specifically designed for the dual differential receiver amplifier function within xDSL transceiver hybrids, as well as other low noise amplifier applications. The AD8022 can be used in receiving modulated signals including discrete multitone (DMT) on either end of the subscriber loop. Communication systems designers can be challenged when designing an xDSL modem transceiver hybrid capable of receiving the smallest signals embedded in noise that inherently exists on twisted-pair phone lines. Noise sources include near-end crosstalk (NEXT), far-end crosstalk (FEXT), background, and impulse noise, all of which are fed, to some degree, into the receiver front end. Based on a Bellcore noise survey, the background noise level for typical twisted-pair telephone loops is 140 dBm/Hz or 31 nV/Hz. It is therefore important to minimize the noise added by the receiver amplifiers to preserve as much signal-tonoise ratio (SNR) as possible. With careful transceiver hybrid design, using the AD8022 dual, low noise, receiver amplifier to maintain power density levels lower than 140 dBm/Hz in ADSL modems is easily achieved.

AD8022
empty frequency bin. MTPR, sometimes referred to as the empty bin test, is typically expressed in dBc, similar to expressing the relative difference between single tone fundamentals and second or third harmonic distortion components. Measurements of MTPR are typically made at the output of the receiver directly across the differential load. Other components aside, the receiver function of an ADSL transceiver hybrid is affected by the turns ratio of the selected transformers within the hybrid design. Since a transformer reflects the secondary voltage back to the primary side by the inverse of the turns ratio, 1/N, increasing the turns ratio on the secondary side reduces the voltage across the primary side inputs of the differential receiver. Increasing the turns ratio of the transformers can inadvertently cause a reduction of the SNR by reducing the received signal strength.

CHANNEL CAPACITY AND SNR

The efficiency of an ADSL system in delivering the digital data embedded in the DMT signals can be compromised when the noise power of the transmission system increases. Figure 39 shows the relationship between SNR and the relative maximum number of bits per tone or subband while maintaining a bit error rate at 107 errors per second.
60

DMT MODULATION AND MULTITONE POWER RATIO (MTPR)

ADSL systems rely on discrete multitone DMT modulation to carry digital data over phone lines. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which is uniformly separated in frequency. (See Figure 24 to Figure 27 for MTPR results while the AD8022 receives DMT driving 800 mV rms across a 500 differential load.) A uniquely encoded quadrature amplitude modulation (QAM) signal occurs at the center frequency of each subband or tone. Difficulties exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s) from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. Conventional methods of expressing the output signal integrity of line receivers, such as spurious-free dynamic range (SFDR), single tone harmonic distortion (THD), twotone intermodulation distortion (IMD), and third-order intercept (IP3), become significantly less meaningful when amplifiers are required to process DMT and other heavily modulated waveforms. A typical xDSL downstream DMT signal can contain as many as 256 carriers (subbands or tones) of QAM signals. MTPR is the relative difference between the measured power in a typical subband (at one tone or carrier) vs. the power at another subband specifically selected to contain no QAM data. In other words, a selected subband (or tone) remains open or void of intentional power (without a QAM signal) yielding an

50

40
SNR (dB)

30

20

10
01053-039

5 BITS/TONE

10

15

Figure 39. ADSL DMT SNR vs. Bits/Tone

POWER SUPPLY AND DECOUPLING

The AD8022 should be powered with a good quality (that is, low noise) dual supply of 12 V for the best overall performance. The AD8022 circuit also functions at voltages lower than 12 V. Careful attention must be paid to decoupling the power supply pins. A pair of 10 F capacitors located in near proximity to the AD8022 is required to provide good decoupling for lower frequency signals. In addition, 0.1 F decoupling capacitors should be located as close to each of the power supply pins as is physically possible.

Rev. C | Page 13 of 16

AD8022

DVDD B1 TP4 + TP5 J1 TP1 A R15 1 49.9 U1 AD9754 C7 1F AVDD C8 0.1F

A A A

DGND B2 TP19 TP18 +

A

AVDD B3 TP6 CLK JP1 B 2 3 TP7

AGND B4

AVEE B5

AVCC B6

TP3

TP2

+ C4 10F EXTCLK DVDD R3 16 PIN DIP RES PK

1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10

C3 10F DVDD R5
1

+ C5 10F C6 10F

R1

R7

P1

2 3 4 5 6 7 8 9 10

C9 0.1F

TP8

AVDD OUT1 OUT2

C19 C1 C2 C25 C26 C27 C27 C29 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9

16 PIN DIP RES PK

A

2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CLOCK DVDD DCOM NC AVDD COMP2 IOUTA IOUTB ACOM COMP1 FS ADJ REFIO REFLO SLEEP 28 27 26 25 24 23 22 21 20 19 18 17 16 15

TP13 TP11 AVDD C11 0.1F 1 2 PDIN J2 JP2

A

TP10

TP9

CT1
A

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C30 C31 C32 C33 C34 C35 C36 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 10 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 2 1 1 1 10 9 8 7 6 5 4 3 2

1 3 5 7 9 11 TO TEK 13 15 AWG 17 2021 19 21 23 25 27 29 31 33 35 37 39

R16 2k R 20k TP14 3

A A

C10 0.1F JP4

01053-040
A

Figure 40. DMT Signal Generator Schematic

TP12 R6 R2 DVDD R6 DVDD R17 49.9 AVCC 0.1F 1F
A

Rev. C | Page 14 of 16
10k
A

10 9 8 7 6 5 4 3 2

R2

AVDD

J3 AD8022 750 226 750

A

OUT1 249

C12 22pF

49.9

DIFFERENTIAL DMT OUTPUTS 249

A

J4 1F 0.1F 10k
A

OUT2

AD8022

C13 22pF AVEE

49.9

Data Sheet

Data Sheet
6800pF 5% NPO 191 1% 243 1% 12V 3 2 8200pF 10% COMMONMODE VOLTAGE SIGNAL CM LEVEL 0.1F 16V 10% X7R 422 1% 0.1F 50V 5% NPO 6 7 VIN 5 191 1% 243 1% 4 VOUT 249 1% 8

AD8022
LAYOUT CONSIDERATIONS
AD8022
1 +VOUT

+VIN

8200pF 10%

249 1%

AD8022
01053-041

6800pF 5% NPO

Figure 41. Differential Input Sallen-Key Filter Using AD8022 on Single Supply, +12 V
7.5 2.5 2.5 7.5 12.5
(dB)

As is the case with all high speed amplifiers, careful attention to printed circuit board layout details prevent associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. Removing the ground plane from the area near the input signal lines reduces stray capacitance. Chip capacitors should be used for supply bypassing. One end of the capacitor should be connected to the ground plane, and the other should be connected no more than 1/8 inch away from each supply pin. An additional large (0.47 F to 10 F) tantalum capacitor should be connected in parallel, although not necessarily as close, in order to supply current for fast, large signal changes at the AD8022 output. Signal lines connecting the feedback and gain resistors should be as short as possible, minimizing the inductance and stray capacitance associated with these traces. Locate termination resistors and loads as close as possible to the input(s) and output, respectively. Adhere to stripline design techniques for long signal traces (greater than about 1 inch). Following these generic guidelines improves the performance of the AD8022 in all applications.

17.5 22.5 27.5 32.5 37.5 42.5 10k 100k 1M FREQUENCY (Hz)
01053-042

10M

Figure 42. Frequency Response of Sallen-Key Filter

Rev. C | Page 15 of 16

AD8022 OUTLINE DIMENSIONS

5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497)
8 1 5 4

Data Sheet

6.20 (0.2441) 5.80 (0.2284)

1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE

1.75 (0.0688) 1.35 (0.0532)

0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)

45

0.51 (0.0201) 0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 43. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8)Dimensions shown in millimeters and (inches)
3.20 3.00 2.80

3.20 3.00 2.80 PIN 1 IDENTIFIER

5.15 4.90 4.65

0.65 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.40 0.25 15 MAX 1.10 MAX 0.23 0.09 0.80 0.55 0.40
10-07-2009-B

6 0

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 44. 8-Lead Mini Small Outline Package [MSOP] (RM-8)Dimensions shown in millimeters

ORDERING GUIDE
Model 1 AD8022AR AD8022ARZ AD8022ARZ-REEL AD8022ARZ-REEL7 AD8022ARMZ AD8022ARMZ-REEL AD8022ARMZ-REEL7 AD8022ARM-EBZ AD8022AR-EBZ
1

Temperature Range 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C

Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board Evaluation Board

012407-A

Package Option R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8

Z = RoHS Compliant Part.

2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01053-0-8/11(C)

Rev. C | Page 16 of 16