PROJECT TITLE: Flash ADC Design Student Names: Nagaraj Hegde, Raed Suftah _________________________________________________________________

Presentation Average Grade Final Report

Introduction/Executive Summary Design Approach

GRADE /10 GRADE

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Schematic Layouts Entire System Schematic Layout Error log sheet DRC, Well Check, etc All blocks are integrated Simulations are performed Input/Output identified in table or figure forms for proper operation

Simulation Results /25

System Integration

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Conclusion/Summary Mention number of transistors References Appendix- Spice Code DRC Checks, Layout vs. Schematic Checks, etc. for verification of design Total Report Grade

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Executive summary:
The process of taking an analog voltage, VAnalog, and converting it to a digital signal can be accomplished in several ways. One way is by means of parallel encoding (also known as flash converting). In this method, several comparators are set up, each at a different voltage reference level (VA, VB, VC, VD) with their outputs (C1, C2, C3). The comparators operate in such a way that, if the analog input is greater than the reference node voltage, the comparator output will go high (approximately +Vcc), represented by a logic 1. If the analog input is less than the reference node voltage, the comparator output will go low (approximately Vcc), represented by logic 0. Electric VLSI CAD tool with 350 nm CMOS technology was used to design the circuit in schematics and layout and LTSpice was used to simulate the design. A 3 bit flash ADC with conversion timing of 27ns was designed. The document below explains the phases of design in detail.

Part One: Resistor divider network

The reference voltages are typically generated through the use of a resistor ladder. The resistor ladder is connected between positive and negative reference voltages Vref+ and Vref. The nodes on the reference ladder are connected to the comparators in the flash ADC depicts a resistor reference ladder. Variations in resistor value along the ladder will result in incorrect reference voltages. Figure1 below explains the resistor divider network.

Figure 1: resistor reference ladder.

Part Two: Comparator

A comparator is a circuit that has binary output. Ideally its output is defined as

A comparator compares the voltages at the + and inputs. If the + input is at a higher voltage than the input the comparator output will be high. If the input is at a higher voltage than the + input the comparator output will be low. Below Figure2 is a top level schematic of a comparator.

Figure 2: Comparator Design

 Comparator Schematic on Electric

As per [1] we got the transistor scaling and accordingly designed the schematic and layout. Below Figure 3 is the schematic design of the comparator circuit. There are 8 transistors in the circuit. The resistance value is 175000 ohm.

Figure 3: Comparator Schematic

When we ran the LT Spice simulation for the above circuit we got the below response as in Figure4. The blue line is non-inverting input for the comparator and red line is a sinusoidal input to inverting terminal. As can be seen, the green line, which is the output of the comparator, is behaving as expected.

Figure 4: Comparator Schematic Simulation

Below Figure 5 is the layout for the Comparator as per the schematic design.

Figure 5: Comparator Layout

When the layout was simulated, it resulted in below figure 6. As before, the behavior is as expected. After checking the simulated outputs, the compensation Capacitance was fixed to be 100fF. And 100fF of Load capacitance is also added. These were designed using Poly1 and Poly2 as parallel plate capacitor resulting in C=A/d where A is the Area of the plates and d is the distance between plates. The resistors were designed using N-Poly resistor.

Part three: 8:3 Priority Encoder

Figure 6: Comparator Layout Simulation

The priority encoder is a multi-input device, which tells the binary number of the input, having the highest priority. In our project we have used a 8:3 priority encoder, which means that there are 8 inputs going out to be 3 outputs. Since an n bit flash ADC will use 2n-1 comparators, in our design we will be needing 7 comparators. This means we need to use only 7 inputs from the encoder and the bit 0 is not used. Below figure 7 is the schematic of priority encoder which works as per the below equations:

Figure 7: Schematic of Priority Encoder

The Boxes are all logical AND, OR, NOT gates as per the above Equations. The total transistor Count for this circuit is 39.

in the above circuit, the encoder will work like if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. The priority encoder is designed into detect the position of the leading one. Below figure 8 is the layout for priority encoder. 5 metal layers were used to reduce the complexity of routing.

Figure 8: Layout of the priority Encode

Figure 8. Layout of 8:3 priority encoder.

Part four: System Integration

In this part we will connect the previous parts together to make one system: Flash AnalogDigital converter. Below figure 9 is the schematic design of 3 bit ADC. As discussed before this has 7 comparators, and a priority encoder which encodes the output from the comparators stage to 3 bit code.

Figure 9: Schematic of Flash ADC

When the schematic was simulated the response is as in Figure 10 for a sinusoidal input. As we see, the behavior is as expected and the ADC convers the analog values to 3 bit digital value.

Figure 10: Simulation of ADC schematic.

Layout was designed routing all the parts together as per schematic design and it looked as below in Figure 11. Along with comparator and priority encoder, resistor divider network with 8 resistors of 1 K ohm each where designed used n-poly resistor.

Figure 10: Layout Of flash ADC

When we performed DRC, it resulted in below Figure 12:

Figure 12: DRC of the ADC layout

We simulated the design and below are the output waveforms of bit0, bit1 and bit 2 respectively of ADC with respect to the input sinusoid and which can be very easily verified to be correct.

Figure 13: Out put bits (bit0 top, bit1 middle and bit2 bottom) of ADC with a sinusoidal input. The combined waveform helps to see the number of stages generated for full scale input (the design is 3 V VDD, -3V VSS). Sinusoidal input having mean 1.5 V and amplitude 3V and frequency 1KHz is used as input so as to capture all possible responses. It can be easily verified from Figure 14 that the ADC produces 8 (23) , stages for the input applied as it varies from 0 to 3V.

Figure 14: ADC layout simulation. Problems faced: During the full system layout design, there was a comparator left without a global VDD connection and this resulted in spurious behavior of ADC output bit 0. By backtracking the problem it was solved. Findings: Rise time of the Output bit was found to be 0.6us for a sinusoidal input as in Figure 15:

Figure 15: Rise time calculation for sine wave input Fall time was found to be ~0.5us for a sinusoidal input as per Figure 16 below:

Figure 16: Fall time calculation for sine wave input

To find the conversion timings (time it takes for all the output bits to be stable for a given input), the system was tested with a pulse and conversion time was found to be ~30ns for this case as per

Figure 17: Conversion time for a pulse. And this agreed with the fact that, after 3MHz input frequency(corresponding to 30ns time), the out put of the ADC starts getting distorted as seen below:

Figure 18: Distortion after 3MHz input sinusoidal frequency, While we see little/no distortion at 1 MHz as in Figure 19:

Figure 19: Response of ADC for 1MHz input sinusoid.

Conclusion:
We designed a Flash ADC with below specifications: No of bits Conversion timing for pulse input Rise time for sinusoidal input Fall time for sinusoidal input Total Number of transistors Operating Range in Hz 3 30ns 0.6us 0.5us 135 0 3MHz

This was a very good learning experience in designing mixed signal systems. References: 1. Understanding Flash ADCs Maxim Semi http://www.maximintegrated.com/appnotes/index.mvp/id/810 2. http://webpages.eng.wayne.edu/cadence/ECE7570/doc/comparator.pdf 3. http://coel.ecgf.uakron.edu/grover/web/ee263/slides/Chapter%2006B.pdf 4. Design and implementation of flash ADC http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5423784 5. http://www.ewh.ieee.org/tc/csc/europe/newsforum/pdf/2010-ASC/ST192.pdf 6. http://www.computer.org/portal/web/csdl/doi?doc=doi/10.1109/ICONS.2008.68 7. http://www.ewh.ieee.org/tc/csc/europe/newsforum/pdf/IMS2011-03.pdf

Appendix 1. Spice Code for the layout: *** SPICE deck for cell adc_test{lay} from library Final-Prj *** Created on Sat Dec 01, 2012 13:01:30 *** Last revised on Sat Dec 01, 2012 14:08:08 *** Written on Sat Dec 01, 2012 14:08:31 by Electric VLSI Design System, *version 9.03 *** Layout tech: mocmos, foundry MOSIS *** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF *CMOS/BULK-NWELL (PRELIMINARY PARAMETERS) +ITL5=0 RELTOL=0.01 ABSTOL=500PA VNTOL=500UV LVLTIM=2 +LVLCOD=1 .MODEL N NMOS LEVEL=1 .MODEL P PMOS LEVEL=1 .MODEL DIFFCAP D CJO=.2MF/M^2 *** SUBCIRCUIT and2_1x FROM CELL Final-Prj:and2_1x{lay} .SUBCKT and2_1x A B Y gnd vdd Mnmos@0 Y net@5 gnd nmos@0_n-trans-well N L=1.75U W=1.75U AS=14.088P +AD=12.862P PS=19.6U PD=14.7U Mnmos@1 net@10 B gnd nmos@1_n-trans-well N L=1.75U W=1.75U AS=14.088P +AD=5.206P PS=19.6U PD=7.7U Mnmos@2 net@5 A net@10 nmos@2_n-trans-well N L=1.75U W=1.75U AS=5.206P +AD=14.904P PS=7.7U PD=15.867U Mpmos@0 Y net@5 vdd pmos@0_p-trans-well P L=1.75U W=5.25U AS=23.888P +AD=12.862P PS=25.667U PD=14.7U Mpmos@1 net@5 A vdd pmos@1_p-trans-well P L=1.75U W=5.25U AS=23.888P +AD=14.904P PS=25.667U PD=15.867U Mpmos@2 vdd B net@5 pmos@2_p-trans-well P L=1.75U W=5.25U AS=14.904P +AD=23.888P PS=15.867U PD=25.667U .ENDS and2_1x *** SUBCIRCUIT and3_1x FROM CELL Final-Prj:and3_1x{lay} .SUBCKT and3_1x A B C Y gnd vdd Mnmos@8 net@309 A gnd nmos@8_n-trans-well N L=1.75U W=1.75U AS=14.088P +AD=5.206P PS=19.6U PD=7.7U Mnmos@9 net@310 B net@309 nmos@9_n-trans-well N L=1.75U W=1.75U AS=5.206P +AD=5.206P PS=7.7U PD=7.7U Mnmos@10 net@291 C net@310 nmos@10_n-trans-well N L=1.75U W=1.75U AS=5.206P

+AD=14.241P PS=7.7U PD=12.95U Mnmos@11 Y net@291 gnd nmos@11_n-trans-well N L=1.75U W=1.75U AS=14.088P +AD=12.862P PS=19.6U PD=14.7U Mpmos@8 net@291 A vdd pmos@8_p-trans-well P L=1.75U W=5.25U AS=23.428P +AD=14.241P PS=25.55U PD=12.95U Mpmos@9 Y net@291 vdd pmos@9_p-trans-well P L=1.75U W=5.25U AS=23.428P +AD=12.862P PS=25.55U PD=14.7U Mpmos@10 net@291 C vdd pmos@10_p-trans-well P L=1.75U W=5.25U AS=23.428P +AD=14.241P PS=25.55U PD=12.95U Mpmos@11 vdd B net@291 pmos@11_p-trans-well P L=1.75U W=5.25U AS=14.241P +AD=23.428P PS=12.95U PD=25.55U .ENDS and3_1x *** SUBCIRCUIT and4_1x FROM CELL Final-Prj:and4_1x{lay} .SUBCKT and4_1x A B C D Y gnd vdd Mnmos@13 Y net@482 gnd nmos@13_n-trans-well N L=1.75U W=1.75U AS=14.088P +AD=12.862P PS=19.6U PD=14.7U Mnmos@14 net@499 A gnd nmos@14_n-trans-well N L=1.75U W=1.75U AS=14.088P +AD=5.206P PS=19.6U PD=7.7U Mnmos@15 net@500 B net@499 nmos@15_n-trans-well N L=1.75U W=1.75U AS=5.206P +AD=5.206P PS=7.7U PD=7.7U Mnmos@16 net@501 C net@500 nmos@16_n-trans-well N L=1.75U W=1.75U AS=5.206P +AD=5.206P PS=7.7U PD=7.7U Mnmos@17 net@482 D net@501 nmos@17_n-trans-well N L=1.75U W=1.75U AS=5.206P +AD=15.19P PS=7.7U PD=14U Mpmos@12 Y net@482 vdd pmos@12_p-trans-well P L=1.75U W=5.25U AS=21.805P +AD=12.862P PS=22.68U PD=14.7U Mpmos@13 net@482 B vdd pmos@13_p-trans-well P L=1.75U W=5.25U AS=21.805P +AD=15.19P PS=22.68U PD=14U Mpmos@14 net@482 D vdd pmos@14_p-trans-well P L=1.75U W=5.25U AS=21.805P +AD=15.19P PS=22.68U PD=14U Mpmos@15 vdd C net@482 pmos@15_p-trans-well P L=1.75U W=5.25U AS=15.19P +AD=21.805P PS=14U PD=22.68U Mpmos@16 vdd A net@482 pmos@16_p-trans-well P L=1.75U W=5.25U AS=15.19P +AD=21.805P PS=14U PD=22.68U .ENDS and4_1x *** SUBCIRCUIT not FROM CELL Final-Prj:not{lay} .SUBCKT not A Y gnd vdd Mnmos@0 Y A gnd nmos@0_n-trans-well N L=1.75U W=1.75U AS=21.438P AD=12.862P +PS=28U PD=14.7U

Mpmos@0 Y A vdd pmos@0_p-trans-well P L=1.75U W=5.25U AS=32.769P AD=12.862P +PS=40.6U PD=14.7U .ENDS not *** SUBCIRCUIT or4 FROM CELL Final-Prj:or4;1{lay} .SUBCKT or4 A B C D Y gnd vdd Mnmos@4 gnd A net@57 nmos@4_n-trans-well N L=1.75U W=1.75U AS=8.575P +AD=8.452P PS=11.2U PD=11.76U Mnmos@5 net@57 B gnd nmos@5_n-trans-well N L=1.75U W=1.75U AS=8.452P +AD=8.575P PS=11.76U PD=11.2U Mnmos@6 gnd C net@57 nmos@6_n-trans-well N L=1.75U W=1.75U AS=8.575P +AD=8.452P PS=11.2U PD=11.76U Mnmos@7 net@57 D gnd nmos@7_n-trans-well N L=1.75U W=1.75U AS=8.452P +AD=8.575P PS=11.76U PD=11.2U Mnmos@8 Y net@57 gnd nmos@8_n-trans-well N L=1.75U W=1.75U AS=8.452P +AD=12.862P PS=11.76U PD=14.7U Mpmos@4 Y net@57 vdd pmos@4_p-trans-well P L=1.75U W=5.25U AS=31.238P +AD=12.862P PS=39.9U PD=14.7U Mpmos@5 net@57 D net@58 pmos@5_p-trans-well P L=1.75U W=5.25U AS=15.619P +AD=8.575P PS=11.2U PD=11.2U Mpmos@6 net@58 C net@120 pmos@6_p-trans-well P L=1.75U W=5.25U AS=15.619P +AD=15.619P PS=11.2U PD=11.2U Mpmos@7 net@120 B net@59 pmos@7_p-trans-well P L=1.75U W=5.25U AS=15.619P +AD=15.619P PS=11.2U PD=11.2U Mpmos@8 net@59 A vdd pmos@8_p-trans-well P L=1.75U W=5.25U AS=31.238P +AD=15.619P PS=39.9U PD=11.2U .ENDS or4 *** SUBCIRCUIT _8_3_encoder FROM CELL Final-Prj:8_3_encoder{lay} .SUBCKT _8_3_encoder D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 gnd vdd Xand2_1x@0 net@178 D5 net@66 gnd vdd and2_1x Xand3_1x@1 net@105 net@131 D3 net@46 gnd vdd and3_1x Xand3_1x@2 D2 net@131 net@105 net@41 gnd vdd and3_1x Xand3_1x@3 net@178 net@131 D3 net@60 gnd vdd and3_1x Xand4_1x@0 D1 net@178 net@131 net@227 net@54 gnd vdd and4_1x Xnot@0 D5 net@105 gnd vdd not Xnot@1 D4 net@131 gnd vdd not Xnot@2 D2 net@227 gnd vdd not Xnot@3 D6 net@178 gnd vdd not Xor4@0 D7 D6 D5 D4 O2 gnd vdd or4 Xor4@1 D7 D6 net@41 net@46 O1 gnd vdd or4 Xor4@2 D7 net@54 net@60 net@66 O0 gnd vdd or4 .ENDS _8_3_encoder

*** SUBCIRCUIT Comparator FROM CELL Final-Prj:Comparator{lay} .SUBCKT Comparator In1 In2 Out P1 VDD VSS gnd Mnmos@0 net@0 net@0 VSS nmos@0_n-trans-well N L=0.7U W=3.15U AS=51.777P +AD=7.779P PS=38.15U PD=11.55U Mnmos@1 VSS net@0 net@1 nmos@1_n-trans-well N L=0.7U W=3.15U AS=8.024P +AD=51.777P PS=12.017U PD=38.15U Mnmos@2 VSS net@0 Out nmos@2_n-trans-well N L=0.7U W=9.8U AS=67.13P +AD=51.777P PS=80.15U PD=38.15U Mnmos@3 net@1 In1 net@4 nmos@3_n-trans-well N L=0.7U W=2.1U AS=15.925P +AD=8.024P PS=18.9U PD=12.017U Mnmos@4 P1 In2 net@1 nmos@4_n-trans-well N L=0.7U W=2.1U AS=8.024P AD=15.558P +PS=12.017U PD=18.55U Mpmos@0 VDD net@4 net@4 pmos@0_p-trans-well P L=0.7U W=10.5U AS=15.925P +AD=134.913P PS=18.9U PD=111.417U Mpmos@1 P1 net@4 VDD pmos@1_p-trans-well P L=0.7U W=10.5U AS=134.913P +AD=15.558P PS=111.417U PD=18.55U Mpmos@2 VDD P1 Out pmos@2_p-trans-well P L=0.7U W=65.8U AS=67.13P AD=134.913P +PS=80.15U PD=111.417U Rresnpoly@0 gnd net@0 175000 * Spice Code nodes in cell cell 'Final-Prj:Comparator{lay}' C1 P1 Out 100f C2 Out GND 100f .ENDS Comparator *** TOP LEVEL CELL: Final-Prj:adc_test{lay} X_8_3_enco@0 net@131 net@127 net@124 net@120 net@116 net@113 net@110 O0 O1 O2 +gnd VDD _8_3_encoder XComparat@0 net@180 In net@110 Comparat@0_P1 VDD VSS gnd Comparator XComparat@1 net@171 In net@113 Comparat@1_P1 VDD VSS gnd Comparator XComparat@2 net@168 In net@116 Comparat@2_P1 VDD VSS gnd Comparator XComparat@3 net@172 In net@120 Comparat@3_P1 VDD VSS gnd Comparator XComparat@4 net@175 In net@124 Comparat@4_P1 VDD VSS gnd +Comparator XComparat@5 net@195 In net@127 Comparat@5_P1 VDD VSS gnd Comparator XComparat@6 net@179 In net@131 Comparat@6_P1 VDD VSS gnd Comparator Rresnpoly@0 net@180 VDD 1000 Rresnpoly@1 net@171 net@180 1000 Rresnpoly@2 net@168 net@171 1000 Rresnpoly@3 net@172 net@168 1000 Rresnpoly@4 net@175 net@172 1000 Rresnpoly@5 net@195 net@175 1000

Rresnpoly@6 net@179 net@195 1000 Rresnpoly@7 gnd net@179 1000 * Spice Code nodes in cell cell 'Final-Prj:adc_test{lay}' VDD VDD 0 DC 3.0 VSS VSS 0 dc -3.0 VGND GND 0 DC 0 VIN1 In 0 sin(1.5 1.5 1000) .include C:\Electric\models.txt .tran 0ns 1.5ms .END 2. DRC Log sheet for the Layout When we ran DRC, there was no error as in Figure1.

Fig 1: DRC for the layout 3. Well Check: When well check was performed on the complete layout below is Figure2 generated with no erros:

Figure 2: Well check of the layout.

4. Schematic VS Layout NCC check: When the schematic and layout were checked for comparison, below result, as in Figure 3 is generated which verified that both are matched.

Figure 3: Schematic vs layout check