ELEC301- CMOS VLSI Design

Chapter 06 CMOS Inverter, DC Characteristics

Reading Assignment: Chapter 5 Rabaey et. Al.
Some parts of the notes are taken from the notes provided in the book Digital Integrated Circuits A design Perspective by J. Rabaey, 2nd Edition
ELEC301 Lect 6

Topics covered
Static Behaviour of a CMOS Inverter Voltage Transfer Curve (VTC)
Noise Margins for complementary and ratioed Logic n/ p ratio

Provides a good understanding of the DC Characteristics of a CMOS inverter

Extract the VTC and analytical analysis of the transfer function for different operating regions. Noise Margin and DC performance of complementary and ratioed CMOS. Extend DC Analysis to more complex gates
ELEC301 Lect 6

Introduction
Inverter is the nucleus of all digital design. Electrical behavior of complex circuits can be almost completely derived by extrapolating the results obtained for inverters. The analysis of inverters can be extended to explain the behavior of more complex gates, such as NAND, NOR or XOR, which in turn form the building blocks for modules. The following properties will be analyzed: robustness (static or steady-state behavior); performance (dynamic or transient response); Heat dissipation and supply capacity requirement (power consumption).
ELEC301 Lect 6

Functionality and Robustness: The Static Behavior

Noise in Digital Integrated Circuits A digital gate should perform the digital function it is designed for even subject to noisy conditions. Noise - unwanted variations of voltages and currents at the logic nodes
v ( t) i( t) V DD

(a) Inductive coupling

(b) Capacitive coupling

( c) Pow er and ground noise

ELEC301 Lect 6

Steady-state parameters
measure how robust the structure is with respect to variations in the manufacturing and noise disturbances. digital circuit operates on logic variables x {0,1}. Electrical properties, e.g. current and voltage are continuous values Mapping electrical voltage into a discrete variable to represent logical values, associating a nominal voltage level with each logic state: 1<=> VOH, 0<=> VOL where VOH and VOL represent the high/low logic levels VOL = VOH and VOH = VOL Logic swing : VOH VOL (Equal to VDD for best case)
5

ELEC301 Lect 6

Immunity against Noise

There are many noise sources as described previously. The noise can affect the level of the signals at the input of the gate and can cause faulty switching. A robust gate: Fluctuations of the voltage at the input of the gate would not cause faulty transitions We will define the noise Margin!!! We need to analyze the robustness of the gate against variations of the input voltage.

ELEC301 Lect 6

DC Operation: Voltage Transfer Characteristic

V(x)

V(y)

V OH

V M VOL

The switching threshold voltage presents the midpoint of the V(y) switching characteristics, which is obtained when the output of a gate is short-circuit to the input. Even if an ideal nominal value is V(y)=V(x) applied at the input, the output signal will often deviate form the expected nominal value. Switching Threshold These derivation can be caused by noise or by the loading of the gate output.

VOL

V OH Nominal Voltage Levels

V(x)

ELEC301 Lect 6

Mapping between analog and digital signals

V(y) "1" VOH VIH Undefined Region "0" VIL VOL VOL V V IL IH V(x) VOH Slope = -1

Slope = -1

Acceptable region: delimited by VIH and VIL. VIH (VIL) is defined as the point where the gain (dVy/dVx) =-1 Region between VIH and VIL : undefined region Desirable to have: midway in the logic swing: VOL to VOH implies the transfer characteristics switch abruptly
ELEC301 Lect 6

Noise Margin
"1" VOH Noise Margin High Noise Margin Low VOL "0" Gate Output Gate Input NML NMH

VIH Undefined Region VIL

NML=|VIL-VOL| NMH=|VOH-VIH|

A measure of the sensitivity of a gate to noise :

NML(noise margin low) and NMH(noise margin high)

The noise margins represent the level of noise that can be sustained when gate are cascaded. The margins should be larger than 0 for a digital circuit to be functional (and by preference as large as possible).
ELEC301 Lect 6

Fan-in and Fan-out

(a) Fan-outN M N (b) Fan-in M

Fanout - number of load gates N that are connected to the output of the driving gate. Increasing the fan-out of a gate can affect its logic output levels. Also a large fan-out acts as an extra load and deteriorates the dynamic performance of a gate. Fan-in - the number of inputs to the gate. Gates with large fan-in tend to be more complex which often results in inferior static and dynamic properties.
ELEC301 Lect 6

10

The Ideal Gate

Vout

g= Vin

Ri = Ro= 0

infinite gain in the transition region gate threshold located in the middle of logic swing high and low noise margins equal to half the swing input and output impedances of the ideal gate are infinity and zero, respectively

ELEC301 Lect 6

11

Delay Definitions
Vin

50% t Vout t pHL t pLH 90% 50% 10% tf

ELEC301 Lect 6

t tr
12

Power Dissipation

ELEC301 Lect 6

13

The Static CMOS Inverter

V dd s g g d d s V ss Vout

V in

Cload

ELEC301 Lect 6

14

CMOS Inverter
N Well PMOS V DD 2 Contacts

Share power and ground

Abut cells

Connect in Metal

In Polysilicon

Out Metal 1

NMOS GND
VDD

VDD

PMOS In Out NMOS

ELEC301 Lect 6

15

Switch Model of CMOS Transistor

|VGS |

Ron

|VGS | < |VT|

ELEC301 Lect 6

|VGS | > |VT|

16

CMOS Inverter First-Order DC Analysis

V DD

V DD Rp

V out Rn

V out

VOL = 0 VOH = VDD VM = f(Rn, Rp)

V in = V DD
ELEC301 Lect 6

V in = 0

What happens if a PMOS is used for the pull-down and an NMOS is used for the pull-up?
17

CMOS Inverter: Transient Response

V DD Rp V DD

tpHL = f(Ron.CL) = 0.69 RonCL

V out CL Rn V out CL

V in 5 0 (a) High to Low

ELEC301 Lect 6

V in 0 V DD (b) Low to High

18

CMOS Properties
Full rail-to-rail swing equal to supply voltage high noise margin Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation (ignoring leakage) Low power Direct path current during switching Need to be optimized Steady state, there always exists a path with finite resistance between the output and either Vdd or Vss low output impedance (Ron) less sensitive to noise and disturbances (0 or Vdd state) Input resistance is extremely high (Iin=0)

ELEC301 Lect 6

19

Voltage Transfer Characteristics

Can be deduced from the load-line plots, which superimpose the current characteristics of the NMOS and the PMOS devices
V

I DS P = I DS n VGS n = Vin V DS n = Vout VGS P = Vin V dd V DS P = Vout V dd

V in g

dd s

d g d s V ss V out Clo
ad

Combining the VI characteristics of the n-device and p-device

ELEC301 Lect 6

20

PMOS Load Lines

IDn V in = VDD +V GSp IDn = - IDp V out = VDD +V DSp

V out

IDp Vin=0 V in=1.5

IDn

IDn Vin=0 Vin=1.5

V DSp VGSp=-1 VGSp=-2.5 Vin = VDD+V GSp IDn = - IDp

V DSp

Vout

Vout = V DD+V DSp

ELEC301 Lect 6

21

CMOS Inverter Load Characteristics

I Dn

Vin = 0

Vin = 2.5

PMOS

Vin = 0.5

Vin = 2

NMOS

Vin = 1 Vin = 1.5 Vin = 2 Vin = 2.5 Vin = 1.5

Vin = 1.5 Vin = 1 Vin = 1 Vin = 0.5 Vin = 0 Vout

ELEC301 Lect 6

22

CMOS Inverter VTC

Vout 2.5 NMOS off PMOS res NMOS s at PMOS res NMOS sat PMOS sat NMOS res PMOS sat

1.5

NMOS res PMOS off 2.5 V in

23

0.5

0.5
ELEC301 Lect 6

1.5

CMOS Inverter VTC

ELEC301 Lect 6

24

CMOS Inverter VTC

Region A:

NMOS: OFF PMOS: LIN

Region B:

NMOS: SAT PMOS: LIN

Region C: NMOS: SAT PMOS: SAT Region D: NMOS: LIN PMOS: SAT Region E: NMOS: LIN PMOS: OFF
ELEC301 Lect 6

25

Region A & B
Region A Defined by 0 < Vin < Vtn n-device cut off, p-device linear Idsn=-Idsp =0 Vdsp= Vout - Vdd with Vdsp =0 Hence Vout = Vdd Region B Defined by Vtn < Vin < Vdd /2 p-device linear region, n-device saturation represented by a resistor for ptransistor and a current source for the n-device
26

ELEC301 Lect 6

Current equation at Region B

The saturation current Idsn for the n-device is obtained by setting Vgs = Vin . So n Wn [Vin Vtn]2 n = [ ] Idsn = n tox Ln 2 The current for the p-device can be obtained by noting that Vgs = (Vin -Vdd) and Vds = (Vout -Vdd) and hence (Vout Vdd)2 = p [Wp ] p Idsp = (p )(Vin Vdd Vtp)(Vout Vdd) tox Lp 2 Substituting Idsp = -Idsn we have
2

n Vdd 2 Vout = (Vin Vtp) + (Vin Vtp) 2[Vin Vtp]Vdd (Vin Vtn) p 2
ELEC301 Lect 6

27

Switching Threshold Region (Region C)

Both the n- and p-devices are in saturation represented by two current sources in series Saturation currents are given (short channel model)

VDSAT VDSAT p n ( ) I = V V V V Idsn = nVDSAT V V dsp p DSAT M dd tp M tn p n 2 2

Equating Idsn and Idsp and solving for Vm we have

VM =

(Vtn +

VDSATn 2

) + r (Vdd + Vtp + 1+ r

VDSATp 2

) where

r=

k pVDSATp k nVDSATn

sat W p
p

satnWn
28

ELEC301 Lect 6

Switching Threshold as a function of Transistor Ratio

1.8 1.7 1.6 1.5 1.4

V (V)

1.3 1.2 1.1 1 0.9 0.8 10

10

W /W
p

ELEC301 Lect 6

29

Region D
Defined by Vdd /2 < Vin < Vdd - Vtp p-device saturation, n-device linear The two currents are

Idsp = p

[Vin Vdd Vtp] 2

V Idsn = n[(Vin Vtn)Vout ] 2

With Idsp = - Idsn we have

2 out

p Vout = (Vin Vtn) + (Vin Vtn) (Vin Vdd Vtp)2 n

2
ELEC301 Lect 6

30

Region E
Defined by Vin Vdd - Vtn p-device cut off, n-device linear Idsn=-Idsp =0 Vgsp= Vin - Vdd which is more positive than Vtp and Hence Vout = 0

ELEC301 Lect 6

31

Switching Threshold as a function of Transistor Ratio

1.8 1.7 1.6 1.5 1.4

V (V)

1.3 1.2 1.1 1 0.9 0.8 10

10

W /W
p

ELEC301 Lect 6

32

n/p ratio

ELEC301 Lect 6

33

Determining VIH and VIL

Vout V OH

VM

V in V OL V IL V IH

A simplified approach

ELEC301 Lect 6

34

Inverter Gain
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 0

gain

0.5

1.5

2.5

V (V)
in

ELEC301 Lect 6

35

Examples of VTC of Real Inverter

ELEC301 Lect 6

36

Examples of VTC of Real Inverter

ELEC301 Lect 6

37

Examples of VTC of Real Inverter

ELEC301 Lect 6

38

Impact of Process Variations

2.5

Good PMOS Bad NMOS Nominal

Vout(V)

1.5

Good NMOS Bad PMOS

0.5

0 0

0.5

1.5

2.5

Vin (V)

ELEC301 Lect 6

39

NMOS/PMOS ratio
5 x 10
-11

tpLH
4.5

tpHL

t (sec)

tp
4

= Wp/Wn

3.5

1.5

2.5

3.5

4.5

ELEC301 Lect 6

40

n/p ratio (II) (Temperature effect).

When n/p is decreased, the transition region shifts from left to right; however the output voltage transition remains steep and hence the switching performance is not affected. n/p =1 is desirable since it allows a capacitive load to charge and discharge in equal times by providing equal current-source and -sink capabilities. Temperature effect: 1.5 and hence Ids 1.5 n/p is relatively independent of temperature since n and p are similarly affected. Both Vtp and Vtn decrease slightly as temperature increases. Region A is reduced while Region E is increased, overall result is the transfer curve shifting left as temperature increases.
ELEC301 Lect 6

41