ECO Master Training - CR

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CR-5000, System Designer, Board Designer, PWS, Package Synthesizer and Lightning are trademarks or registered trademarks of Zuken, Inc. The other company names and product names are trademarks or registered trademarks of each company.
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Contents
Preface Welcome to the world of the Engineering Change/Operation
Chapter 1
Using Engineering Change and Operation Tools
1. Overview of the Lesson ................................................................................................1-1
Chapter 2
Engineering Changes
1. Forward Annotation (Engineering Change)...................................................................2-1

Forward Annotation ........................................................................................................................2-1 Forward Annotation Tool.................................................................................................................2-5 Forward Annotation Processing .....................................................................................................2-6 * ECO List File................................................................................................................................2-6 Tool Setting for Forward Annotation Tool........................................................................................2-8 * Resource File for Forward Annotation Tool ................................................................................2-10 Executing Forward Annotation .....................................................................................................2-11 Executing Forward Annotation during Interaction.........................................................................2-17 * Forward Annotation Log Display Dialog .....................................................................................2-18 Executing Forward Annotation by Communication.......................................................................2-19 Cautions on Forward Annotation ..................................................................................................2-22
2. Backward Annotation ..................................................................................................2-24

Backward Annotation ...................................................................................................................2-24 Backward Annotation Tool ............................................................................................................2-28 Backward Annotation Processing.................................................................................................2-29 * Backward Annotation Information List File (DCF) ......................................................................2-29 Tool Setting for Backward Annotation Tool ...................................................................................2-30 * Resetting Design Rule Database ...............................................................................................2-31 * Resource File for Backward Annotation Tool..............................................................................2-31 Executing Backward Annotation...................................................................................................2-32 Executing Backward Annotation during Interaction ......................................................................2-34 Executing Backward Annotation by Communication ....................................................................2-35 Cautions on Backward Annotation ...............................................................................................2-36
3. Referencing Schematic Diagram (Cross-Probing) ......................................................2-39

Referencing Schematic Diagram (Cross-Probing) .......................................................................2-39 Executing Referencing Schematic Diagram (Cross-Probing).......................................................2-40
4. Changing PC Board Specifications .............................................................................2-45

Changing PC Board Specifications ..............................................................................................2-45 Changing Design Rules (Editing Design Rules) ...........................................................................2-46 Reflecting Changes in the Technology Library onto the PC board (Updating Technology)...........2-48 Changing the Number of Conductive Layers (Editing Design Rules + Updating Technology)......2-52 * Delete Layer Data Forcibly Mode...............................................................................................2-55
5. Changing Components ...............................................................................................2-56

Reflecting Information in the CDB Library onto Component Information on the PC Board ..........2-57 Components are newly copied from CDB (Component Copy from CDB).....................................2-60 Referencing Footprint Specification Name and Reflecting All Component Shapes at Once ........2-61 Which Tool Should Be Used to Reflect CDB Changes? ...............................................................2-64
Chapter 3
Designing in Accordance with Operation
1. Divided Design..............................................................................................................3-1
Divided Designing ..........................................................................................................................3-1 Inputting Divided Area ....................................................................................................................3-3 Dividing the PC Board ....................................................................................................................3-4 Loading PC Board..........................................................................................................................3-8 * Technology Connector .................................................................................................................3-9 * Monitor Reference .....................................................................................................................3-10 Expanding Nesting Board.............................................................................................................3-11 Editing Nesting Board ..................................................................................................................3-13 Generating Hierarchy Connector..................................................................................................3-18 Editing Hierarchy Connector ........................................................................................................3-20
2. Designing by Reuse....................................................................................................3-21
Designing by Reuse .....................................................................................................................3-21 Inputting a Schematic Diagram for Designing by Reuse ..............................................................3-23 Designing by Reuse .....................................................................................................................3-24 Expanding a Reused PC Board ...................................................................................................3-26
3. Designing Build-up PC Board .....................................................................................3-27

Registering Build-up Via...............................................................................................................3-28 Registering Design Rules for a Build-up PC Board ......................................................................3-28 Useful Commands for a Build-up PC Board .................................................................................3-30 Drill Output of Build-up Via ...........................................................................................................3-37
4. Placing Jumper ...........................................................................................................3-39

Registering Jumper Components.................................................................................................3-40 Defining the Jumper Component..................................................................................................3-43 Placing a Jumper .........................................................................................................................3-44 * Changing Pitch ..........................................................................................................................3-44 Wiring Jumper ..............................................................................................................................3-45
5. Placing Decoupling Capacitor .....................................................................................3-46

Setting Placement Groups ...........................................................................................................3-47 Registering Decoupling Capacitor................................................................................................3-48 Attribute Passing Checks .............................................................................................................3-49 Executing Placement ...................................................................................................................3-50
6. Design with Different Rule for Each Constraints Area.................................................3-52

Defining Rules By Area ................................................................................................................3-53 Inputting Rules By Area................................................................................................................3-54 Designing with Rules By Area ......................................................................................................3-56 * Make Figure Into Component for Rules by Area ........................................................................3-59
7. Organizing the CDB ....................................................................................................3-60

Operation of Layer Mapping.........................................................................................................3-62 Operation of Other Footprint (Operation of Footprint Specification Name)...................................3-64
Appendix
1. Batch Program List ...................................................................................................... A-1
Database Operation ...................................................................................................................... A-1 ASCII Input/Output Interface ......................................................................................................... A-2 Component Library Management.................................................................................................. A-3 Design Change and Design Assist ................................................................................................ A-4 PC Board Information Reference/Output ...................................................................................... A-5 CAM Data Output/Reference ........................................................................................................ A-6 Interface to External Systems ....................................................................................................... A-7
Preface Welcome to the world of the Engineering Change/Operation

The Master Training <Engineering Change/Operation> is designed to enable you to learn how to maintain consistency between the schematic data and PC board data designed with the Board Designer when the schematic data is changed and how to operate the system for effective design. This book is intended for users who wish to master knowledge and skills for managing and operating data used in the Board Designer.
The aim is to attain a level where you can help operators. You will learn the flow of board design.
Beginners Training
Beginners Training <PCB Design>

Simple operations for PCB design
Master Training
Library
Master Training <Component Library>
Registration and management of libraries
The aim is to attain the knowledge necessary to be an operator.
Board Design
Master Training <PCB Design>
Detailed operation for PCB design
Master Training <PCB Design Library>

Registration and management of PCB design libraries
Master Training <CAM>

Operation for manufacturing panel design through CAM output
Master Training <Engineering Change/Operation>

Operation and knowledge related to engineering design change/operation
Users engaged only in library design and management should study up through Library but we also recommend reading Board Design. Users only engaged in board design are expected to mainly study Board Design but are recommended to previously read and try out Library.
Preface
Preface - 1
1. Overview of the Lesson

This Master Training <Engineering Change/Operation> manual explains "Operations to be performed if the circuit is changed and the process for reflecting changed contents" "Operations that lead to the efficient PCB designing" for a previously designed PC board. Unlike the other training manuals, no data for training is given in this manual. Please refer to the procedures for when a design has been changed and operations using the Board Designer.
IC2 IC1 R1 IC3 IC2

IC1
R1
IC3
R2 IC4
(Board generation)
CN1
IC2
IC4
(Change)
Change
IC3 IC1 R100 IC3 R101 R2 IC4 IC2
Change
Addition
(Forward annotation)
Deletion
Engineering change
Sub-PCB: ex_b.pcb
Parent PCB: ex.pcb
Parent PCB: ex.pcb
Sub-PCB: ex_a.pcb
Divided design
Chapter 1 Using Engineering Change and Operation Tools
1-1
The organization of the Master Training <Engineering Change/Operation> manual is as follows: Changing design To reflect changes on the schematic diagram on PCB data.
2. Backward annotation
To reflect changes in PCB data on the schematic diagram.
3. Referencing schematic diagram

To display the schematic diagram and PCB data on the same screen so that attribute data can be transferred from the schematic diagram, or components or nets can be selected. Conversely, components can be selected from the PCB data.
4. Changing PCB specifications

To reflect addition or deletion of a conductive layer or changes in layer mapping on the PCB data. Also to reflect changes in design rules on the PCB data.
5. Changing components
To reflect changes in CDB library on the PCB data.
Reference
See [Chapter 2 Engineering Changes].
1-2
Designing in accordance with operation
1. Divided design Data for one PCB is divided into several types for designing. When the design of each PCB data has been completed, the data is synthesized into one PCB. 2. Reused design Existing schematic diagrams and PCB data are also used in designing other PCBs.
3. Designing built-up PCB Design rules and valid commands necessary for designing a built-up PCB will be introduced.
4. Placing jumper
Preparatory work to generate jumper components and jumper generation will be introduced.
5. Placing decoupling capacitor

To generate decoupling capacitors not input to the schematic diagram with Board Designer.
6. Designed by different rule for each area The board, which generated the area in which the rule applied is different, is used for the design.
7. Organizing CDB To summarize the operation of components used in designing with the Board Designer.
Reference
See [Chapter 3 Designing in Accordance with Operation].
1-3
1. Forward Annotation (Engineering Change)

Forward annotation (engineering change) reflects any change made in the schematic diagram, while a PCB is being designed or after a PCB has been designed, on the PCB data.
IC2 IC1 R1 IC3 IC2
IC1 IC3 R1
R2 IC4
(Board generation)
CN1
IC2
IC4
(Change)
Change
IC3 IC1 R100 IC3 R101 R2 IC4 IC2
Change
Addition
(Forward annotation)
Deletion
Forward Annotation
The flow of forward annotation with the Board Designer is as illustrated below.
Chapter 2
Engineering Changes
2-1
Forward annotation reflects the contents of the following changes in the schematic diagram onto the PC board database. < Changed Contents>
1. 2. 3. 4. 5. 6. 7. 8.
Adding, changing, or deleting a component (gate) Adding or deleting a net (path), or changing net (path) connections Changing reference designator Adding or deleting a component group and adding or deleting component to/from component group Changing board net color Changing stock code Adding wiring width of net (including shielded wiring width and maximum/minimum wiring width of pin pair) Adding, changing, or deleting an attribute
1. Adding, changing, or deleting a component (gate) Contents that are added, changed or deleted are only reflected on components with "Component subject to board design: Yes" set in the CDB part library .
2. Adding, changing, or deleting a net (path) Contents that added, changed connection or deleted a net on the schematic drawing are reflected on the PCB. Not only the addition of a new net, but also addition of pin pairs is supported.
3. Changing reference designator Only the reference designator of components using the same symbol and with the same configuration (number of gates and gate IDs) can be changed.
2-2
Chapter 2
Engineering Changes
4. Adding or deleting a component group and adding or deleting component to/from component group A component placement group deleted from or added to the schematic diagram is reflected on the PCB. Components can also be added to or deleted from a component group on the PCB.
5. Changing board net color "Board net color" changed on the schematic diagram is reflected on the PCB.
Caution
During forward annotation, board net colors will not be changed unless [Reflect Board Net Color] is executed.
6. Changing stock code The stock code changed on the schematic diagram is reflected on the PCB.
7. Adding wiring width of net (including shielded wiring width and maximum/minimum wiring width of pin pair) The "pattern width" or "shielded pattern width" added or changed on the schematic diagram is reflected on the PCB.
Caution
During forward annotation, pattern widths will not be changed unless [Reflect Pattern Width] is executed.
Chapter 2
Engineering Changes
2-3
8. Adding, changing, or deleting an attribute The component attribute, net attribute, electrical net, pin pair number, and component pin attribute that have been added, changed or deleted on the schematic diagram are reflected on the PCB.
Reference
For details, refer to the online documentation.
2-4
Chapter 2
Engineering Changes
Forward Annotation Tool

The Forward Annotation Tools has the following three ways to execute it.
1. Forward Annotation Tool 2. Forward annotation during interaction with Board Designer 3. Forward annotation by communication with System Designer Forward Annotation Tool
From the CAD File Manager, click (Forward Annotation) to start the tool.
Click
Forward annotation during interaction with Board Designer (FA during interaction) Select Utilities Forward Annotation Select Netlist from the Placement/Wiring Tool.
Click
Forward annotation by communication with System Designer Open a schematic diagram on the same screen by using the System Designer, and open the PCB data to be designed by using the Board Designer. Then execute the following command: Select Utilities Forward Annotation Board Designer Net List And Design Rule from the System Designer. The Forward Annotation Tool is started after net information has been output.
Forward annotation is automatically executed after net information is output.
Chapter 2
Engineering Changes
2-5
Forward Annotation Processing

During forward annotation, the contents of the net list (.ndf) and design rule list (.ruf) extracted from the schematic diagram are compared with information on the components and nets of the PC board database and design rule database. Different information is then output to the ECO list file. Based on this ECO list, the contents of the change are reflected on the PC board database (PCB) and design rule database (RUL). * ECO List File Information on the net list and design rule list is compared with information on the PC board database (PCB) and design rule database (RUL) when forward annotation is executed. If any difference is found, information on the difference is output to the ECO list file.
Caution
Do not rewrite the ECO list file directly.
The changed contents can be checked by selecting Confirm Change Info from the menu bar on the Forward Annotation Tool.
2-6
Chapter 2
Engineering Changes
The following keywords are used to compare the contents in the net list (.ndf) and design rule list (.ruf) extracted from the schematic diagram with the information on the components and nets of the PC board database and design rule database: Keywords for changing design
Component ID (gate ID) Reference designator Net name
Caution
An ID that is automatically appended when a component (symbol) is input using the System Designer (e.g., 1.cmp2) is called a component ID. With the Board Designer, "Gate ID" is displayed on the Query window if information on a component is referenced by using a query command.
Example
If the reference designator for a symbol has been changed on the attribute changing dialog for the System Designer in order to change a reference designator on the schematic diagram, the reference designator for a component having the same gate ID on the PCB is changed because the component ID is not changed.
If IC1 in the above figure is deleted and the same component is newly input as IC200 in order to change a reference designator on the schematic diagram. However, the reference designator and component ID are changed. On the PCB, therefore, IC1 is deleted and IC200 is newly added.
Chapter 2
Engineering Changes
2-7
Tool Setting for Forward Annotation Tool

Items to be reflected on the PCB data can be selected when the Forward Annotation Tool is executed. The following items can be specified on the tool setting dialog that is displayed by selecting Set Set Up Tool from the menu bar for the Forward Annotation Tool. <Items that can be specified when forward annotation is executed>
1. 2. 3. 4. 5. 6. 7.
Output net/rule list from Schematic Change PC Board Database Save Temporary Patterns and Jumpers Reflect Net Color Reflect Pattern Width Retain footprint when changed part name references the same package name Temp. Part Assignment
1. Output Net/Rule List from Schematic Only when [CR-5000 Schematic] is selected for Set Net List Type selected from the menu bar for the Forward Annotation Tool, can the newest net list (.ndf) and design rule list (.ruf) be output from a specific schematic diagram (.cir) specified as a schematic information name. [On] Outputs the newest net list and design rule list. If the schematic drawing consists of two or more sheets, a sheet number can also be specified. [Off] Does not output the newest net list and design rule list.
Caution
The net list and design rule list cannot be output in an environment other than that where the System Designer can run.
2. Change PC Board Database Specify whether to reflect the changed contents on the PC board database or not. [On] Reflects the changed contents on the PC board database. [Off] Does not reflect the changed contents on the PC board database. The changed contents are output to the ECO list, so that they can be checked before they are reflected on the PC board database.
Reference For details of the ECO list, refer to "* ECO List File" on page 2-6.
3. Save Temporary Patterns and Jumpers Specify whether to save jumper components that are no longer necessary as a result of deleting a wiring pattern or net connected to a vacant pin or not. [On] Saves the jumper components. [Off] Deletes the jumper components.
2-8
Chapter 2
Engineering Changes
4. Reflect Board Net Color Specify whether "Board Net Color" appended to the net on the schematic diagram is reflected on the PCB. [On] Reflects the board net color. [Off] Does not reflect the board net color.
Undefined Blue Red Undefined Color Board Net Color on Blue PCB (before Tone execution of FA) Hatching Execution of Forward Annotation Undefined Color Board Net Color on Blue PCB (after Red execution of FA) Tone Hatching ( represents the "Board Net Color on PCB" that has been changed by "Board Net Color on Schematic" after execution of forward annotation. Board Net Color on Schematic
Caution
If "Tone" or "Hatching", instead of a net color, is specified for the net to be changed, they are reset after execution of forward annotation.
5. Reflect Wiring Width Specify whether to reflect the "pattern width" or "shielded pattern width" appended to the net on the schematic diagram on the PCB. [On] Reflects the wiring width. [Off] Does not reflect the wiring width.
Caution
To reflect a wiring width, a wiring stack name with the same value as the pattern width set on the schematic diagram defined on all layers is used. If such a stack name does not exist, the wiring width is added to the wiring width stack. When the wiring width is added to the wiring width stack, [Wiring Spec] Wiring Width Limit. of the design rule database is not taken into consideration. Even when the wiring width besides restriction is specified, a wiring width stack is generated by the wiring width.
Reference For details on reflecting wiring width, refer to the Online Help.
6. Retain footprint when changed part name references the same package name Specify whether to retained the changed in footprint in a PC board, when a part changed in Forward Annotation and the original part reference the same package name. You will use this when the changes in footprint in a PC board and you do Forward Annotation (change the part) while you do not wont to change it to default footprint. [On] The changes in footprints on a PC board are retained. [Off] The footprint is updated to default footprint referenced in a library.
Note
A default footprint means the footprint to which a package points by top priority according to the priority of the footprint specification name of a design rule database.
Chapter 2
Engineering Changes
2-9
7. Temp. Part Assignment Specify whether to execute temporary part assignment or not. Until a part is registered to the library, temporary part assignment is used to assign a temporarily registered part to a component. [On] Opens Temp. Part Assignment dialog if a part existing in the net list does not exist in the part library or if a package indicated by a part does not exist in the package library. A part correspondence table can be prepared in the following ASCII file format and specified. The file extension is .pt2. temporaryPart2 { part name that does not exist part name that exists } [Off] Does not open the Temp. Part Assignment dialog and an error occurs.
* Resource File for Forward Annotation Tool
The initial-setting value of a tool setting dialog reflects the contents of a setting of a tool resource file [board.rsc].
%ZUEROOT%\info\board.rsc %CR5_PROJECT_ROOT%\zue\info\board.rsc %HOME%\cr5000\ue\board.rsc

Note
The priority of the set contents is (3) (2) (1).
(1) (2) (3)
################################################## # Temporary Part Specification [On/Off] assignTemporaryPart: Off Specification of temporary part allotment ################################################## # Temporary Part List (pt2 file) Temporary part correspondence table #temporaryPartList: ""
path name
################################################## # Net list output from schematic [On/Off] Output net/rule list from Schematic fwrdAnnoNetList: Off ################################################## # Schematic Sheet No.From fwrdAnnoSheetFrom: 1 Schematic Sheet Number (From) ################################################## # Schematic Sheet No.To Schematic Sheet Number (To) fwrdAnnoSheetTo: 998 ################################################## # PCB Data Change [On/Off] fwrdAnnoUpdatePCB: On Change PC Board Database ################################################## # Keep the pattern which connect # with the empty terminal [On/Off] Save Temporary Patterns and Jumpers fwrdAnnoNcPin: Off ################################################## # Change net color [On/Off] fwrdAnnoUpdateNetColor: On Reflect Board Net Color ################################################## # Change width [On/Off] Reflect Pattern Width fwrdAnnoUpdatePatternWidth: Off ################################################## # Retain footprint when changed part name references # the same package name [On/Off] Retain footprint when changed part name fwrdAnnoSaveFtpSamePkg: Off
references the same package name.
2 - 10
Chapter 2
Engineering Changes
Executing Forward Annotation

1. From the CAD File Manager, click (Forward Annotation).
Click
2. Set parameters for forward annotation.

(1) Engineering Design Change Tool
Confirm that the Engineering Change Mode is Forward Annotation.
(1)
(2) Circuit Data Name
(2)
(3)
Specify a schematic diagram directory to which the net list is to be output. This field changes depending on the netlist type when forward annotation is executed.
(3) PC Board Database Name

Specify the path name of the PC board database (.pcb) being designed or completed.
Reference * For details on Update Design Relation, refer to [Set the relation between PC board data and circuit data] on page 2-20.
3. Specify the type of net list to be referenced. Select Set Net List Type from the menu bar and specify the type of net list to be referenced. Since the circuit information input field changes to the field for net list name specification, the target net list is specified, respectively.
Display will change
Chapter 2
Engineering Changes
2 - 11
Net List Type The Forward Annotation Tool can change the design by using the three types of nets CR-5000 net list (NDF, RUF), PWS/CCF net list, and PWS/ECF net list. From the Net List Type specified an object of net list type. The specification method is following four.:
CR-5000 schematic (NDF, RUF specify the schematic) CR-5000 net list (NDF, RUF directly specify the net list) PWS/CCF net list (with/without DEFINITION) PWS/ECF net list
Note
When you select CR-5000 schematic for the net list, refer to the following fixed parts for the target net list (NDF, RUF).
Reference part specified schematic directory (.cir)/ext/schematic directory name.ndf(ruf)

If you set Output net/rule list from Schematic as ON in the Set Up Tool then from the specified schematic directory it will output net list (NDF, RUF) to in the above-mentioned path. So you may do Forward Annotation by using a latest schematic information.
Reference For the dialog of Set Up Tool, refer to [Tool Setting for Forward Annotation Tool] on page 2-8.
This net list type is automatically changed depending on the file type selected in the CAD File Manager when the annotation tool is started.
Example
For example, if the tool is started from the CAD File Manager with ECF selected.
Net list type
Specify the ECF path to be referenced.

Note
The net list type can be set in the resource file (board.rsc) when the set name is selected and the tool is started.
################################################## # Default "Set Net List Type" [CIR/NDF/CCF/ECF] #fwrdAnnoNetListKind: CIR

Reference For details on board.rsc, refer to [Resource Files] in the Online Help. Reference Processing of forward annotation slightly differs when CCF or ECF is used. Online Help.
When you use this, refer to the
2 - 12
Chapter 2
Engineering Changes
Tool Setting Dialog 4. Select Set
Set Up Tool from the menu bar.

The changed contents to be reflected when forward annotation is executed can be specified on this dialog.
Reference
For details, refer to [Tool Setting for Forward Annotation Tool] on page 2-8.
5. To change the CDB library that is temporarily referenced when forward annotation is executed, select Set Library from the menu bar.
Specify the name of a library to be referenced. In the default status, the file name described in the following resource files is displayed. %ZUEROOT%\info\library.rsc %CR5_PROJECT_ROOT%\zue\library.rsc %HOME%\cr5000\ue\library.rsc
6. Click Execute. Processing is performed in the following sequence: Reading net list Reading design rule list Outputting ECO list Saving PC board database Reflecting ECO
Click
(1)
Normalizing land status Reflecting design rules

The message will display while it it processing
(2)
End
Chapter 2
Engineering Changes
2 - 13
Clearing Net Attribute
(1) Output ECO List If you changed net colors on PC board and did Reset Design Rule Database in Backward Annotation, then if you set Reflect Board Net Color as ON and do Forward Annotation, then net colors that you set in PC board will clear. In this case, the following warning dialog is displayed.
To save this message to a file, select Save Messages.
If an attribute value (such as loop wiring = enabled) is appended to a net using the PC Board Design Rule Edit (RUL) and not reflect it to schematic by Backward Annotation then in this condition if you do Forward Annotation then you will get above warning messages and the attribute value of the net is cleared.
Reference For the Backward Annotation, refer to [2. Backward Annotation] on page 2-24.
(2) Normalized Land Status Land Status Change History File The land status of the padstack is changed to an appropriate status when the changed
contents are reflected based on the ECO list file. For a padstack with a normalized land status, the following warning message is displayed:
These contents indicate the contents of PC board data name.loh at the same location as the PC board database. The status of each land is as follows: Land Status Output Character String noland No land noconnect Unconnected land connect Connected land thermal Thermal land clearance Clearance land
The dialog shown on the left is displayed when forward annotation has been correctly terminated.
Note
If an error occurs during execution of forward annotation, identify the error by selecting Confirm Confirm Error Current Error. An error number is displayed with the error. From the Online Help [Error/Warning Messages], search for the error number, and look for the meaning of the message and the way to deal with the error.
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Chapter 2
Engineering Changes
Note
The Forward Annotation Tool also has the following functions:
Restoring PC board data to data before Forward Annotation execution Extracting differences between PCB and RUL Checking displayed contents
Restoring Data
[Restoring PC board data to that before forward annotation execution] When the ECO list is reflected, the contents of the PC board database are changed and processing is finished. At the same time, the PC board database before change is saved under another name. Therefore, the status before change can be restored after execution of forward annotation. Select Set Restore Data from the menu bar.
Caution
After terminating the tool, the status of the pre-change PC board database cannot be restored.
[Extracting difference between PCB and RUL] Difference Extraction between If Delete Net, Add Net, Delete Component or Add Component is executed on PCB and RUL the Placement/Wiring Tool and data is stored, the contents of the change are only
saved to the PC board database (PCB). Because PCB&Rul and NDF&RUF are compared as explained in [* ECO List File] on page 2-9, forward annotation cannot be executed unless PCB = RUL. By the checking a differences between PCB and RUL in advance, the propriety of necessity and execution for Backward Annotation can be checked.
Select Confirm PCB design changes from the menu bar.
Caution
If forward annotation is executed with information on PCB different from that on RUL, the message Design changes are made in PCB. Perform back-annotation before forward-annotation is displayed in the message area of the annotation tool.
Chapter 2
Engineering Changes
2 - 15
[Checking displayed contents] The changed design contents can be checked.

Design Change History File
Select Confirm Confirm Change from the menu bar.
Design Change History File Design history files describing the changed contents are output to the same layer as the PC board file when forward annotation or backward annotation is executed. The following two types of design history files with the same information but in different formats are output. Of these, the contents of PC board file name.coh are the same as the above list dialog.
PC board file name.coh List format PC board file name.coe CSV format
Note
Design change history files are output with each PC board and are additionally written each time forward annotation or backward annotation is executed.
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Chapter 2
Engineering Changes
Executing Forward Annotation during Interaction

1. Select Utilities ForwardAnnotation Select Netlist the menu bar.
Click
2. Set parameters for forward annotation.

(1) Forward Annotation
(1) Specify a net list type and a net list name. When CR-5000 Shematic was selected to Net List Kind, you can specify the sheet number for output Net.
(2)
(2) Parameters
Specify whether each of the following five items is reflected or not. Save Temporary Patterns and Jumpers Reflect Board Net Color Reflect Pattern Width Retain footprint when changed part name references the same package name Temp. Part Assignment
Reference (1) For Update Design Relation, refer to [Set the relation between PC board data and circuit data] on page 2-20. Reference (2) For details of each parameters, refer to [Tool Setting for Forward Annotation Tool] on page 2-8.
3. Click Execute. Processing will be performed in the same sequence as the Forward Annotation Tool. 4. A mark is displayed to indicate a net with a cleared attribute value or the location of design change. In addition, Forward Annotation Log dialog is displayed.
Note
This Forward Annotation Log dialog is also displayed after execution of forward annotation by communication with System Designer.
Chapter 2
Engineering Changes
2 - 17
* Forward Annotation Log Display Dialog When the [Name] column on the Forward Annotation Log dialog is double-clicked, the corresponding location in the editor is zoomed.
Clicking Close on the Forward Annotation Log dialog causes the mark displayed on the editor to disappear. To confirm again, select Utilities Forward Annotation Forward Annotation Log.
Note
The contents of the Forward Annotation Log dialog show the latest contents of the Design Change History File [PC board file name.coh]. Accordingly, if you execute Forward Annotation from the CAD File Manager, you can still check the locations that have changed from the Forward Annotation Log after opening a file.
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Chapter 2
Engineering Changes
Executing Forward Annotation by Communication

If both the System Designer and the Board Designer have been started and the following conditions are satisfied, forward annotation to the Board Designer is executed at the same time of the net list has been correctly output by selecting Utilities Forward Annotation Board Designer Net List And Design Rule from the menu bar in the schematic editor. Execution conditions for forward annotation by communication
The file names for schematic data and PC board data are the same. (same base name) (for example, if schematic data file name is A.cir, the PC board data file name must be A.pcb). The schematic and PC board are in correlation. (Design Relation) (For this condition, schematic data and PCB file name does not need to be the same name.)
Example
Same Database Name To execute forward annotation by communication by opening schematic diagram file BD-sample.cir and PC board data file BD-sample.pcb 1. Start System Designer and open schematic diagram file BD-sample.cir. Also start Board Designer and open PC board data file BD-sample.pcb. 2. Change design on the schematic diagram, and select Utilities Forward Annotation Board Designer Net List And Design Rule from the menu bar.
Click OK on the dialog that is displayed after the net list has been correctly output.
Click
Processing progress will be displayed in the message display area and process for the forward annotation in Board Designer will start.
Click
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Example
Set the relation between PC board data and circuit data For example, if you like to do forward annotation by communication with the relation between different circuit name SD-sample.cir and PC board data BD-sample.pcb 1. From the CAD File Manager, click the [BD-sample/[Board]] PC board file set, and click Action Change Design Relation from the Assist menu.
Click
2. In the dialog of Change Design Relation,

Click
(file selector) select an object of from circuit directory [SD-sample.cir] and click OK. 3. The circuit directory that set in relation will display as shown on the left. Double click the file set [BD-sample/[Board]] to execute the Placement/Wiring Tool.
Move the directory by using a relation
4. Next, start System Designer. Double click the [SD-sample.cir] circuit directory for which you set a design relation to move the directory in the CAD File Manager to the location with the circuit directory. If circuit data is related to PC board data in the same way, and you double click a PC board data file set, the directory moves to the location of the PC board data.
Double click
Double click
After you execute the System Designer, from the menu bar execute a Utilities Forward Annotation Board Designer Net List And Desing Rule. Rest of all are the same as previus page.
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Other way to set the relation
Set the relation to circuit design data is described as in previous page it can set up from CAD File Manager arbitrarily to PC board data. But you may also set it in tool dialog of New Board Generation, Forward Annotation, and Backward Annotation.
Board Generation Tool
Forward Annotation Tool
Backward Annotation Tool
Also if you execute the forward annotaiton or backward annotation from PC board data that has relation, then it will executed with an object of circuit data is already set in.
Reference
For the each tool dialog, refer to [Executing Forward Annotaion] on page 2-11 and [Executing Forward Annotation during Interaction] on page 2-17 .
To cancel the design relation, select the PC board file set or circuit directory in the CAD File Manager to display the Assist menu, and click Action Change Design Relation. Enter a check in Remove Relation at the bottom right of the design relation dialog, and click OK.
Click Click
Note
In the forward annoation by communication after you execute the forward annoation from circuit design data, the dialog which checks whether it performs to PC board data or it does not carry out can be displayed. If you set as [confirmExecECO : On] in %ZUEROOT%\info\board.rsc, then before execute the forward annoation to PC board data it will display the following confirme dialog.
:
################################################# # Display dialog to confirm # executing ECO on Board Designer [On/Off] confirmExecECO: Off
Reference
For [board.rsc], refer to [* Tool Resource file for Forward Annotation] on page 2-10.
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Cautions on Forward Annotation

1. If a component has been added, it is added as a basic component. Open the schematic diagram by using the Placement/Wiring Tool and then place the component in the layout area.
2. Wired patterns may remain after forward annotation. Deleting component The component is deleted but the wired pattern remains.
The wiring pattern can be deleted in the antenna mode of the wiring deleting command.
Changing net
A wired pattern remains if the connection destination is changed. The pattern is deleted only if the following conditions are satisfied:
The connection destinations of both the pins have been deleted (the pins become vacant). The same signal name has been deleted from the PC board.
Even if the connection destination is changed, the wired pattern remains. Be sure to (Area DRC) command after execution of forward annotation. If an error execute occurs, correct the error.
3. The following changes are not subject to forward annotation: Changing only part/pin assignment/function attributes Changing package name indicated by part Changing footprint name indicated by part Changing footprint/padstack/pad Update these changes by selecting Utilities Update Component from CDB in the Floor Plan or Placement/Wiring Tool.
Reference
For points to be cautioned, refer to the Online Help.
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Note
Tips
Operate using the component library for schematic designing to maintain consistency between the schematic diagram for the System Designer and the component information used for the PC board data in the Board Designer. The operation flow when the component library for schematic designing is used is illustrated below.
Operation Using Component Library for Schematic Designing
Because the component library for schematic drawing is extracted from the part library as illustrated above, inconsistency of component information does not take place when a new PC board is generated, or when forward annotation or backward annotation is executed. When designing is changed by adding a new component or changing the existing component information, the necessary information is registered to or corrected in the part library. After this extract the LCDB and update the component library for schematic.
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2. Backward Annotation
Backward annotation is used to extract information that has been changed while a PC board is designed and to reflect that information on the schematic diagram. By executing backward annotation, consistency of the schematic data and PC board data can be maintained.
IC2 IC1 R1 IC3 IC2
IC1 IC3 R1
R2 IC4
(Board generation)
CN1
IC2
IC4
(Change)
Change
R100 R101 IC1 IC3
Addition Deletion Deletion
(Backward annotation)
CN1
IC2
IC4
R2
Backward Annotation
The flow of backward annotation with the Board Designer is as illustrated below.
COH
COE
DCF
Design change history file
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Backward annotation is used to reflect the following changed contents made on a PC board to the schematic diagram. < Changed Contents>
1. 2. 3. 4. 5. 6. 7.
Adding, changing, or deleting a component Adding, changing, or deleting a net Changing reference designator Exchanging pin or gate Adding a component group and adding component to component group Changing stock code Adding, changing, or deleting an attribute
1. Adding, changing, or deleting a component (gate) Contents added, changed or deleted on the PC board are reflected on the schematic diagram. A component added on the PC board is added to sheet 999 (999.sht).
Caution A component added on the Board Designer is done so as a package component (1 component = 1 gate). If information at package component level is not registered to the component library for schematic designing, therefore, the change cannot be reflected on the schematic diagram.
2. Adding, changing, or deleting a net Contents that added changed connection of or deleted a net on the schematic diagram are reflected on the PC board. Not only the addition of a new net, but also the addition of a pin pair is supported.
Caution If a net is appended to a vacant pin, a net shorter than the connected pin is drawn out on the schematic diagram and a signal name is set. The net is not wired on the schematic diagram.
Caution If a net has been deleted, part of the net from a pin is deleted on the schematic diagram. deleted.
A series of nets is not
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3. Changing reference designator The reference designator of a component that has been changed on the PC board is reflected on the schematic diagram.
4. Exchanging pin or gate Information on pins exchanged by referring to the logical polarity of the part information or equivalent definition of the function information, or on gates exchanged by referencing the setting of function names of the pin assign information is reflected on the schematic diagram.
Caution
When information on exchanging pins or gates is reflected, the pin numbers on the schematic diagram are changed.
5. Adding a component group and adding component to component group A component can be added to an existing component group or a new component group can be registered by using the Group Manager on the Floor Plan Tool. Information on setting components to that component group can be reflected on the schematic diagram.
Caution Caution
Addition of a component that belongs to a component group or registration of a new component group can be reflected, but a component deleted from a component group and deletion of a component group is not reflected. Group Manager is only can used in Floor Plan Tool [Option].
6. Changing stock code A stock code changed on the PC board is reflected on the schematic diagram.
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7. Adding, changing, or deleting an attribute Component, net, pin pair, or component pin attributes added or changed on the PC board are reflected on the schematic diagram.
Reference
For details, refer to the online documentation.
Caution
The component which can be reflected to a schematic

Of the changed contents 1 through 7 (page 2-25 to 2-27) that can be reflected on the schematic diagram, information for which Use for Schematic: Yes is specified as the part information for the CDB can be reflected on the schematic diagram.
[Part Library]
[Query the Part]
When a change or add is made for like jumper on the PC board but that change should not be reflected on the corresponding component on the PC board, set Use for Schematic: No.
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Backward Annotation Tool

For the Backward Annotation Tool, there is three ways to execute it.
Backward Annotation Tool Backward Annotation during Interaction in Board Designer Backward Annotation by Communication with System Designer Backward Annotation Tool
From the CAD File Manager, click (Back Annotation).
Click
Backward Annotation during Interaction in Board Designer (BA during interaction) From Placement/Wiring Tool, select Utilities BackAnnotation, and execute.
Execute the backward annotation with set a Change Schematic (Auto) as OFF. In this case, it only output a backward annotation file (DCF) and not reflect it to System Designer.
Click
Backward Annotation by Communication with System Designer On the same desktop, open the PC board data from Board Designer and circuit data from System Designer, and then execute it by following command. From the Placement/Wiring Tool, click a Utilities BackAnnotation.
Execute the backward annotation with set a Change Schematic (Auto) as ON.
After output the DCF file, automatically display the backward annotation execute dialog from System Designer. By click a execute button, it will reflect to circuit data.
Click Click Click Click
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Backward Annotation Processing

Backward annotation is used to compare the PC board database and design rule database to discover the changed contents on the PC board, extract change information (difference information) to a backward annotation information file (DCF). This is necessary in order to maintain consistency between the PC board and schematic diagram. * Backward Annotation Information List File (DCF) Information on changes found as a result of comparing the PC board database with the design rule database is output to the backward annotation information list file (DCF).
(1)
The PC board data base and the design rule database have the same information immediately after a new PC board has been created or forward annotation as shown on the left.
(2)
The changed contents on the Board Designer are saved only to the PC board database. Consequently, the information on the PC board database differs from that on the design rule database. Backward annotation outputs this change information to the DCF file.
DCF
Caution Do not rewrite the DCF file directly.
After the backward annotation, to check the changed contents, select Confirm Confirm Change from the menu bar in the backward annotation.
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Tool Setting for Backward Annotation Tool

The items that are to be reflected on the schematic diagram can be selected when the Backward Annotation Tool is executed. The following items can be specified by using the tool setting dialog that is displayed by selecting Set Set Up Tool from the menu bar on the Backward Annotation Tool. <Items that can be specified when backward annotation is executed>
1. 2. 3.
Reset Design Rule Database Change Schematic (Auto) Update Range
Resetting Design Rule Database
1. Reset Design Rule Database Specify whether to update the information on the design rule database (RUL) after the backward annotation information file has been output. [On] Reflects design change information made on the PC board (such as addition or deletion of components and nets) onto the design rule database (RUL). [Off] Does not reflect the most recent information onto the design rule database. 2. Change Schematic (Auto) Specify whether to extract the changed contents made on the PC board to a backward annotation information file (DCF) and to reflect the changed contents on the schematic diagram based on the DCF file, or to execute only extraction of the DCF file. [On] Reflects the changed contents on the schematic diagram. [Off] Executes only extraction of the DCF file and does not reflect the changed contents on the schematic diagram.
Caution
To reflect the changed contents on the schematic diagram by specifying [On], the environment must be that where the two systems, Board Designer and System Designer, run on one machine; otherwise, the schematic diagram cannot be updated. If [Off] is specified, the changed contents can be reflected onto the schematic diagram using a backward annotation on the System Designer, by read in the DCF file.
Note
3. Update Range Specify a range in which the schematic diagram is to be updated or the changed contents are to be extracted to the DCF file. [Swap Pins/Swap Gates/Change References/Change Part] As this title indicates, swapping of pins or gates and changing of a reference designator or part are reflected on the schematic diagram. However, the changed contents, if parts are swapped, are reflected only if the following condition is satisfied:
(Condition)
Part of the schematic symbol to be swapped is not changed in parallel with part change on the PC board. In addition, the symbol names are the same before and after the change.
[Update all PCB changes] page 2-25.
Reflects all the changed contents explained on
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* Resetting Design Rule Database After the new board generation or forward annotation, the information for reference designator, part name, pin number, net name and etc will saved on to the PCB and RUL by each. But when you do change the design like add/delete the net or component, these information will only save to board database therfor when you save the file, the board database and desing rule database have not adjustment. This means there is a difference between PCB and RUL.
Change Reference Add Component
IC1 IC5 IC4 IC2 IC7 IC6 IC3
PCB
IC101:LS08 Change Reference IC2:LS08 Delete Component R1:4.7k Change Part C101:1.0uF Add Component
RUL
CN1
IC1:LS08 IC2:LS08 R1:1.8k
Change Part
Delete Component
In forward annotation, the information on PCB and RUL is performed considering an equal thing as a premise. The forward annotation cannot be performed when the adjustment of PCB and RUL is not maintained. In such a case, the Reset Design Rule Database which reflects the information on PCB to RUL is needed.
* Resource File for Backward Annotation Tool The initial-setting value of a tool setting dialog reflects the contents of a setting of a tool resource file [board.rsc]. %ZUEROOT%\info\board.rsc %CR5_PROJECT_ROOT%\zue\info\board.rsc %HOME%\cr5000\ue\board.rsc
Note
(1) (2) (3)
The priority of the set contents is (3) (2) (1).

################################################## # reset the DesignRuleDB [On/Off] bwrdAnnoBackPost: On Reset Design Rule Database ################################################## # automatically apply back annotation # to the schematic [On/Off] bwrdAnnoUpdateSch: Off Change Schematic (Auto) ################################################## # Update Range # Off: Swap Pins/Swap Gates/Change References/Change Part # On : Update all PCB changes bwrdAnnoCompNet: Off Update Range
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Executing Backward Annotation

1. From the CAD File Manager, click (Back Annotation).
Click
Click
2. Set parameters for backward annotation.

(1) Engineering Change Tool
Confirm that Engineering Change Mode is [ Backward Annotation].
(1) (2)
(2) Circuit Data Name

Specify a file path that outputs the backward annotation information file (.dcf). To perform processing up to reflecting the changed contents on the schematic data, also specify a schematic diagram directory name (.cir).
(3)
(3) PC Board Database

Specify the path name for the PC board database (.pcb) being designed or completed.
3. Select Set Set Up Tool from the menu bar.

The changed contents to be reflected when backward annotation is executed can be specified on this tool setting dialog.
Reference For details, refer to [Tool Setting for Backward Annotation Tool] on page 2-30.
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4. Click Execute.
Processing will be performed in the following sequence: Extracting backward annotation information Reflecting on schematic diagram Saving PC board database Resetting backward annotation information End
*2 *1
Caution
*1 Executed only when Change Schematic (Auto) is set to ON. *2 Executed only when Reset Design Rule Database is set to ON. If the file to be used is opened by any other tool, an error occurs and backward annotation cannot be executed.
Caution
When backward annotation has been completed correctly, the dialog shown on the left is displayed.
Reference
If an error occurs during backward annotation execution, identify the error by selecting Confirm Confirm Error Current Error. An error number is displayed with the error. From the Online Help [Error/Warning Messages], search for the error number, and look for the meaning of the message and the way to deal with the error. The Backward Annotation Tool also has the same following functions as the Forward Annotation Tool:
Note
Restoring PC board data to data before backward annotation execution Extracting differences between PCB and RUL Checking displayed contents
Because each of these functions has been explained in the forward annotation description, only command names are introduced below.
Reference Refer to page 2-15 for the explanation of each function.
[Restoring PC board data to data before execution of backward annotation] Select Set Restore Data from the menu bar. [Extracting differences between PCB and RUL] Select Confirm PCB design changes from the menu bar. [Checking displayed contents] Select Confirm Confirm Change from the menu bar.
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Executing Backward Annotation during Interaction

1. Select Utilities BackAnnotation the menu bar.
Click
2. Set parameters for backward annotation.

(1) Backward Annotation
(1) (2)
Set a Reset Design Rule Database. Set a Change Scematic (Auto) as OFF.
(2) Range of Change

Specify the changed information that output to DCF file.
Reference
Detail information for (1) and (2), refer to [Tool Setting for Backward Annotation Tool] on page 2-30.
3. Click Execute. Processing will be performed in the same sequence as the Backward Annotation Tool that described in previus page. 4. When it finished in normal, then message will displayed in message area.
5. The PC board file name.dcf will output to the same directory with PC board data.
Caution
In the backward annotation during interaction, you may not specify the output directory for the DCF file.
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Executing Backward Annotation by Communication

If both the System Designer and the Board Designer have been started and the following conditions are satisfied, backward annotation to the System Designer that refer that DCF file will executed at the same time of the DCF file output by selecting Utilities Back Annotation from the menu bar in the Placement/Wiring Tool. Execution conditions for backward annotation by communication
The file names for schematic data and PC board data are the same. (same base name) (for example, if schematic data file name is A.cir, the PC board data file name must be A.pcb). The schematic and PC board are in relation. (Design Relation) (For this condition, schematic data and PCB file name does not need to be the same name.) Change Schematic in tool set dialog is ON
Reference
For details on Update Design Relation, refer to [Set the relation between PC board data and circuit data] on page 2-20.
Example
To execute forward annotation by communication by opening schematic diagram file BD-sample.cir and PC board data file BD-sample.pcb
1. Start System Designer and open schematic diagram file BD-sample.cir. Also start Board Designer and open PC board data file BD-sample.pcb. 2. After the change design on the PC board, select Utilities Back Annotation menu bar and execute it. 3. Set Change Design as ON, and set the Update Range, then click Execute button.
Click
Click
Click
4. The window of System Designer will be in active, and backward annotation tool execute confirmation dialog will display. If you click Yes, then Back-annotation from BD in System Designer will display. Set the engineering design range and click a Execute button. When it finished in normally, message dialog show in left button will display.
When the backward annotation from BD is running, the message [Updating schematic data] will display on the Board Designer. When the Back-annotation from BD is finish, finished message will display as below and close the backward annotation dialog.
Click
Click
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Cautions on Backward Annotation

1. To reflect backward annotation information on the schematic diagram, the component library for circuit designing (LCDB) is referenced. Information on the component library (CDB) and that on the component library for circuit designing (LCDB) must be consistent.
Reference Refer to an example on designing operation while maintaining consistency between the component library and the component library for circuit designing in [[One Point Advice] in Cautions on Forward Annotation] on page 2-23.
2. If a component has been added with the Board Designer, a package symbol is added to the 999.sht of schematic.
It is therefore necessary that information at component level (component type: component) be registered to the component library for circuit designing (LCDB). If a gate is added as a result of adding a net as follows, the gate is added to the schematic diagram.
Reference For the specification, cautions, and a restriction matter of backward annotation, refer to the Online Help.
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3. In order to maintain the consistency of PC board data and circuit data, it is necessary to reflect the change information a circuit at the time of backward annotation execution.
Described as in page 3-29 [ Backward Annotation Processing], backward annotation information list file (DCF) is output as information for the difference of PCB and RUL in the reset design rule database. Please be careful about after once you reset it, even so you redo the backward annotation, difference information that output in first time will not output in the second time of DCF file.
Example
Schematic (original)
C1 IC1 IC2
R1
Backward Annotation in First time Change Schematic : OFF
Reset Design Rule Database : ON

DCF
Add Component C101
Not reflect only the changed information in first time.
C101 Add Component
Backward Annotation in Second time Change Schematic : ON Reset Design Rule Database : ON
DCF
Change Reference R1R101
IC1 C1 IC2
C101 R101 Change Reference
R101
Reflect only the changed information in second time.
Like described in above, changed information before the first backward annotation can not reflect it.
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Therefore, in the environment that not have a System Designer, every time you execute the backward annotation you need to save the each DCF file and need to execute backward annotation for number of DCF file.
Reflect to Circuit
[Execute Backward Annotation (first time)]
DCF
Add Component C101
C101 C1 IC1 IC2
R1
[Execute Backward Annotation (second time)]
DCF
Change Reference R1R101
C101 C1 IC1 IC2
R101
Note
If the tool set dialog is in following setting, then the dialog to which cautions are urged will display. Change Schematic (Auto) : OFF Reset Design Rule Database : ON
Note
You may defined the display or not display for the confirmation dialog in tool resource file (board.rsc)
################################################## # Display BwrdAnno Reset confirm Dialog # [On/Off] #bwrdAnnoResetConfDia: Off

Reference
For details on board.rsc, refer to [* Resource File for Backward Annotation Tool] on page 2-31.
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3. Referencing Schematic Diagram (Cross-Probing)

Referencing Schematic Diagram (Cross-Probing)
Communication can be established between the System Designer and Board Designer, so that Board Designer components or nets can be selected while referencing the schematic diagram designed with the System Designer, or the attributes changed on the schematic diagram can be transferred between the System Designer and Board Designer.
Double-Click
Send
Caution1 Cross-probing can be executed between System Designer and Board Designer when executed on the same display and by the same user. Caution2 There is no check for whether the schematic diagram and layout are of the same design data.
Cross-probing is a function that can be executed between the System Designer and Board Designer. The functions that can be used, however, differ depending on the tool to be manipulated, as follows: If the System Designer is manipulated
1. 2. 3. 4.
Selecting component from schematic diagram Selecting net from schematic diagram Transferring attribute from schematic diagram Grouping of components from schematic diagram
If the Board Designer is manipulated
1. Checking unplaced component and unconnected net from PC board 2. Checking when component or net is referenced from PC board
Keywords for Cross-probing
The keywords to identify data when using the above functions are as follows:
Component Net
Note
System Designer Reference Net name
Board Designer Original reference Net name
The Original reference means, reference that set in the new board generation or forward annotation.
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Executing Referencing Schematic Diagram (Cross-Probing)

The procedure for executing the functions explained in the preceding section is as follows. Be sure to execute Steps 1 through 4 when executing cross-probing.
1. Start System Designer and open the schematic diagram. 2. Select Communicate To Layout from the menu bar. To Layout : ON 3. Start Board Designer and open PC board data. 4. Select Communicate To Schematic from the menu bar. To Schematic : ON
The procedure changes depending on the function to be executed. The execution procedure for each function is explained next.
(To manipulate the System Designer)

<Selecting a component from the schematic diagram (move)> 1. Click (Move Component) on the icon bar in Board Designer. 2. In System Designer, double-click the component. If you like to select several component, change the focus to Component Cell and click a Communicaton Send Select Status.
Double-Click
3. The component is in drag mode on the Board Designer. When you use Send Select Status (like sending a selecting several components), on Board Designer also in select mode. If you like to do dragg move, then click a Data End and change to dragg move mode.
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<Selecting a component from the schematic diagram (align component) A component can also be selected from the schematic diagram even when the Align Component command is executed. (Align Component) from Board 1. Click Designer. Set [Schematic Location] to ON on the panel menu. 2. Specify two or more symbols on System Designer while holding down the SHIFT key. Click Communicate Send on the menu bar.
Click Click Click
Click
3. The components are aligned as in schematic diagram, if Data End on the assist menu for Board Designer is clicked.
If symbols specified on the schematic diagram are arranged in the order of IC8, IC6, and IC7 from the left, the components on the Board Designer are also aligned in the same order.
<Selecting net from the schematic diagram> 1. Click (Input Wire) on the icon bar for Board Designer. 2. Focus Net Object on System Designer, and click a net. Select Communicate Send from the menu.
Click
Instead of selecting Communicate Send, the net can also be transmitted by double-clicking the mouse button.
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The net selected on Board Designer is zoomed, unconnected.
<Transferring an object from the schematic diagram>
1. Focus Net Object on System Designer

Click
and click a net. Click (Change Attribute) and specify the max total length and min total length from the attribute changing dialog. When you click OK in dialog of change attribute will send it to Board Designer.
Reference
For details of the attributes that are passed, refer to the Online Help.
When the net is referenced on Board Designer, the max total length and min total length of the net are displayed.
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<Grouping components from the schematic diagram> 1.Click or on Board Designer. 2.Focus Component Cell on System Designer. Select two or more symbols to be grouped. (Change Attribute) and set a Click component placement group on the attribute changing dialog.
The grouped components can be checked by selecting Attributes Group Manager from the menu bar in the Floor Plan Tool for Board Designer.
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(To manipulate the Board Designer)

<Checking unplaced component and unconnected net> 1. Select Communicate Update Marking from the menu bar on the Board Designer.
2. A white mark is displayed on the System Designer to indicate an unplaced component and unconnected net.
The white highlight indication can be canceled by clicking Communicate Marking Release on the menu bar in the System Designer.
Checking when component or net is referenced from PC board 1. Click (Query Data) on Board Designer.
Click a component or net.
Click
2.The component or net referenced on the Board Designer is selected in red on the System Designer.
Select or [Mark] can be chosen when selecting Communicate Communication Mode from the menu bar in the Board Designer for checking. Select An object with an attribute to be changed on the System Designer is displayed. Mark White highlight indication. This highlight indication can be canceled by selecting Communicate Marking Release from the menu bar in the System Designer.
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4. Changing PC Board Specification

If the design specifications are changed as follows during or after completing designing, the specifications of the PC board data are changed.
Changing PC Board Specifications

Board Designer broadly classifies the above changes into the following two types of information: Changing technology Changing number of wiring layers and attribute Addition or deletion of layer (such as user-defined layer) Changing layer order and layer comment Changing mapping of layer Changing design rules Changing usable wiring width Changing clearance values Changing used via Changing to other design rule
The tool to be used differs depending on which type of information is to be changed. If the design rule is also changed as a result of changing the number of wiring layers and the layer attribute (positive, mixed, or negative) of each wiring layer, two tools are used. Tools used for changing PC board specifications
To change design rules Change Design Rule Tool To change technology information PCB Technology/Component Update Tool
These two tools are divided into the following topics and explained:
Changing design rules (editing design rules) Reflecting changes in technology library on PC board (updating technology) Changing number of conductive layers (editing design rules + updating technology)
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4. Changing PC Board Specifications
Changing Design Rules (Editing Design Rules)

To add a usable wiring width (pattern width) during designing, to add a padstack that is used as via generated during wiring, or to change clearance values, use the design rule editor to make additions or changes. The design rule editor can be started in the following two ways:
1. From layout editor 2. Starting from the CAD File Manager Starting from editor Additions or changes can be made while the PC board data is open, without having to close an opened file or terminate a tool. 1. Select Module Edit Design Rules from the menu bar.
Click
Starting from the CAD File Manager 1. From the CAD File Manager, click (Change Design Rule).
Click
Execute design rule edit tool for PC board by ether one of the above, and edit the design rule. The changed information will reflect by File Save. If the Design Rule Editor is started from the CAD File Manager, changes are reflected when the tool exits.
Caution1
If the Design Rule Editor is started from the CAD File Manager, it references the "Technology/Part/Package/ Footprint" Library contained in the PCB Design Library List File when it starts.
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Note
If the Design Rule Editor is started from the editor, the settings and changes below cannot be carried out. To make the changes below, start the Design Rule Editor from the CAD File Manager. Changing Technology Name Update PC Board Database Execute Library Searcher Footprint Spec Name Changing Power Plane Net Name
The functions below can only be used when the Design Rule Editor is started from the editor. They cannot be used in the Design Rule Editor if it is started from the CAD File Manager.
Add/Delete Decoupling Capacitor

Reference
Add/Delete Jumper
The contents of each setting item, and the usage, refer to [Master Training <PCB Design Library>].
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Reflecting Changes in the Technology Library onto the PC board (Updating Technology)
When you are in the process of designing a PC board, if there has been a change in the technology, such as an added layer or a change to layer mapping, use the Technology Update Tool to reflect that change from the Technology Library to the PC board data which is being designed, or which has been designed.
Caution Addition of layers other than conductive layers is explained in this section. For addition or deletion of a conductive layer, refer to the next section [Changing Number of Conductive Layers (Editing Design Rules + Updating Technology)].
From the CAD File Manager, click
(Technology Update).
Click
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Example
To add a user-defined layer [user-def1] to PC board database exwir.pcb created by using technology name [layer6-PPBNPP].
1. Select Edit Technology from PCB Design/Manufacture Common Tool and add user-defined layer [user-def1] to [layer6-PPBNPP].
Click
Click Click
Click Register Noncond. Layer.
Add [user-def1].
2. In the CAD File Manager, first select the file set [exwir/[Board]], and then click (Plot Tool).
Clicking Execute button reflects the contents of technology name [layer6-PPBNPP] in the technology library on the PC board database.
If the contents of the technology used for the PC board in the technology library have been changed, execute the above operation.
Note
The PCB Technology/Component Update Tool also has two functions, [Update Technology data in PCB] and [Update footprint spec and part/package relationship] when it reflects new technology information on the PC board data:
[Update Technology data in PCB]
[Update footprint spec and part/package relationship]
In the [Update footprint spec and part/package relationship], following process can be performed. Reflecting footprint specification names all at once Deleting patterns connected to vacant pins Updating component shapes all at once
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PCB Technology/Component Update Tool The parameters of the PCB Technology/Component Update Tool are as follows: (1) PC Board/Design Rule Database Name
Set a PC board/design rule database name for which the technology is to be updated.
(1) (2) (3)
(2) Update Technology data in PCB

Specify whether the technology is updated or not. The number of conductive layers for the technology in the PC board is compared with the number of conductive layers in the technology library for the technology name set as the design rule, and [Add Layer], [Delete Layer] or [Change Layer Mapping] is displayed as Update Mode.
(3) Consider changing footprint spec and relation part with package
The footprint is updated in accordance with the priority of [FootPrint Spec Name] in the design rule. If a part name and a package name related to it are changed, the part information is updated. In addition, all the package information is updated.
Reference
An example of Changing footprint spec. will be given in [5. Changing Components] on page 2-56.
Moreover another item to be reflected when the technology is updated can also be specified by selecting Set Set Up Tool from the menu bar. (1) Keep the pattern which connects with the empty terminal
(1) (2) (3) (4) (5)

(2) Footprint update mode
Specify whether a wiring pattern connected to a vacant pin is saved or deleted. On Save Off Delete
Compare version Compares the version of the footprint in the footprint library with the version of the footprint on the PC board, and updates only the footprint in the newer library. Update All Updates all the footprints and padstacks in the PC board from CDB. Not update Does not perform updating from CDB.
(3) Keep in-component figure

Specify whether the shape edited on the PC board is saved as is, or returned to the shape of the library. Padstack or General Figure (Edited)* can be specified. *
Reference
General Figure (Edited) means figures in components, except component symbols and padstacks. These figures (lines and surfaces) can be edited on the PC board.
An example of Set Up Tool use is given in [5. Changing Components] on page 2-56.
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(4) Keep layer information

Layer commnet Specified whether save the layer comment edited in PC board or reflect the layer commnet edited and set in .technology edit tool to PC board. Save the layer comment in PC board : ON Reflect the layer comment in technology : OFF Even so Layer comment is ON, comment for layer that newly added is reflect from set in technology. Layer order Specified whether save the layer order edited in PC board or reflect the layer order edited and set in .technology edit tool to PC board. Save the layer order in PC board : ON Reflect the layer order in technology : OFF When Layer order is ON and added layer, align the existing layer then it adds to the bottom of the existing layer in a display order in technology.
Reference Reference
For the setting of layer comment in technology library, refer to [Master Training <PCB Design LIbrary>]. For the setting of layer comment in PC board, refer to [Master Training <PCB Design LIbrary>].
(5) Update relationship in component with changed footprint

Specify whether or not to update the information related to components updated in a footprint on the board. On......Update Off......Do not update
Reference
For details on the PC Technology/Component Update Tool, refer to the Online Help.
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Changing the Number of Conductive Layers (Editing Design Rules + Updating Technology)
To change the number of wiring layers in the PC board data when the PC board is being designed or completed, or to change the wiring layer attribute, the technology name of the PC board data is changed and information on the new technology is reflected from the technology library onto the PC board data.
If the technology name is changed because the number of wiring layers or the wiring layer attribute has been changed as illustrated above, change the technology name of the PC board data by using the design rule editor. The technology must be updated because changing only the technology name does not reflect information on the newly set technology onto the PC board data.
Example
To change a 4 layer technology [Star-4] to a 6 technology [Star-6] and then change the PC board data into that for the 6 technology:
1. From the CAD File Manager, click Rule Editor.
(Change Design Rule) to start the Design

Click list icon for technology name.
Click
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2. The confirm dialog for continue to change the technology name will display. Click OK.
At the time you change the techonology name, it will save the editing data. After you changed, you may not change back to before. Therefore it will display the confirm dialog.
Click
3. The technology names registered to the library will be listed. Select technology name: [Star-6] and click OK.
Click
4. When layer number is change, the confirme dialog will display as shown in left. Click OK. If the number of conductive layers is changed, a dialog that sets correspondence of layers before and after a change is opened. Change layer correspondence as necessary.
Click
The dialog shown on the left indicates that four layers are selected at present. After layers have been added, the highest and lowest layers are automatically assigned to the highest and lowest layers of six layers. However, the inside layers can be changed.
Caution
The highest and lowest layers cannot be added or deleted.
Changing the conductive layer assignment To assign the data for wiring Layer 2 to Layer 2 of the new wiring layer configuration
Click
Click
(1) Click [3] under New Cond. layer. (2) Click . After you done the setting, click OK.
Click
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5. Since layer is added, It checks for no non-set up item. Select Utilities Design Rule Check from the menu bar.
When the conductive layers are added, [Design Rule Stack] and [Wiring Width Stack] for the added layers are not set. Also in the dialog of setting a conductive layer, if the power plane layer was moved then set the net name for the power plane layer. Followed by above message, revise the each stack.
6. After setting unset parts, Save the PC Board Design Rule Editor and click File Exit Tool.
If the technology name has been changed, the dialog shown on the left is displayed and the PCB Technology/Component Update Tool can be started. Click Yes.
Click
The technology update tool will executed. Update Mode will be Add Conductive Layer.
Click
7. Click Execute.
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If the dialog shown on the left is displayed, click OK and check the contents.
Click
Because the number of wiring layer has been changed, the padstack used as the pin shape for the component and the land status for the padstack used as wiring via are normalized. Information that has been changed as a result of normalizing the land status is displayed as a warning message.
Click
This completes [Add Conductive Layer]. The procedure is the same for [Delete Wiring Layer], except that only for deletion is the parameter Set Delete Layer Data Forcibly of the PCB Technology/Component Update Tool referenced. * Delete Layer Data Forcibly Mode If a conductive layer or a non-conductive layer is deleted, an error occurs and processing cannot be performed if data exists in the layer to be deleted. To delete the layer forcibly even if data exists, From the menu bar in the PCB Technology/ Component Update Tool Set Delete Layer Data Forcibly : ON set and execute.
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5. Changing Components
Only the necessary component information on the PC board is copied from the CDB library by the Board Generation Tool, based on the net list (NDF) and design rule list (RUF).
New PC Board Generation Flow
When the contents of the CDB library have been changed, the information used to generate a new PC board database is different from the current information, the old component information on the PC board is left as unchanged. To update the component information on the PC board by using the information in the CDB library, the following two tools are used:
Component Update command from CDB PCB Technology/Component Update Tool
To copy a new component from the CDB library onto the PC board, use the following command:
Component copying command from CDB
To change the footprint specification name or the priority of the footprint specification name, use the following tool:
PCB Technology/Component Update Tool
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Reflecting Information in the CDB Library onto Component Information on the PC Board
Necessary component information is copied from the CDB library based on the net list and design rule list when a new PC board is generated and components are mapped. If a component is changed during designing and thus the CDB library is changed, the new component information must be reflected on the component information on the PC board.
To reflect the component information in the CDB library onto the components on the PC board, the following two tools are used:
Component Update command from CDB PCB Technology/Component Update Tool Component Update Command from CDB This command updates the component information currently existing in the PC board data by using the CDB library. Specify one piece of information to be updated for each library (part, package, or footprint library) at a time. Two or more pieces of information can also be specified at a time. Components placed on the PC board are also changed.
PCB Technology/Component Update Tool This tool is used to update information on the footprint library existing in the PC board data all at once by using a footprint name as the key.
FTP
FTP
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[Component Update Command from CDB] As an example, the component of a footprint is updated. 1. Select Utilities Update Component from CDB from the menu bar of an editor such as the Placement/Wiring Tool. 2. Select Footprint as [Kind:] as the information to be updated. 2 3
The following five types can be selected as Kind:
Part Package Footprint Padstack Pad
3. Type in a name to be displayed on the list to [Filter]. If * is input, all names are displayed.
[Version] compares the version number that is increased by one during CDB registration or updating with the information in the library and PC board, and lists only the version that satisfies the following condition:
Note
(Condition) Not specified Master > Local Master Local
Note
Master means the library and Local means the component information on the PC board.
Caution If Footprint is specified as Kind:, the PC Board Shape Edit Tool and Artwork Tool update only components that are not related to a net. Therefore, only the names of components that do not have pins, such as non-circuit components, are listed.
4. Select the name of the library to be updated from the name list. Some or all library names can be selected from the displayed data.
* Two or more library names can be specified by clicking the mouse button while holding down CTRL. the mouse button while holding down SHIFT specifies a range. Clicking
5. Select items as necessary.
The following items can be selected:
(Recursion Update) Updates the padstack/pad used for the footprint when a footprint is updated. (Options to update Footprint) Specifies whether information on the silk figures edited on the PC board or on swapping pads is to be left as is, or should be reset by updating from the CDB library. Check the figure to be saved (leave as is). (Options to Update Padstack/Pad) Keep Edited PadSpecifies whether the pad edited on the PC board is to be updated or not when a padstack/pad is edited. Keep Hole Type Specifies whether the hole-type is updated or not during padstack updating.
6. Click OK or Apply.
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[PCB Technology/Component Update Tool] 1. In the CAD File Manager, first select a PC board set name, and then click (Technology Update).
2. Click Set Set Up Tool on the menu bar.
Click
As necessary, specify [Footprint update mode] or [Keep in-component figure].
Reference For details on each tool, refer to [PCB Technology/Component Update Tool] on the page 2-50.
3. Click OK. A warning message indicating that a component area has been generated or one indicating that a padstack has been normalized may be displayed in the same manner as when the technology is updated.
Comparing Footprint Versions
If [Footprint update mode] in [PCB Technology & Component Update/Set Up Tool] displayed by selecting Tool Set Up Tool is set to [Compare version], the footprint to be updated can be checked before all components are updated at once. Select Confirm Compare Footprint Version from the menu bar.
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Components are newly copied from CDB (Component Copy from CDB)
The component and padstack pad to be placed in the layout area are copied from CDB to the PC board and then placed and input. The components described in the net list and the padstack pads used for those components are automatically copied when a new PC board is generated. To generate a component not related to the net list or a padstack pad not existing on the PC board, first execute [Copy Component from CDB].
1. Select Utilities Copy Component from CDB from the menu bar of an editor such as the Placement/Wiring Tool. 2. Select the information to be copied from [Kind]. 3 4 2
The following five types can be selected as Kind:
Part Package Footprint Padstack Pad
3. The footprint or padstack is an object of copy, then specify [Technology Name] to be referenced during copying. 4. Type in a name to be listed to [Filter]. If * is input, all names are listed.
5. Select the name of the library to be updated from the name list. Some or all library names can be selected from the displayed data.
* Two or more library names can be specified by clicking the mouse button while holding down CTRL. the mouse button while holding down SHIFT specifies a range. Clicking
6. Click OK or Apply.
The processing progress is displayed in the Query window.
Click
Click Close.
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Referencing Footprint Specification Name and Reflecting All Component Shapes at Once
Component information can be reflected onto the components on the PC board according to the priority of a footprint specification name. This section briefly explains how to use a footprint specification name. A footprint specification name is set to the CDB package information. The priority of the footprint specification name is defined in the design rule library and is reflected on the design rule database when a new PC board is generated and at the same time the footprint used in PC board is also decided by referencing the priority of the footprint specification name.
(Package information)
(Design rule)
For example, a footprint for high-density (specification name: High) and a footprint for low-density (specification name: Low) are set to Package A. Only a footprint (specification name: default) that can be used to design any PC board is set to the other components.
Specification name : Low Specification name : High
default
default
Prriority of footprint specification name: High > default
Referencing a footprint specification name and reflecting component shapes all at once is to change the shapes of the components on the PC board according to the priority of the footprint, if the priority of the footprint is changed as a result of editing the design rule.
Priority of footprint specification name : Low > default
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Change the priority of the footprint specification name to [High>default] and update the component information on the PC board. 1. In the CAD File Manager, first select the file set [PC board name/[Board]], and then
click
(Change Design Rule).

Click list icon for Footprint Spec Name.
Click
2. Change the priority of the footprint specification name.

Click [High] in [FootPrint Spec List] on the left column, then click Add>> button.
Click
With [High] selected, click
Click
Priority will sequentially increase from the top of the right column.
Click
Click OK.
Click
3. Checks the priority is attached to a footprint specification name. Click File Exit Tool.
Click
The Confirm dialog for saving will display. Click Yes.
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If a footprint specification name is changed, the dialog shown on the left is displayed and [PCB Technology/Component Update Tool] can be started.
Click
Click Yes.
The changed [High>default] will be displayed as [FootPrintSpec Name].
Click
4. Click Execute.
In the same manner as when the technology is updated, a warning message indicating that a component area has been generated or that a padstack has been normalized may be displayed. Checking Footprint Change History
If the shapes of components are changed all at once according to the priority of the footprint specification name, the information on the changed component can be checked by using the following command after execution of the PCB Technology/Component Update Tool. Click Confirm Changed Footprint List on the menu bar.
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Which Tool Should Be Used to Reflect CDB Changes?

[5. Changing Components] has explained the tools that reflect the changed information on the CDB onto the PC board database if the information in the CDB library has been changed. This section provides tables that summarize which tool should be used for what change. Refer to these tables when you do not know which tool should be used.
Library Name Part Changed Contents Number of pins, pin number, pin name Pin assignment Package name A B C Remarks Error [Different structure] occurs in [Update Component from CDB: Part]. Error [Different structure] occurs in [Update Component from CDB: Part]. Existing components are as those of the old package when only [Update Component from CDB: Package] is executed. Execute [Change Component: Change Footprint] after updating.
Stock code Attribute information (such as jumper and polarity) User-defined attribute Library Name Changed Contents

A
B
C
Remarks Existing components are as those of the old package when only [Update Component from CDB: Package] is executed. Execute [Change Component: Change Footprint] after updating. Able to specify whether each general figure and padstack pad is reset or not with [PCB Technology/Component Update Tool]. Existing components are as those of the old package when only [Update Component from CDB: Package] is executed. Execute [Change Component: Change Footprint] after updating. Able to specify whether each general figure and padstack pad is reset or not with [PCB Technology/Component Update Tool]. Existing components are as those of the old package when only [Update Component from CDB: Part] is executed. Execute [Change Component: Change Part] after updating. Able to specify whether each general figure and padstack pad is reset or not with [PCB Technology/Component Update Tool].
Package Footprint name (without specification name changed)
Default footprint (without specification name changed)
Addition or change of footprint specification name (priority of footprint specification name is changed by changing design rule)
Attribute information (such as package type, and body diameter) User-defined attribute

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Library Name Footprint
Changed Contents Footprint shape
A
B
C
Remarks Able to specify whether each general figure and padstack pad is reset or not with [Update Component from CDB: Footprint] and [PCB Technology/ Component Update Tool]. Error [Different structure] occurs in [Update Component from CDB: Footprint]. Error [Different structure] occurs in [Update Component from CDB: Footprint]. Use Recursion Update from [Update Component from CDB: Footprint].
Number of pins in footprint
Footprint pin number
Pad and padstack shapes used in footprint Mounted polarity, panel design attribute User-defined attribute Padstack Padstack shape Penetration Hole

Able to specify whether an edited shape is reset or not. Able to specify whether hole type is saved or not with [Update Component from CDB: Padstack Able to specify whether an edited shape is reset or not.
Plating Pad Pad shape

<Reflecting Tool>
Symbol in above Table A B C Forward Annotation Change Footprint Spec Name in PCB Technology/ Component Update Tool Tool Name Update Component from CDB
The meanings of marks in Columns A, B, and C in the above tables are as follows: : Reflects the object. : Stringed object is reflected onto the components on the PC board by executing [Change Component] command after [Update Component from CDB] command. : Does not reflect.
Reference These tables are also shown in Appendix A: Reflecting CDB Objects on PC Board Database, Board Designer Users Guide, Vol. 1.
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1. Divided Design
The PC board data created with Board Generation Tool can be divided into several blocks so that layout designing of each block can be carried out in parallel with the other blocks.
Sub-PCB: ex_b.pcb
Parent PCB: ex.pcb
Parent PCB: ex.pcb
Sub-PCB: ex_a.pcb
Dividing PC board Loading PC board blocks Expansion
Divided Designing
The following figure illustrates the flow of divided designing with Board Designer.
Parent PC board : MOTHER
Sub-PC board : MOTHER_a
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1. Divided Design
To divide designing, use [Divide], [Load Nesting] and [Expand] that can be selected by selecting [Divide] from the Placement/Wiring Tool. The following functions can be used:
Divide Provides commands that are mainly used for divided designing. Hierarchy Connector Generates a hierarchy connector that indicates connection points with the other divided PC board blocks at the boundary of the divided PC board area. Disp. Nets of Parent Board Specifies whether an unconnected net in the divided area that is expanded on the parent PC board is displayed or not. Update Updates and displays the current status if a divided sub-PC board is monitored or referenced or if a hierarchy connector is generated.
By using [Divide], execute divided designing in the following procedure. Execute the operation indicated in parentheses as necessary. Shown on the right below are the commands that must be executed.
Divided Designing Procedure
(1) Inputting divided area
Divide Generate an area (from panel menu).
(Generating hierarchy connector) Hierarchy Connector (2) Dividing PC board Divide PC board dividing command Divide PC board block loading command (Update Load Nesting & Hierarchy Connector)
Editing parent and sub-PC boards (Monitoring) (3) Loading sub-PC board
Divide PC board block loading command Divide Expanding command
(4) Expanding sub-PC board
The commands necessary for performing each process are explained below in accordance with the above flow.
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Inputting Divided Area

Specify which area in one PC board is to be divided.
Operation
1. Select Divide Divide from the menu bar on the Placement/Wiring Tool.
Click
Click Draw Area. Select Canvas. Selecting specification mode for divided area
Canvas....Specify the area to be divided in the form of a rectangle or a polygon. Group Area....If you generate a group area and use it as a divided area, specify the name of the group.
2. If [Canvas] is selected as the specification mode for the divided area, specify an area to be divided.
P1 X X P2
Click P1, P2, P3, P4, P5, and P6, and click Data End on the assist menu.
P5 X
P6
P4 X
X P3
Note
To generate any area as the divided area, specify an area with Canvas and specify Data End. To generate a group area as the divided area, select a group from the group name list displayed below Canvas.
Note
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1. Divided Design
Dividing the PC Board

Divide the data in the divided area into several blocks as sub-PC boards. You cannot proceed to the following operation unless you have selected Command End because Divide Divide used to specify a divided area is used.
Operation
1. Click Divide Divide on the menu bar of the Placement/Wiring Tool. 2. Click [Select Area/Nesting. 3. Select the area to be divided from the canvas by clicking. (Divide) on the panel menu 4. Click to divide the selected area.
The Divide dialog will be displayed. From Parent PCB
Divide An area in the object is deleted from the parent PC board.
Copy The object of the parent PC board is not changed.
To Sub-board
Click
Keep Land Status Divide the specified area keeping current land status.
Specifies processing if a sub-PC board with the same name exists. Overwrite Overwrites the sub-PC board to the existing sub-PC board file. Add Merges the sub-PC board with the existing sub-PC board file.
Base Point
Specifies the base point for the new PC board generated by dividing. This base point is used for nesting.
5. Click OK.
A divided PC board file (PCB/RUL) [PC-board-name_a] will be created in the same directory as the PC board (parent PC board) currently edited.
Naming rule for divided PC board

If Group Area is selected Component group name.pcb Example: GroupA.pcb If Canvas is selected Name of PC board being edited_a.pcb Example: ex_a.pcb _a, _b, and _c are appended in sequence.
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When you divide the PC board, it will normalize the land status of padstack. If this process changed land status, then the dialog for Normalize Land Status show in below will display.
If you do not wont to change the land toggle button on status, then click the the right-hand side of After Change cell of an object ID, and change to No Change.
Click
Divide work is an end above. The parameter of the panel menu of a divide command is descrived here. (Divide), the data to is controllable by setup of a panel menu. Before performing Also the parameter at the time of area data or divided data relativity move and rotate can be specified.
[Select Visible Layer] The layers set in visible layer are the objects of Divide. [Select Via] Via is an object of Divide. [Cut Mode] Specify the data that overlap the border line of divided area to be cut out or not. [Rlt.Distance] Relative movement is carried out by the coordinates (X Y) which specified the divided are or the nesting. [Rotate] Specify the rotation angle when rotating the nesting block or divided area in a drag. [Load Nesting] When specified nesting is already inputted, specify whether the information on a certain nesting is already updated, or it newly adds.
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[Object to Be Put on Divided PC board] The following objects are put on the divided PC boards by the Divide command:
1. PC board outline The divided sub-PC board is copied in the same shape as the parent PC board. Regardless of the mode selected, the outline of the parent PC board is not deleted or changed. 2. Layout area The layout area of the sub-PC board is copied in the same shape as the parent PC board. Regardless of the mode selected, the layout area of the parent PC board is not deleted or changed. 3. Component If all the objects in a component are included in the divided area, they are put on the divided PC board. After specifying a divided area, an object can be excluded from or included in division.
Reference For commands that exclude or include an object from or in a divided area after specifying the divided area, refer to [Editing Nesting Board] on page 3-13.
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Panel menu
4. Wiring pattern (via, line, area) Wiring via (Processing differs depending on whether [Select Via] is set to ON or OFF). [ON] Padstack center point will be put on the divided PC board if it is included in the divided area. [OFF] Via is not put on the divided PC board.
Wiring line (Processing differs depending on whether [Cut Mode/Line] is set to ON/OFF). [ON] A line straddling over the boundary of areas is cut at the boundary line and is put on the sub-PC board. [OFF] Only lines that are completely included in the area are put on the sub-PC board. A line straddling over the boundary of areas is not put on the sub-PC board.
Wiring area (Processing differs depending on whether [Cut Mode/Area] is set to ON/OFF). [ON] An area or constraints area straddling over the boundary of areas is cut at the boundary line and put on the sub-PC board. [OFF] Only an area or constraints area completely included in the area is put on the sub-PC board. An area or constraints area straddling over the boundary of the area is not put on the sub-PC board.
Note
Caution
5. Non-conductive layer object The line and area are treated in the same manner as the wiring line and wiring area above. The constraints area data is treated in the same manner as the wiring area. The other figures are treated as divided data if their shape is included in the divided area. In addition to the object, the following information is copied to the sub-PC board: Logical net Design rule
If a layout area has not been input on the parent PC board, it is not divided.
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Loading PC Board
When each sub-PC board has been designed, load the data for the sub-PC board to the parent PC board.
Operation
1. Open the parent PC board. Click Divide Divide on the menu bar for the Placement/Wiring Tool.
2. Click Select Area/Nesting. 3. By the Canvas, click the divided area from which the data of a sub-PC board is loaded to the parent PC board. Or, select a PC board block name from the list of PC board blocks. (Load Nesting) on the panel 4. Click menu to start dividing.
A technology connector will be displayed. If necessary make the layers of the parent PC board and sub-PC board correspond to each other. If the technology for the parent PC board and sub-PC board is the same, click OK.
Reference For details on the technology connector, refer to [*Technology Connector] on the next page.
Caution
An unconnected net that straddles over blocks is displayed in a dotted line. Because a PC board block holds only displayed data, DRC is not executed to each object. The status in which a PC board block is loaded cannot be retained. After loading a PC board block, be sure to execute PC board block editing command [Expand] so that the block becomes an object on the parent PC board. Then save the object.
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* Technology Connector The technology connector dialog is opened to make the layers of the parent PC board correspond to those of the sub-PC board when the sub-PC board is loaded to the parent PC board. If the layer configuration of the sub-PC board is identical to that of the parent PC board, there is no problem. If different, however, which layer of the sub-PC board is loaded to which layer of the parent PC board must be specified.
(1) Information on PC board being edited (parent PC board) (2) Information on PC board to be loaded (sub-PC board) (3) Indicates the connection status between PC board being edited (parent PC board) and PC board (sub-PC board) to be loaded. To the left and the right are the layers of the parent PC board and sub-PC board, respectively. (4) Of the layers of the PC board (sub-PC board) to be loaded, unconnected layers that are not assigned to the parent PC board are displayed.
(1)
(2)
(3)
(4)
<<Operation of Technology Connector>> Canceling layer connection between a PC board being edited and a PC board to be loaded
Click
Select the layer with a connection to be canceled from Display Connection Status and click Unconnect on the assist menu.
To assign and load an unconnected layer to a PC board layer being edited

Double-Click Click
Select a layer of connection destination from Display Connection Status and double-click the PC board layer (sub-PC board) to be loaded and connected to that layer from Unconnected Layers.
To exchange a connected layer with an unconnected layer

Click Click
Select a layer to be exchanged from Unconnected Layers and click the layer of exchange destination on Display Connection Status. Then click Exchange on the assist menu.
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1. Divided Design
[Load Nesting] only displays the design of the sub-PC board. This status is called [Monitor Reference]. Progress on the designing of the sub-PC board from the parent PC board can be checked by using this Monitor Reference. At this time, the sub-PC board data is not yet the parent PC board data. * Monitor Reference When monitoring and referencing the divided PC board by using [Load Nesting], the status when [Load Nesting] has been executed may be displayed even while designing of the parent and sub-PC boards progresses. In this case, select Divide Update Nesting Board from the menu bar. The status of the divided PC board will be updated to the current status.
Note
The parent PC board can also be monitored and referenced from the divided PC board. While monitoring and referencing the PC boards, it is possible to specify whether the unconnected nets of both the parent PC board and divided PC board are displayed or only the unconnected net of the divided PC board is displayed. Click Divide Disp. Nets of Parent Board on the menu bar.
(Displaying nets of parent and sub-PC boards)
(Displaying net of only sub-PC board)
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Chapter 3
1. Divided Design
Expanding Nesting Board

The divided PC board loaded to the parent PC board by [Load Nesting] is expanded to the data of the parent PC board. This operation can be executed immediately after [Load Nesting].
Operation
1. Select Divide Divide with the sub-PC board loaded to the parent PC board. 2. Click [Select Area/Nesting] under. 3. On the canvas, click the divided area from which the sub-PC board is to be loaded. Or, select a nesting board name from the nesting board list. 4. Click
(1)
Click
Click
(Expand) on the panel menu.
(1) Nets Specify a processing method if net names are in duplicate.

[Net name of component pins to be expanded] Merge Merges the same names as those of a series net. Divide Creates a new net name for the object to be expanded. A net name such as $BN00000 [number] will be created. [Net name of pattern to be expanded] Merge Merges the same names as those of a series net. A net name that does not exist at the expansion destination is assumed as that of a transient net. Divide Assumes the pattern of the same net of the component pin to be expanded as a new net ($BN00000 [number]) and the others as transient nets.
(2) (3)
(4) (5) (6) (7) (8)
(2) Groups
Specify a processing method if a group name is in duplicate. Merge Assumes a group name in duplicate is the same component group. Divide Assumes all the components in the object to be expanded are one group (specify a group name).
(3) Components
Specify whether a component expand or not. And when a component expand,specify a processing method if a component is in duplicate. Merge The gate ID of the component on the PC board to be expanded is not changed. If the gate ID is in duplicate, a new gate ID ($BF00000 [number]) is assigned. Divide Generates a new gate ID ($BF00000 [number]) as the gate ID of the component on the PC board to be expanded. In addition, generates a new reference name by adding the set value of the reference offset value. [Duplicated Comp.] Expand.......................................... Expand components with duplicated references. Expand (Delete Parent's Comp.).. If references have been duplicated, delete the component on the parent PC board. Not Expand................................... Do not expand components with duplicated references.
(4) Select Via

ON : Expands via. OFF : Does not expand via.
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1. Divided Design
(5) Lock Via Angle

ON : Lock the via angle for the child PCB. OFF : Not lock the via angle for the child PCB.
(6) Keep Land Staus

ON : Keep land status for the child PCB. OFF : Normalize land status for the child PCB.
Merge the surface data on the child and the parent. ON : Merge surface. OFF : Does not merge surface.
(7) Merge Area
(8) Hierarchy Connector

Parent Does not expand the hierarchy connector. Sub-PCB .. Deletes the hierarchy connector of the parent PC board being edited and expands the hierarchy connector of a PC board block.
Caution
If the design rule of the divided PC board has been changed, it is changed to the design rule of the parent PC board after expansion.
5. Click OK.
The data inside the child board will expand to the parent board.
When expanding it, the land status of the padstack is normalized. If the land status is changed as a result of this process, it is displayed in the list on the Normalize Land Staus dialog shown on the left. If you do not want to change the land status, toggle button on the then click the right-hand side of the After Change cell of an object ID, and change to No Change.
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Chapter 3
1. Divided Design
Editing Nesting Board

The [Divide] command has the following commands that can be used to edit the divided area and nesting boards:
Move/Rotate Revert to Original Point Delete Change Path Name Extract RUL Diff. Move Component to Nesting Board
[ Move/Rotate] A divided area or a nesting board can be moved or rotated.
Operation
1. Open the parent PC board with the Placement/Wiring Tool and select Divide Divide from the menu bar.
Click
2. Click Select Area/Nesting.
3. On the canvas, click the divided area from which a PC board is to be loaded.
4. Specify a rotation angle.
5. After you select the divided area to be moved or rotated, when you click Data End on the assist menu then the tool will change to the drag move mode. The point clicked when the divided area has been selected serves as the reference point for the destination. 6. When Rotate is selected from the assist menu, the selected divided area is rotated by the angle specified on the panel menu.
Click
Data End
Rotate
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1. Divided Design
[ Revert to Original Point] The divided area or the nesting board that has been moved or rotated is returned to the coordinate value or angle when the nesting board has been loaded.
Operation Panel menu
1. Select Divide Divide from the menu bar. Click Select Area/Nesting and select the divided area to be returned to the original coordinates or angle. 2. Click (Return to Original Point) on the panel.
Click
[ Delete] The divided area, nesting board, and hierarchy connectors are deleted.
1. Select Divide Divide from the menu bar. Click Select Area/Nesting and select the divided area to be deleted. 2. Select (Delete) from the panel menu.
The confirmation dialog shown on the left will be displayed. Click Yes.
Click
Reference
If the hierarchy connector is displayed, it is deleted. If a nesting board is displayed by monitoring, the nesting board is deleted. When a divided area is input or when a nesting board is expanded, the divided area is deleted. If all the above are displayed or generated, the hierarchy connectors, nesting board and divided area are deleted in that order.
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Chapter 3
1. Divided Design
[ Change Path Name] The PC board path name assigned to the divided area is changed. This operation is used when the file path for the divided PC board (PC board block) has been changed.
1. Select Divide Divide from the menu bar. Click Select Area/Nesting and select the divided area with a PC board path name to be changed. (Change Path Name) on the panel menu. 2. Click The File Selector dialog is displayed. 3. Select a divided PC board (PC board block name).
Click
[ Extract RUL Diff.] It is possible to check whether the design rules for the parent PC board and divided PC board (nesting board) are different on the Query window. The contents on this window can be output to a file.
1. Select Divide Divide from the menu bar. (Extract RUL Diff.) from the panel menu. 2. Click The File Selector dialog will be displayed.
Click
3. Select a divided PC board (nesting board name) on this dialog.
Information on difference will be displayed on the Query window. As necessary, the information can be saved to any file by Save As.
Caution
If the design rule for the divided PC board has been changed, it is changed to the design rule for the parent PC board after expansion. The difference in design rules can be checked in advance by looking at the list on the File Selector dialog.
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1. Divided Design
[ Move Component to PC board block] A component or figure specified on the parent PC board can be moved to the divided nesting board.
Operation
1. Select Divide Divide from the menu bar.
2. Click Select Comp. or Select Figure.

Click
3. On the canvas, select a component or figure to be moved to the nesting board. (Move/Copy to Board) from 4. Select the panel menu. Specify Move or Copy and click OK.
Click
Click
5. The File Selector dialog will be displayed. Select a file (PC board block) to which the component or figure is to be moved or copied.
Click
Click Yes on the confirmation dialog shown on the left.
Click
PC board block to which component or figure is to be moved or copied
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Chapter 3
1. Divided Design
In addition to the Divide Divide command that can be selected from the menu bar, the following operations related to divided designing can also be selected:
Selecting display mode for divided area Referencing information on divided area [ Selecting display mode for divided area] The display mode for the divided area can be changed by ON/OFF.
Change the checking for View Divided Area in the menu bar by ON/OFF.
Click
The condition of display the Divided Area as ON, can be change to Simple/Detail in Option dialog.
Click Environment Option from menu bar. Select Simple/Detail from pull down menu of [Block Area].
Simple ............. Displays the shape and PC board path name of the divided area. Detail ............... Displays the shape and PC board path name and, while a PC board is loaded, data in the PC board block. OFF ................. Does not display the divided area.
Operation
(Simple) (Detail) (OFF) [ Referencing information on divided area] The file path for the divided PC board (PC board block) can be referenced.
1. Select
(Query) from the tool bar.
Click
2. Select Block Area/Panel in Object Info from the menu bar and click the PC board block on the PC board.
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1. Divided Design
Generating Hierarchy Connector

Hierarchy connectors can be generated as necessary to perform divided designing. A hierarchy connector generates the points on each of the nets straddling over the parent PC board and sub-PC board at the boundary of the divided areas. When the parent PC board and sub-PC board are separately wired, they can be connected when [Expand] is executed by connecting them to these points. This hierarchy connector is generated after the divided areas have been input.
Reference Refer to [Divided Designing Procedure] on page 3-2.
Follow this procedure to generate hierarchy connectors automatically.

Operation
1. After inputting the divided areas, select Divide Hierarchy Port from the menu bar on the Placement/Wiring Tool. Mode
Rough Route ..... Specifies a rough route for an unconnected net straddling the divided area specified by Select Area and the parent PC board. Select Area ........ Selects a divided area in which the hierarchy port is to be generated.
Angle
Specifies an angle at which the rough route is to be input.
Non-Generated Nets
Highlights and displays unconnected nets for which a hierarchy port is not generated.
2. Click [Select Area] on the panel menu. 3. Click the divided area. 4. Click the Create from the panel menu.
Click
Click
The Target dialog will be displayed. Select Unconnected Nets and click OK. A hierarchy connector will be generated.
Click
Hierarchy connector
Click
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Chapter 3
1. Divided Design
Follow this procedure to specify a rough route and generate a hierarchy connector.
1. After inputting the divided area, select Divide Hierarchy Connector from the menu bar on the Placement/Wiring Tool. 2. Select [Select Area] from the panel menu and click the divided area. 3. Select [Rough Route] from the panel menu.
P1
4. Specify unconnected nets for which a rough route is to be generated, P1 and P2. A hierarchy connector will be generated for the unconnected nets in an area specified by P1 and P2.
P2
P2
P1
5. The specified nets will be bundled into one. Then specify Rough Route (P1 and P2). 6. After inputting the rough route, click Data End.
7. Click Create on the panel menu. 8. Select Rough Route and click OK.
Click
Click
After the hierarchy connector has been generated, execute [Divide].
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1. Divided Design
Editing Hierarchy Connector

The hierarchy connector that has been generated can be edited as follows:
Moving hierarchy connector Updating hierarchy connector Deleting hierarchy connector (Refer to Delete on page 3-14.) [ Moving Hierarchy Connector] Move the hierarchy connector. 1. Click (move) from the tool bar. 2. Select Drag. from the panel menu. 3. Click Lock Hierarchy Connector from the panel menu. 4. Specify a hierarchy connector using P1 and the destination using P2.
P2 X
P1
Note
If you set Lock Hierarchy Connector as ON, then it only cam move on the border line of divide.
[ Updating Hierarchy Connector] The hierarchy connector moved on the parent PC board can be reflected on the divided PC board or vice versa. 1. In the monitor and reference status, select Divide Reload Hierarchy Connector from the menu bar on the Placement/Wiring Tool.
The confirmation dialog shown on the left will be displayed. Clicking OK updates the hierarchy connector.
Click
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Chapter 3
2. Designing by Reuse
An existing schematic diagram and PC board data created with that schematic diagram can be reused to design other new PC board.
Designing by Reuse
The following figure illustrates the flow of design reuse by Board Designer.
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For designing by reuse, the PC board to be reused is loaded by using [Divide] in the Placement/Wiring Tool, in the same manner as divided designing. The following [Divide] menu functions are used for designing by reuse.
Divide (Board) . Executes loading and expansion of a reused PC board. Disp. Nets of Parent Board . Specifies whether to display an unconnected net in the divided area expanded on the parent PC board.
To use designing by reuse, input information on the PC board and components to be reused by using the System Designer, and create new PC board data by using the net list and design rule list output by the System Designer.
Work Procedure for Designing by Reuse
(1) Drawing a schematic diagram
Copy & Paste on the System Designer
Generating new PC board
(2) Loading PC board to be reused
Divide Command that loads PC board block to be reused
Editing PC board
[2. Designing by Reuse] explains how to input a circuit with the System Designer and how to load a PC board to be reused in designing a new PC board.
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Chapter 3
Inputting a Schematic Diagram for Designing by Reuse

A new schematic diagram can be created by reusing an existing schematic diagram. As an example, it is assumed that the name of the existing schematic diagram is SD-sasmple.cir, and that a PC board has already been completed based on this schematic diagram. PC board data name is BD-sample.pcb The operation to create a new PC board data [New/[Board]], by reusing SD-sample/ BD-sample, is explained below.
Operation
1. Start System Designer.
Open the schematic diagram [SD-sample] to be reused.
2. Select the circuit block (component, net) and copy it to be reused to the buffer. Select Edit Buffer Copy 1 from the menu bar. (Any of buffers 1 through 5 may be selected.)
X P2 IC4 CN6 P1 X P1 X IC6 IC8
P2
3. Create a new schematic diagram (New). 4. Open the copied schematic diagram [New.cir] and select Edit Buffer Paste 1 from the menu bar.
5. Change the component named [CN6] on the schematic diagram of the copy source to [CN600] at the copy destination (New). (Similarly, change [IC4] [IC400],. [IC6] [IC600],. [IC8] [IC800],.)
After changing the reference, scroll down the attribute changing dialog. The following attributes will be found.
Re-used Filename Re-used Reference
Note
SD-sample CN6
*These attributes are key items when executing [Load Reused Block Template].
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6. Finish the schematic diagram (New).
Designing by Reuse
Next, prepare the divide data.
7. Rename the reused PC board file name [BD-sample] to the original reuse schematic diagram base name [SD-sample]. In the reused design, original PC board base name and schematic diagram base name need to be the same. After you change the PC board file name, please check the original reuse PC board data.
IC8 CN6 IC6 IC4
Show as in left diagram reuse wired PC baord. Reuse components are [CN6], [IC4], [IC6], and [IC8].
8. From the schematic diagram data [New] that generated in 6., output net list and design rule list then generate the PC board data [New] by Board Generation Tool.
Input the PC board shape and layout area, then put the components to outside of PC board shape by Stack Components.
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Chapter 3
9 Select Divide Divide from the menu bar on the Placement/Wiring Tool. (Load Reused Block Template) from the panel menu and select the 10. Click original PC board data [SD-sample].
(1) Reused Board
Specify a PC board to be reused. The name of the PC board is the name set to component attribute: the name specified in [Reused file name] on the schematic diagram.
(2) (3) (4)
(1)
(2) Change Directory Path

Change the path of the PC board to be reused. By default, the displayed pathname of reused PC board data name [SD-sample.pcb] is the same as the one of the opened PC board data (reuse destination of PC board data). If the reused PC board data exists in a deferent directory then please change the directory.
(3) Comp. Info.

Correspondence between the reference of the components on the PC board to be reused and the reference of the components on the PC board currently edited can be referenced.
(4)Replace Components
Specify whether components are placed at the original position on the PC board reused or not when the reused PC board is expanded. The reference set to component attribute: [Reference to be reused] on the schematic diagram is the key to the correspondence between the original components and current components.
11. After confirming the reused PC board and component information, click OK on the [Load Reused Block Template] dialog.
Technology Connector will be displayed. If necessary, make the layers for the parent PC board correspond to the layers for the sub-PC board. If the technologies for the parent PC board and sub-PC board are the same, click OK.
Click
Reference For Technology Connector, refer to [*Technology Connector] on page 3-9.
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12. From the reused PC board, components and wiring data will be input.
In this status, the data are not those of the PC board currently edited. In this status, the reused PC board can be moved or rotated in a similar manner to divided designing.
Reference On how to move or rotate a PC board, refer to [
Editing Nesting Board] on page 3-13.
Expanding a Reused PC Board

The PC board loaded by Load Reused Block Template is expanded to the PC board data being edited. The way to expand it is same as divided design.
13. Click Select Area/Nesting from the panel menu. 14. On the canvas, click the PC board block to be reused. Or, select a PC board block name from the list of PC board blocks. 15. Click (Expand) on the panel menu.
Load Reused Block Template Dialog
If Replace Components is checked on the [Load Reused Block Template] dialog, components in reuse point [CN600], [IC400], [IC600], and [IC800] are replaced in the specified coordinates as shown below.
If the Replace Components is OFF then only wiring patterns other than components will be expanded.
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Chapter 3
3. Designing Build-up PC Board

Board Designer offers commands useful in designing a build-up PC board. This section explains these commands and the design rules related to designing a build-up PC board.
A build-up PC board can be designed in the same way as an ordinary PC board. In addition, however, a padstack used for build-up via must be registered and build-up via for the design rule and each clearance value must be set. The points to pay attention to when designing a build-up PC board are indicated below.
Design Process for Build-up PC Board
Registering CDB library
Registering build-up via
Registering technology library
Registering design rule library
Defining via specification and build-up via to be used
Generating PC board database
Inputting PC board outline, etc.
Placing components
Wiring
Generating and editing build-up via Drill output of build-up via
Output
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Registering Build-up Via

Register build-up via by using the Padstack Editor. An important point in registering padstack that is used as build-up via is to set the following attribute:
Build-up via attribute

Start the Padstack Editor.
ON
Set [Buildup Via attr.] to [ON].
Registering Design Rules for a Build-up PC Board

The following items in the design rule library are related to build-up PC boards: Core Layer (Board Spec) Interstitial Via, Qualified Padstack (Via/Area Spec) Buildup Via Clearance (Wiring Clearance)
(Board Spec Core Layer)
(Wiring Clearance Via Hole Clearance)
(Via/Area Spec Interstitial Via, Qualified Padstack)
(Wiring Clearance Rule Unit)
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Chapter 3
[ Core Layer] Set From-to for the core layer of the build-up PC board. This item is referenced when build-up via is generated. Click PCB Design/Manufacture Common Tool Edit Design Rules to start the design rule library edit tool.
From the Board Spec tab, set Core Layer as ON and set a value for From-To.
[ Drill Rule] Specify internal via. To limit the interstitial layer of the input via, set Layer Combi. Limit. as ON. From the Via/Area Spec tab, set Enable Interstitial Via as ON. To limit the input layer of the interstitial via, set Layer Combi. Limit. as ON.
If Layer Combi. Limit. is set as ON, click Register Layer Combination of Via and specify the From-to for the layer to which via can be input.
Click
[ Via/Area Spec : Qualified Padstack] Set [Qualified Padstack] when a different padstack is used for each From-to.
By clicking Add/Delete Padstack, padstack can be added by referencing the combination list set by Register Layer Combination of Via above.
Click
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[ Wiring Clearance : Via Hole Clearance] Padstack that has buildup via attribute will refer the clearance vaule in [Buildup Via] item for via hole clearance.
[ Wiring Clearance : Design Rule Unit] Padstack that has buildup via attribute will refer the clearance vaule in [Buildup Via] item for each clearance in design rule unit.
Useful Commands for a Build-up PC Board

This section introduces the Board Designer commands that are useful in designing a build-up PC board.
Generating build-up via Merging via Dividing via Removing antenna via Area DRC ( Editing 3D via Build-up basic module is necessary.) [ Generating build-up via] The following via is generated during wiring.
Staccato Via
Spiral Via
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Chapter 3
Select Edit Input Wire from the menu bar in the Placement/Wiring Tool.
From the panel munu set Buildup Via as ON.
Click Parameters and set the parameters used to generate build-up via.
The parameters are explained on the next page.
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Buildup Via
Specify a padstack to be used as build-up via. (If omitted, refer to Padstack Used.)
Skip Via
Specifies whether skip via is generated or not. (Skip via cannot be generated if Interstitial Via Combination Limit is selected and if the combination of skip via is not set for Register Layer Combination of Via.)
Core Layer
Specifies a core layer. (Specify [Rule] if a design rule is set.)
Pattern Length
Refer to the above figure. can be specified. A pattern length that is common to all layers or peculiar to each layer
Search Via
Search via cannot be generated if a DRC error occurs when build-up via is generated. If [Search Via] is selected from the panel menu, search via is generated where possible on the [Search Grid] specified in an area by the parameter [Search Radius].
Search grid
The build-up via is generated when the Active Layer is changed.
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Chapter 3
[ Merging via] Divided via existing at the same point or within a specified permissible value is merged into one via.
Caution Via cannot be merged if the result of merging violates Layer Combi. Limt. In the Via /Area Spec menu.
Select Edit Post-wiring Process from the menu bar in the Placement/Wiring Tool.
Select [Merge Via] from [Padstack] on the panel menu.
Click via existing on the same point, such as 1-2 and 2-3, as shown below.
Click
Via will be changed (merged) to via for 1-3.
Parameter
Click Parameter on the panel menu. Set a value to [Merge Tolerance] for Padstack on the displayed parameter dialog. Even via that does not exist on the same point can be merged.
Merge tolerance
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[ Dividing via] Via at which a DRC error occurs can be divided and moved as shown below so that the clearance can be maintained.
Caution
Via cannot be divided if the result of dividing violates Layer Combi. Limit. in Via/Area Spec. In the above example, a DRC error occurs on the pattern and via for Layer 4. In this case, layers above and below the layer where the error occurred (i.e., layers 3 and 5) are moved. Next, the message Violate Interstitial Via Limitation is displayed and via cannot be divided unless combinations 1-3, (or 1-2 and 2-3), 3-5, and 5-6 do not exist in Layer Combi. Limit..
Select Edit Post-wiring Process from the menu bar in the Placement/Wiring Tool.
Select [Divide Via] for [Padstack] on the panel menu.
Click a via.
Click
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Chapter 3
[ Removing antenna via] Antenna via like that shown below is deleted.
Caution The antenna cannot be deleted if the result of deleting violates Layer Combi. Limt. in Via /Area Spec menu
Select Edit Post-wiring Process from the menu bar of the Placement/Wiring Tool.
From the panel menu select [Remove Antenna Via].
Click an object of via.
Click
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[ Area DRC] The following via can be checked with Area DRC: Board specifications (inner via limitation, build-up via layer) Special via (antenna via, loop via, divided via) Board specifications [Inner Via] A check for whether Layer Combi. Limit. in Via/Area Spec menu is violated. Also it could find out the via that violated Qualified Padstack and Available Padstack.
[Buildup Via Layer] A check for whether build-up via exists on a layer specified as From-to in the core layer of the Board Spec.
Special via The following via is detected.
Caution
For information on how antenna via is detected, refer to Layer Combi.Limt. of Via/Area Spec.
Reference For details, refer to the Online Help.
Select Check Area DRC from the menu bar in the Placement/Wiring Tool.
Click DRC Sub Dialog on the panel menu and set the necessary checks to ON.
Execute Area DRC. DRC error marks If an error occurs as a result of the above check, the following error marks are displayed:
Inner Via Violate Qualified Padstack Buildup Via Layer DRC [from-to] DRC [qualifiedPadstack] DRC [buildupvia-layer] Antenna Via Loop Via Divided Via DRC [antenna-via] DRC [loop-via] DRC [divided-via]
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Chapter 3
Edit Via on 3D] (A Z0538 license is necessary for this option tool.) Buildup vias can be moved or merged by using the 3D editor.
Select Edit Edit Via on 3D from the menu bar in the Placement/Wiring Tool. The build-up via can be moved, divided, and merged in the editor for Edit Via on 3D.
Drill Output of Build-up Via

After designing a build-up PC board, execute output (CAM output). At this time, pay particular attention to the output layer during drill output.
Example
As an example, this section introduces drill output of a build-up PC board with the following via specifications. Layer combination specifications 12 13 23 36 67 68 78
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In this example, the drill process is divided into the following five steps:
Layer Build-up Layer 1 Build-up Layer 2 Core Layer 3-6 Build-up Layer 7 Build-up Layer 8 Step Name Build 1 Build 2 Core 3-6 Build 7 Build 8
[Setting Drill Process with Build1]

[Layer]: [Specified From-To]: Cover Hole WIR(1)-WIR(2)
Holes 1 - 2 and 1 - 3 are output with the above setting.
[Setting Drill Process with Build2]

[Layer]: [Specified From-To]: Cover Hole WIR(2)-WIR(3)
Holes 1 - 3 and 2 -3 are output with the above setting.
[Setting Drill Process with Core 3-6]

[Layer]: [Specified From-To]: From-To Hole WIR(3)-WIR(6)
Only holes 3 - 6 are output with the above setting.
[Build7] specifies [WIR(6)-WIR(7)] for [Hole Including Specified Inner Layer], like [Build1]. Similarly, [Build8] specifies [WIR(7)-WIR(8)] for [Hole Including Specified Inner Layer].
Reference For details on drill output, refer to [Master Training <CAM>].
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Chapter 3
4. Placing Jumper
A jumper can be generated in the middle of wiring.
Usually, jumpers should be defined at the preparatory stage, placing as many jumpers as necessary.
Generation Process of Jumper
Registering jumper components
Defining jumper components
Placing components
Placing jumpers
Wiring
Wiring of jumpers
Output
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4. Placing Jumper
Registering Jumper Components

Register jumpers in the same manner as other components, by using each library registration tool in the CDB. The point of when you register a jumper component is set [Jumper] in part information as ON.
Setting [Part Information] to [Jumper]

Operation
1. Register the shape of the jumper component with the Footprint Editor.
2. Register the package information on the jumper component with the Package Editor. Register jumpers of different pitches to separate footprints as shown on the left. They should be set as package information. The pitch can then be changed by selecting Edit Change Pitch.
3. Register part information on the jumper component with the Part Editor. Set Jumper in Log/Attribute tab as ON.
Jumper
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Chapter 3
4. Placing Jumper
Next is register a jumper has more than three pins. For the jumper has more than three pins, registered it as Function Pin Assignment Part. Register a Function as just one pin, and for the Pin Assignment set all pins to connect to same function.
Set with pin assignment for Jumper has more than three pins
Operation
Follow is register a jumper has more than three pins. 1. Register the shape of the jumper component with the Footprint Editor.
2. Register the package information on the jumper component with the Package Editor.
3. Register the function information of the jumper component with the Function Editor.
Register a just one pin in function registration as shown on the left.
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4. Placing Jumper
4. Register the pin assign information of the jumper component with the Pin Assignment Editor.
Register all pin assign to same function in pin assignment registration as shown on the left.
5. Register the part information of the jumper component with the Part Editor. Set Jumper in the Log/Attribute tab to ON.
Jumper
There is a two way to generate a jumper component on the PC board.
From menu bar of Placement/Wiring Tool, input by Edit Add Component. From the Input Wire in Placement/Wiring Tool, generate jumper.
Note
The component that could generate as jumper in Input Wire is part is jumper component, two pins component, and use padstack as pin.
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Chapter 3
4. Placing Jumper
Defining the Jumper Component

To copy jumper components to the PC board database, define the part names of the jumper components in advance using the design rule library.
Operation
1. Click Comp. Objects in the Design Rule Library Editor.
Click
Click
2. From the Jumper tab, define the part name of the jumper component on the Assign Components dialog.
Click the list icon and select the necessary jumper component from Part Name List.
The part names of the jumpers defined in the part library will be listed.
Click Click
Repeat the above operations for the necessary number of jumpers.
When setting has been completed, save it and end the Design Rule Library Editor.
Note
If a jumper is necessary after designing has been started, copy a jumper component directly from the CDB library, instead of the Assign Components dialog.(1) Or from the PC Board Design Rule Edit that is executed while you open the PC board file, defined the jumper with the same operation described in the above. The jumper will be automatically copied from CDB library.(2) (1) Copy the jumper component by selecting Utilities Copy Component from CDB from the menu bar. (2) Defined the jumper component and copy it to PC board by executed Design Rule Library Editor from Module Edit Design Rules in the menu bar.
Caution
Jumpers cannot be defined in the Design Rule Editor if it is started from the CAD File Manager.
Chapter 3
3 - 43
4. Placing Jumper
Placing a Jumper
Operation
Place the jumper by using the Floor Planner or the Add Component command in the Placement/Wiring Tool. 1. Move to the Floor Plan or Placement/Wiring Tool.
2. Click Edit Add Component on the menu bar.

Set Jumper as Component Type.
Specify the part name of the jumper to be generated as Part Name.
Specify a reference for Ref-Des. Specify an angle and side when placing the jumper.
3. Specify one point on the canvas.
* Changing Pitch
If the part names and stock codes are the same but only the pin pitch is different, the pitch of an already placed component can be changed by defining two or more footprints in one package and by using the Change Pitch or the Move Wire command.
Registering package
JUMPER10
JUMPER20
Changing pitch
10mm
Reference
For details on the commands, refer to Master Training <PCB design>.
20mm
Moving Wire
Click the pin on the jumper and drag it.

Click
10mm
20mm
3 - 44
Chapter 3
4. Placing Jumper
Wiring Jumper
When a jumper generated, it does not belong to any net. The jumper belongs to a net when a pattern is drawn to the jumper.
Operation
1. Click
X P1 P2 X X P3
(Input Wire) on the tool bar.
2. Specify a wiring route in the following procedure:

Jumper
Caution
Wire the jumper from a figure with a net.
A jumper can be generated in the middle of wiring.

Operation Parameter
1. Click
(Input Wire) on the tool bar.
2. Display parameters from the panel menu and click the part name of the jumper.
Click
3. Wire the jumper. In doing so, select Generate Jumper from the assist menu.
X X X
Click
X X
Note Note
When single layer PC board (2 layer PC board), the jumper will be generated by double-click. An unnecessary jumper component can be deleted by connecting the pins of the jumper component that has been generated by the Input Wire command with a line pattern. P1 X P2 X
Chapter 3
3 - 45
5. Placing Decoupling Capacitor

A decoupling capacitor can be automatically generated and placed during designing.
The following procedure is used to generate decoupling capacitors.

Generating decoupling capacitors
Schematic design (System Designer) CDB Library registration
Placement group settings
Decoupling capacitor component registration
Technology Library registration
Design Rule Library registration
PC board database generation
Attribute passing checks
Input of PC board outlines and other information Executing Placement
Placing Components
Wiring
Output
3 - 46
Chapter 3
Setting Placement Groups

When carrying out schematic design in System Designer, set decoupling capacitors and IC components you want to place close together in "placement groups."
Operation
1. In the Schematic Editor, in Change Attribute for the IC components, set "Placement Group Name."
Double click
2. Set the same "Placement Group Name" as in step 1 to the decoupling capacitor you want to place near it.
Double click
Chapter 3
3 - 47
Registering Decoupling Capacitor

Register decoupling capacitors to each library in the CDB. Two-pin components can be registered as decoupling capacitors.
Operation
1. Register the component shape of a decoupling capacitor with the Footprint Editor.
2. Register the package information on the decoupling capacitor with the Package Editor.
3. Register the part information on k decoupling capacitor with the Part Editor.
Note
No special definition for decoupling capacitor is necessary.
3 - 48
Chapter 3
Attribute Passing Checks

When board generation has finished, you can check the settings for the placement group name in the Design Rule Editor for the PC board.
Operation
1. Click Comp. Objects in the Design Rule Editor.
Click
2. You can check the IC components and decoupling capacitors you set in the circuit have been passed the "Placement Group Name" attribute.
Chapter 3
3 - 49
Executing Placement
In the Placement/Wiring Tool, decoupling capacitors are automatically placed near IC components for which you have specified a placement group.
Operation
1. Place the IC component.
2. Holding down the Shift key, click the component for which you want to generate a decoupling capacitor. 3. From the panel menu, specify the placement side for the decoupling capacitor, and click (Place Decoupling Capacitor). Decoupling capacitor placed
Panel menu settings
Click
Executing placement components in placement group
3 - 50
Chapter 3
Note
Carry out the following procedure to generate decoupling capacitors and place them near to IC components in a batch in Board Designer, without using System Designer.
CDB Library registration
Decoupling capacitor component registration
Technology Library registration
Design Rule Library registration
Defining decoupling capacitor components
PC board database generation
Input of PC board outlines and other information Placing Components
Decoupling capacitor generation Defining decoupling capacitor placement priorities Batch placement of decoupling capacitors
Wiring
Output
Reference
For details, refer to the online help.
Chapter 3
3 - 51
6. Design with Different Rule for Each Constraints Area

You may design with setting an exclusive rule to specific constraints area in PC board. In Board Designer, the constraints area with different rule is called Rules By Area.
default clearance default wiring width : 0.2 : 0.5
clearance : 0.1
wiring width : 0.5
A design with rules by area is in the following procedure:

Generation Procedure
Defining rules by area
Defining exclusive rule
Placing components
Inputting rules by area
Wiring
Design with consider of rules by area
Output
3 - 52
Chapter 3
Defining Rules By Area

In the technology library, define the exclusive layer for inputting a rules by area.
Operation
1. Set Set RulesByArea to ON, from the menu bar on the Technology Setup Tool.
Click
2. Generate a new PC board with using a technology that defined in Step 1. The Rules By Area will be set to the generated PC board.
Note
If you notice that a rules by area is necessary after starting designing, you may add rules by area to the PC board in the PCB Technology/Component Update Tool.
If you wish to reflect only setting for rules by area layer, execute only [Update Technology data in PCB].
Reference For details on PCB Technology/Component Update Tool, refer to [PCB Technology/Component Update Tool] on page 2-50.
Chapter 3
3 - 53
Inputting Rules By Area

Input a rules by area on a PC board. A rules by area can be input in any time such as immediately after generating a PC board and after placing components.
Operation
1. Click Input RulesByArea from the menu bar.
Set the shape of inputting constraint area.
Set the rule made to apply to the rules by area that inputting.
2. Input a rules by area.
X P2
X P4
P3 X
P1 X
Caution
Before you input rules by area, you need to have [design rule stack]/[wiring stack] for the rules by area that you wish to input.
Note
The way to execute the command for inputting a rules by area in the Floor Planner or the Placement/Wiring Tool are different from the tool above.
1. Click Utilities Input/Edit Toolbox on the menu bar.
2. Click
(Input RulesByArea) on the icon.
Operations after the command execution are the same.

Reference
For Input/Edit Toolbox, refer to online help.
3 - 54
Chapter 3
Rule that settable for rules by area In the rules by area you may set different rule for each default, but there are effective and not effective one.
Settable Rule Design Rule Stack Wiring Width Stack Default Padstack Qualified Padstack Effect/Not Effect Effect Effect Not Effect Not Effect
Caution
The items that are set as not effect are prepared in consideration of support in the future version. careful, when you set it.
Please be
Rules by area for conductive layers When you input rules by area, you may set the layer that input rules by area to be effective.
Effective on Single Lay [ON] Applied to specified conductive layer Effective on Single Lay [OFF] Applied to all layer
Chapter 3
3 - 55
Designing with Rules By Area

Input rules by areas are referenced in various cases. The following explains designing with rules by areas.
[Consider with rules by area (wiring width stack)]

Operation
1. Click Edit Input Wire from the menu bar then click Parameter.
Set the Wiring Width(RulesByArea) as ON.
2. Inputting a wiring.
P2 P1 X X P3 X X P4 X P6 X P5
It is automatically changed into default wiring width from P5 over rules by area.
Note
If a wiring pattern goes over the boundary line of rules by area then rule is not effective from next construction point (segment).
Out of rules by area Inside a rules by area
P2 X P4 X P3 X
P1 X
Not effect Effect
3 - 56
Chapter 3
[Input wiring with considering the rules by area]

Operation
1. Click Edit Input Wire from the menu bar to input wire
P2 X P3 X P5 X P1 X
Clearance : 0.3 P6 X
X P4
A wiring input is performed in consideration of rules by area. (design rule stack)
Clearance : 0.2
[Move wire with considering the rules by area] 1. Click Edit Move Wire from the menu bar to move the wire.
P1 X
P2 X
Caution
When you move the wire, if the spread mode is set to Jog or No Jog, rules by area is not referenced and default design rule stack is referenced.
2. Set Wiring Width(RulesByArea) to ON from the panel menu to move the wire.
Click
P1 X
In consideration of rules by area, wiring movement cannot be performed at the time of a DRC error.
Chapter 3
3 - 57
[Change the wiring width with considering the rules by area(wiring width stack)] 1. Click Edit Post-wiring Process from the menu bar. Set the following from the panel menu.
Click
Mode Target
: Change : Wiring Width
Click
Click
Click Parameter. Change to Pattern Width.
2. Select target patterns.
It is changed into the wiring width in consideration of rules by area bordering on the boundary line of rules by area.
3 - 58
Chapter 3
* Make Figure Into Component for Rules by Area As the purpose of using rules by area, rules by area may be input around the specific components to design with a special rule. If you move the components after you input the rules by area, you need to move the rules by area also with it.
Rules by Area will not follow the component.
Therefore, make input rules by area as component, and rules by area will follow the component.
1. Click Edit Make Figure Into Component from the menu bar of the Artwork Tool. Click Make Figure into Component.
Click
Click
Click
Click the target of component and rules by area that will be made into component. Click Data End from the assist menu.
2. If you move the component that was made into component, the rules by area follows it.
Click
Click
Chapter 3
3 - 59
7. Organizing the CDB

With Board Designer, operations on the component shape used for designing a PC board can be broadly classified into the following two:
1. Operation of layer mapping 2. Operation of other footprint (operation of footprint specification name) [1. Operation of Layer Mapping] Operation of layer mapping is to determine correspondence between each shape of the component on the PC board and each layer of the PCB, by using each technology of the technology library that determines correspondence between footprint layers and PCB layers. (Merit) By using Operation of layer mapping, a layer for each customer can be created for one footprint if the silk shape of the same component must be changed because the customer is different.
In addition, operation of layer mapping can also be used even if the pad shape of a conductor or resist is different when the same component is used with different PC board specifications.
3 - 60
Chapter 3
[2. Operation of Other Footprint (Operation of Footprint Specification Name)] Operation of other footprint (operation of footprint specification name) is to register a component shape to each footprint and set a footprint specification name when the pin reference points for the same components differ because of a difference in soldering method. This operation is to define the priority of the footprint specification name by the design rule and to determine the necessary component shape. (Merit) This operation is used for the same components with different pin reference points. If the pin reference point is different, two or more reference points cannot be set for each pin in one footprint in accordance with the usage. Therefore, operation of layer mapping cannot be used. In this case, operation of other footprint is used. This operation also simplifies management of footprint layers.
Board Designer can cope with various cases by using operation of layer mapping and operation of other footprint (operation of footprint specification name) in combination.
Chapter 3
3 - 61
Operation of Layer Mapping

This section introduces the specific procedure for operation of layer mapping.
1. 2. 3. 4.
Defining footprint layer Registering padstack Registering footprint Registering technology (defining layer mapping)
[1. Defining footprint layer] A footprint layer can be prepared to which component information that can be used for various PC boards can be input without depending on the number of layers and specifications of the PC board.
Operation
1. Select Tools Define Footprint Layer from the menu bar for the Components Manager.
[2. Registering padstack] Register figures that can be the pin shape of a component to a padstack.
3 - 62
Chapter 3
[3. Registering footprint] By using the padstack registered in 2 above, register a component shape as a footprint.
[4. Registering technology (defining layer mapping)] Set correspondence of layers (layer mapping) between the footprint layer and the PCB layer prepared in 1.
The points for operation of layer mapping have been introduced above. The operation and point for Operation of Other Footprint is described on the next page.
Chapter 3
3 - 63
Operation of Other Footprint (Operation of Footprint Specification Name)

This section introduces the specific procedure for operation of other footprint" (operation of footprint specification name).
1. Registering footprint 2. Registering package information (defining footprint specification name) 3. Defining priority of footprint specification name as design rules [1. Registering footprint] Register a footprint as another footprint in accordance with the soldering condition.
(CHIP2014-Flow)
(CHIP2014-Flow)
[2. Registering package information (defining footprint specification name)] Assign two or more footprints to one piece of package information. At this time, set a footprint specification name to each footprint.
[3. Defining priority of footprint specification name in design rules] Set the priority of the footprint specification name in a design rule.
Click the list icon for Footpirnt Spec Name.
Priority is highest at the top.
3 - 64
Chapter 3
If Map Components is set to ON when a new PC board is generated, the footprint copied to the PC board data by the footprint specification name can be checked on the Assign Components dialog. [Map Components] can be specified on the dialog that is displayed when Set Set Up Tool is selected.
Select components in accordance with the priority of the footprint specification as illustrated below.
Footprint Name Spec
Package Name : A Package Name : B
Flow
Reflow
default
Package library
Sets priority of footprint specification in design rule.
PC board database
Flow > Default

Design rule file (.rul) The points for operation of other footprint (operation of footprint specification name) have been introduced above.
Chapter 3
3 - 65
1. Batch Program List

The CDB, Board Designer and Board Producer have many programs that are not introduced in this Self-Training Course. The [1. Batch Program List] introduces the names and usage of such programs. When using these programs, refer to the corresponding Online Help as shown in the [Refer to:] column of the table below. The column of Product No. shows license numbers.
Database Operation
Program Name Database Copy Program ozcp Usage Copies CR-5000 precisely. Moves CR-5000 securely. database files Product No. Refer to: Database Operation
Database Move
ozmv
database
files
Database Operation
Database Remove
ozrm
Removes CR-5000 database files securely. Upgrades database files created or edited with earlier versions to Rev. 10.0. Converts database files from Rev. 10.0 to Rev. 9.0. Deletes work space that was produced as the design proceeds, and minimizes database size. Unlocks database locked. when it was
Database Operation
Database Upgrade
zdbevolv
Database Operation
Database Downgrade
Zdb10to9
Database Operation
Database Compaction
pcbcompact
Z0501
Database Operation
Database Unlock
zdbrecov
Database Operation
Appendix
A-1
ASCII Input/Output Interface

Program Name Footprint Library Registration Program ftin Usage Inputs footprint library ASCII file (.ftf) to footprint library. Product No. Z0203 Z0409 Z0539 Z0580 Z0581 Z0203 Z0409 Z0539 Z0580 Z0581 Z0201 Z0203 Z0580 Z0201 Z0203 Z0580 Z0201 Z0203 Z0580 Z0801 Z0201 Z0203 Z0205 Z0201 Z0203 Z0508 Z0409 Z0539 Z0580 Z0409 Z0539 Z0580 Z0409 Z0409 Z0409 Z0409 Z0409 Refer to: Component Library ASCII Input/Output
Footprint Library Extraction
ftout
Outputs footprint library ASCII file from footprint library or PC board database.
Component Library ASCII Input/Output
Package Library ASCII Input
pkgconv
Inputs a package library ASCII file to the package library. Outputs the package library to a package library ASCII file (.pkf). Outputs the part library to a part library ASCII file (.cdf).
Component Library ASCII Input/Output Component Library ASCII Input/Output Component Library ASCII Input/Output Component Library ASCII Input/Output Component Library ASCII Input/Output Technology Library ASCII Input/Output Technology Library ASCII Input/Output PC Board Database ASCII Input/Output PC Board Database ASCII Input/Output Panel Database ASCII Input/Output Panel Database ASCII Input/Output Manufacturing rule Database ASCII Input/Output Manufacturing rule Database ASCII Input/Output
Package Library ASCII Output
pkgback
Part Library ASCII Output
partback
CSV to CDF Conversion
csv2cdf
Generates a CDF file from a CSV file that has pin attributes. Inputs a part library ASCII file to the part library. Inputs technology library ASCII file (.tcf) to technology library. Outputs technology library ASCII file from technology library or PC board database. Inputs PC board data ASCII file (.pcf) to PC board database. Outputs PC board data ASCII file from PC board database. Inputs panel data ASCII file (.pnf) to panel database Outputs panel database file from panel database. Inputs manufacturing rule database ASCII file (.mrf) to manufacturing rule database. Outputs manufacturing rule database ASCII file from manufacturing rule database.
Part Library ASCII Output
partconv
Technology Library Registration
tcin
Technology Library Extraction
tcout
PC Board Database Registration PC Board Database Extraction Panel Database Registration Panel Database Extraction Manufacturing Rule Database Registration Manufacturing Rule Database Extraction
pcin pcout pnin pnout mrin
mrout
Z0409
A-2
Appendix
Component Library Management

Program Name Part Coordination Check Program partexam Usage Checks part, pin assign and function to see if component information does no contradict. Checks layer configuration for each library Product No. Z0201 Z0203 Z0201 Z0203 Z0205 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0201 Z0203 Z0205 Z0201 Z0203 Refer to: Consistency Check in Component Information Consistency Check in Component Information Batch Editing of Component Information Batch Editing of Component Information Batch Editing of Component Information Batch Editing of Component Information Batch Editing of Component Information Component Library Merge/Divide Component Library Merge/Divide Component Library Merge/Divide LCDB Generation Library Searcher Search Data Generation Generic Part and Package Generation
Library Configuration Confirmation
confobj
User Property Editor
propedit
Part Deletion
partkill
Edits user-defined properties for each piece of component information in interactive mode or by reading file. Deletes unnecessary parts all at once. For each CDB libraries, import component information from a CSV file or delete the objects. Changes names of objects all at once based on file. Sets package names to specified parts all at once based on file. Copies footprint library or extracts part of its information. Copies package libraries or extracts part of its information. Copies part libraries or extracts part of its information. Outputs component information from part library to LCDB. Generates/updates search data for using library searcher. Automatically generates generic parts (temporarily registered parts) from registered footprint or package information. Generates part library ASCII format file from LDCB.
CDB Edit Program
cdbedit
Object Name Batch Change
chgname
Package Name Batch Setting
setpkg
Footprint Library Merge/Divide
ftpcp
Package Library Merge/Divide
pkgcp
Part Library Merge/Divide
prtcp
LCDB Extraction Search Data Generation
lcdbabst search_gen
Generic Parts Batch Generation
genepart
LCDB to CDB Conversion
lcdb2cdf
Z0201 Z0203
Generating a Part Library from LCDB
Appendix
A-3
Design Change and Design Assist

Program Name Pattern Connection Pinlist Output Program bdnetout Usage Outputs pin information for pattern physically connected from PC board database and design rule database. Outputs logical net list information from PC board database or design rule database. Product No.
Z0501 Z0550 Z0580 Z0581 Z0501 Z0550 Z0580 Z0581 Z0602 Z0501 Z0550 Z0580 Z0581 Z0501 Z0550 Z0580 Z0581 Z0602 Z0501 Z0550 Z0580 Z0581 Z0602
Refer to: Pattern Connection Pinlist Output Net List Output
Netlist Output
netout
Netlist Compare
bdncmp
Compares two specified net lists (.ndf and .sdf) and outputs result.
Net List Comparison
Footprint Spec Reflection
Name
ftsback
Changes and reflects footprint specification name for design rule database onto components on PC board.
Footprint Spec Name Reflection
Component Input/Output
Information
cmpset
Executes five operations on components in PC board database or panel database (component placement information input/output mode, component library input/output mode, unused component library input/output mode, detailed component library input/output mode, stack components mode, change PCB path name mode, PCB information output mode) Outputs list of design differences in design rules. rules and
Component Information Input/Output
Design Rule List Output
drlist
Z0501 Z0550 Z0580 Z0581 Z0602 Z0501 Z0550 Z0580 Z0581 Z0602 Z0501 Z0550 Z0580 Z0581 Z0602 Z0570 Z0201 Z0203 Z0412 Z0413 Z0501 Z0550 Z0580 Z0581 Z0602
Design Rule List Output
Technology List Output
tchlist
Outputs technology name list or technology information list from technology library or PC board/panel database. Compares component information between CDB and PC board database and outputs results.
Technology List Output
PCB/CDB Comparison
Component
cmpdiff
Component Comparison between PCB and CDB Logical Figure Calculation Manufacturing Panel and Divided Design File Copy
Logical Figure Calculation Manufacturing Panel and Divided Design File Copy
calcfig zdbcopy
Performs logical calculations on figures and outputs the merged results. Copies manufacturing panel and divided design file with their parent-child relation maintained.
A-4
Appendix
PC Board Information Reference/Output

Program Name Plotting Program zplot Usage Draws PC board/panel database without starting interactive tool. Product No. Z0501 Z0550 Z0580 Z0581 Z0602 Z0501 Z0550 Z0580 Z0581 Z0602 Z0201 Z0203 Z0501 Z0550 Z0602 Refer to: Plotting PC Boards
Board List Processor
blistp
Outputs component information from PC board/panel database in specified items and format.
Board Information Output
Plot Operating
multiplot
Synthesizes two or more drawings with CR5000 plot intermediate data created with Operate Drawing program, and outputs result of synthesis to plotter. Appends specified text data to CR-5000 plot intermediate data generated by the Plotting Program and outputs it to a plotter. Outputs wiring information by each pin pair. Outputs information (printed resistor list) required for HIC design from Board Designer design data to file.
Merge Multiple Drawings
Text Plotting
strplot
Plotting Text
Wiring Information Output HIC List Output
wirinfo hiclist
Z0501 Z0501 Z0550 Z0560
Wiring Information Output HIC List Output Program
Appendix
A-5
CAM Data Output/Reference

Program Name Photo Data Output Program zphoto Usage Outputs photo data from PC board/panel database to specified layer. Draws, totals, and lists output photo data. Outputs drill data for each of specified holes in accordance with specification of layers and diameter, from PC board/panel database. Draws, totals, and lists output drill data. Lists information related to manufacturing and mounting, such as coordinate value, layer organization and total number of holes, from PC board/panel database. Compares photo data and drill data output by PC board/panel database, and automatically searches for differences. Outputs information from a manufacturing rule library (MRDB) or a manufacturing rule database (MRL). Lists information related to component pins from PC board/panel database. Lists padstacks with test point attributes from PC board/panel database in various formats. Outputs a format file for panaCIM Station (automatic mounter management) from the PC board/panel database. Outputs data in the IPC-D-356A format for bare board testers from the PC board/panel database. Outputs the necessary PC board manufacturing information in the IPC-2581 format from the PC board/panel databases. Product No. Z0602 Refer to: Photo Data Output Check Photo Data Output Drill Data
Photo Data Check Drill Data Output
zphck zdrill
Z0602 Z0602
Drill Data Check CAM Information List Output
zdrck camlist
Z0602 Z0602
Check Drill Data CAM Information List Output
CAM Check Tool
phdiff
Z0602
CAM Data Check
Manufacturing Rule List Output
mrlist
Z0602
Manufacturing Rule List Output
Pin Information List Output
pinlist
Z0602
Pin Information List Output Output In-circuit Tester Pana-CIM Format Output
In-circuit Tester Output
ictout
Z0607
Pana-CIM Format Output
pncimout
Z0610
IPC-D-356 Format Output
zipcd356
Z0611
IPC-D-356 Format Output
IPC-2581 Format Output (Windows only)
ipc2581out
Z0612
IPC-2581 Format Output
A-6
Appendix
Interface to External Systems

Program Name PWS CDB Component Library Conversion (*) PWS BD/CDB Conversion (*) Board Program pws2cdb Usage Converts PWS component libraries, PMASTER and PCMACRO, to CDB library. Converts PWS PC board information, which are PCU, PEM, PCW, PCG and PCP, to CDB library and BD PC board database. Converts CDB library to PWS component libraries, PMASTER and PCMACRO. Converts BD P`C board database to PWS PC board information, which are PCU, PCM, PCW, PCG and PCP. Converts BD PC board database to PWS PC board information, PCU and PCM. Outputs an ASCII file MIC from a parameter file MIG for reference. Inputs an edited ASCII file MIC to a parameter file MIG. Converts a PWS user font file to a user font file used for BD, BP, and CDB. Product No. Z0801 Refer to: PWS
pws2pls
Z0801
PWS
CDB PWS Component Library Conversion (*) BD PWS Board Conversion
cdb2pws
Z0801
PWS
pls2pwsl
Z0801
PWS
BD PWS Artwork PC Board Conversion Parameter ASCII Output
pls2art
Z0801
PWS
migout
Z0801
PWS
Parameter ASCII Input PWS User Font Conversion
migin ufont35
Z0801 Z0201 Z0203 Z0412 Z0413 Z0501 Z0550 Z0580 Z0581 Z0602 Z0405
PWS PWS
Import IGES
igesin
Converts data in IGES file to figure data for PC board/panel database. Converts figure data in PC board/panel database to IGES file. Converts figure data in DXF file to data for PC board/panel database. Converts figure data in PC board/panel database to data for DXF file. Converts figure data in CR-5000 database (PCB) for high-density advanced package (LSI) into figure data in a DXF file that is suitable for editing drawings.
IGES
Export IGES
igesout
Z0405
IGES
Import DXF
dxfin
Export DXF
dxfout
DXF [Package Unit Detail] Export
dxfoutpkg
Z0407 Z0580 Z0581 Z0407 Z0580 Z0581 Z0539 Z0580 Z0581
DXF
DXF
DXF
Caution (*)This program is supported only on UNIX. It cannot be used on Windows.
Appendix
A-7
Program Name DXF [Package Bond Diagram] Export
Program dxfout2
Usage Outputs diagram data written into a nonconductive layer by the Output Diagram program to a DXF file Converts figure data in IDF file to data for PC board/panel database. Converts figure data in PC board/panel database to data for IDF file. Converts figure data in stream file to data for PC board/panel database. Converts figure data in PC board/panel database to data for stream file. Creates data for Lightning from the PC board database.
Product No. Z0539 Z0580 Z0581 Z0410
Refer to: DXF
Import IDF
idfin
IDF
Export IDF
idfout
Z0410
IDF
Import STREAM
streamin
Z0411 Z0580 Z0581 Z0411 Z0580 Z0581 Z0501 Z0550 Z0580 Z0581 Z0602 Z0501 Z0550 Z0580 Z0581 Z0602 Z0807
STREAM
Export STREAM
streamout
STREAM
Conversion from BD to Lightning
bd2hs
Lightning
Conversion from Lightning to Board Designer
hs2bd
Reflects the results of placement/wiring design using Lightning in the PC board database. Creates Board Designer ASCII files from VISULA PC board data CADIF (ASCII file). Creates PCB/RUL file from Board Designer ASCII files. Creates CDB ASCII files from VISULA Central Data Base Creates PRT/PKG/FTP from CDB ASCII files. files
Lightning
PCB Conversion from VISULA to BD (ASCII data conversion) PCB Conversion from VISULA to BD (Binary data conversion) Library Conversion from VISULA to BD (ASCII data conversion) Library Conversion from VISULA to BD (Binary data conversion) FPR Data Conversion Program
rdr2bda
VISULA
bda2pcb cnt2bda bda2cdb bd2fp
Z0807 Z0807 Z0807 Z0501 Z0551 Z0580 Z0581 Z0602
VISULA VISULA VISULA DFM Center
Converts PC board/panel databases to FPR data, in other words, DFM Center database files.
A-8
Appendix
Zuken Inc. Master Training <Engineering Change/Operation> Serial ID C2C1001E

ECO Master Training - CR

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ECO Master Training - CR

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The ZUKEN logo and CI mark are registered trademarks of Zuken, Inc.

Using Engineering Change and Operation Tools

1. Overview of the Lesson ................................................................................................1-1

1. Forward Annotation (Engineering Change)...................................................................2-1

2. Backward Annotation ..................................................................................................2-24

3. Referencing Schematic Diagram (Cross-Probing) ......................................................2-39

4. Changing PC Board Specifications .............................................................................2-45

5. Changing Components ...............................................................................................2-56

Designing in Accordance with Operation

3. Designing Build-up PC Board .....................................................................................3-27

4. Placing Jumper ...........................................................................................................3-39

5. Placing Decoupling Capacitor .....................................................................................3-46

6. Design with Different Rule for Each Constraints Area.................................................3-52

7. Organizing the CDB ....................................................................................................3-60

Preface Welcome to the world of the Engineering Change/Operation

Beginners Training <PCB Design>

The aim is to attain the knowledge necessary to be an operator.

Master Training <PCB Design Library>

Master Training <CAM>

Master Training <Engineering Change/Operation>

1. Overview of the Lesson

IC2 IC1 R1 IC3 IC2

Parent PCB: ex.pcb

Parent PCB: ex.pcb

Chapter 1 Using Engineering Change and Operation Tools

1. Overview of the Lesson

3. Referencing schematic diagram

4. Changing PCB specifications

See [Chapter 2 Engineering Changes].

Chapter 1 Using Engineering Change and Operation Tools

1. Overview of the Lesson

Designing in accordance with operation

5. Placing decoupling capacitor

See [Chapter 3 Designing in Accordance with Operation].

Chapter 1 Using Engineering Change and Operation Tools

1. Forward Annotation (Engineering Change)

1. Forward Annotation (Engineering Change)

1. Forward Annotation (Engineering Change)

1. Forward Annotation (Engineering Change)

For details, refer to the online documentation.

1. Forward Annotation (Engineering Change)

Forward Annotation Tool

Forward annotation is automatically executed after net information is output.

1. Forward Annotation (Engineering Change)

Forward Annotation Processing

Do not rewrite the ECO list file directly.

1. Forward Annotation (Engineering Change)

Component ID (gate ID) Reference designator Net name

1. Forward Annotation (Engineering Change)

Tool Setting for Forward Annotation Tool

1. Forward Annotation (Engineering Change)

1. Forward Annotation (Engineering Change)

%ZUEROOT%\info\board.rsc %CR5_PROJECT_ROOT%\zue\info\board.rsc %HOME%\cr5000\ue\board.rsc

(1) (2) (3)

references the same package name.

1. Forward Annotation (Engineering Change)

Executing Forward Annotation

2. Set parameters for forward annotation.

(2) Circuit Data Name

(3) PC Board Database Name

Display will change

1. Forward Annotation (Engineering Change)

Reference part specified schematic directory (.cir)/ext/schematic directory name.ndf(ruf)