Timing Analysis

Timing Analysis for Digital Design
Bob Reese and Sam Russ Electrical Engineering Department Mississippi State University University of South Alabama
Electrical& ComputerEngineering
University of SouthAlabama
Timing For Digital Systems

Timing analysis of a digital system provides information about: the operating speed system (maximum clock frequency) of the
timing constraints on inputs (setup, hold time) timing characteristics of outputs (propagation delays). Timing characterization of a digital system is the process of determining these timing parameters.
Bob Reese 6/93,SamRuss2/96
Timing
Propagation Delay
Propagation Delay (tpd) - the elapsed time between a change on an input to a change on an output. A combinational output can have propagation high-to-low (tphl) and propagation low-to-high (tplh) times defined for each combinational input which can affect it.
IN OUT Propagation delays are measured from some reference point on the input to a corresponding reference point on the output; ie., 50% point on input to 50% point on the output or 10% and 90% points on input to 10% and 90% points on output.
IN
OUT
tphl
tplh
Timing
Propagation Delay (cont)
A B C
Each output can have propagation delays associated with a particular input: A_TO_Y_PHL A_TO_Y_PLH B_TO_Y_PHL B_TO_Y_PLH C_TO_Y_PHL C_TO_Y_PLH 0.9 ns 1.2 ns 1.0 ns 1.4 ns 0.7 ns 1.0 ns
For simplicity, usually a single propagation delay is associated with an output: Y tpd 1.4ns
Databooks give a typical and maximum propagation delay for combinational outputs.
Timing
Setup and Hold Time

Setup and Hold time are timing parameters associated with an input that is referenced to a clock input. Setup time (tsu) is the minimum amount of time an input has to be stable before the active clock edge. Hold time (thd) is the minimum amount of time an input has to remain stable after the active clock edge.
Rising edge triggered D flip-flop
Not Valid
Valid
Not Valid
CLOCK
tsu thd
If Setup and Hold times are violated then incorrect operation may occur.
Timing
D FlipFlop Timing Parameters

Below are listed the timing parameters for a typical D flip-flop. Note that minimum pulse width values are given for both the clock input and the asynchronous reset input. There is only a tphl specified for the reset line because the Q output can never go high when the reset line is asserted.
Rising edge triggered D flip-flop with low true asynchronous reset D R Q
Propagation Delays Clock to Q tplh Clock to Q tphl R to Q tphl Other constraints: D tsu D thd Clock pulse width high (minimum) Reset pulse width low (minimum)
Timing
System Timing
Inputs Outputs CombinationalLogic
PresentState
State FlipFlops
NextState CLK
Single Phase Sequential System
Question: What is the maximum frequency of operation of this system? Maximum Frequency = 1 / (longest path delay)
Longest Path can be either a. Clock to output delay b. Clock to Register Input delay (register to register delay) c. Input to Register Input delay d. Input to Output Delay Typically, delay path b (register to register delay) dominates and is composed of: Clock_to_Q tpd + comb logic longest tpd from Pstate to Nstate + Nstate tsu
Timing
Maximum Clock Frequency

Another way to look at a single phase sequential system in which all inputs/outputs are registered: Comb Logic D Q tpd longest path (tpd max) tsu
C to Q tpd maximum register to register delay = C to Q tpd + Comb tpd max + tsu
maximum clock frequency = 1 / (maximum register to register delay) Simple sequential system (divide by 2 circuit):
Q Q
Comb tpd max = 0 (assume wire delay is negligible)
Max Freq = 1/ ( C to Q tpd + Comb tpd max + tsu) = 1 /(C to Q tpd + tsu )
Timing
Hold Time
Comb Logic D Q tpd shortest path (tpd min) thd
C to Q tpd In order for the hold time to be satisfied on the second flip-flop the following must be true: C to Q tpd + Comb tpd min > thd If this is NOT true, then the input on the second flip-flop can change before the hold time is satisfied and a hold time violation exists. Simple sequential system (divide by 2 circuit):
Q Q
Comb tpd max = 0 (assume wire delay is negligible)
C to Q tpd + Comb tpd min > thd C to Q tpd > thd
Timing
Setup,Hold Time for External Inputs

External inputs are buffered through pad drivers and may go through combinational logic before they reach a synchronous input; this buffering adds propagation delay. How does this propagation delay affect the external setup and hold time? Consider a chip and the delays involved in getting from the outside to the actual flip-flop...
DIN DIN tpd CLK CLK tpd Comb logic ck tsu,thd Comb logic d D Q
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Timing
Finding the External Setup and Hold Time

Lets look at the timing of this in more detail:
tDIN tCLK
DIN d
DIN tPD Min DIN tPD Max
CLK ck
CLK tPD Min CLK tPD Max
Consider the setup time... What is the worst case? A slow input signal and a fast clock. This occurs when td = tDIN + DIN tPD Max and when tck = tCLK + CLK tPD Min To operate correctly, the internal ck clock has to arrive at least tSU after the internal d signal. tck - td Internal tSU Substituting the td and tck expressions, we have... tCLK + CLK tPD Min - ( tDIN + DIN tPD Max ) tSU Since the external setup time is, by definition, tCLK - tDIN... External tSU Internal tSU - CLK tPD Min + DIN tPD Max
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Timing
External Setup, Hold Time Example

SEL DIN B1 B2 G3 G1 B3 D F1 Q Q G2 F2 D Q
Clk
Assume the following timing parameters: Propagation time though input buffer: 6 ns Propagation time though clock buffer: 6 ns Combinational gates prop time: 3 ns Flip-flop CQ tpd, CQ tpd time: 2 ns Flip-flop hold time: 1 ns Flip-flop setup time: 1 ns
What is the maximum operating frequency? The longest register-to-register path is from flip-flop F1 Q output through gates G2 and G3 to the D input of flip-flop F2. So: max freq = 1 / (F1 CQ tpd + G2 tpd + G3 tpd + F2 tsu) = 1/ (2 + 3 + 3 + 1) = 1/(9 ns) = 111.1 Mhz
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Timing
External Setup, Hold Time Example (cont.)

SEL DIN B1 B2 G1 Clk B3 F1 D Q G2 G3 F2 D Q Q
Assume the following timing parameters: Propagation time thoughclock buffer: 6 ns Combinational gates prop time: 3 ns 2 ns Flip-flop CQ tpd, CQ tpd time: Flip-flop hold time: 1 ns
Flip-flop setup time: 1 ns
What is the external hold, setup time on input DIN? DIN setup time is: DIN tsu = tsu + DIN tpd max - Clk tpd min = tsu + (B2 tpd + G2 tpd + G3 tpd) - (B3 tpd) = 1 + (6 + 3 + 3 ) - 6 = 7 ns DIN hold time is: DIN thd = thd - DIN tpd min + Clk tpd max = thd - (B2 tpd + G1 tpd) + (B3 tpd) = 1 - (6 + 3 ) + 6 = -2 ns Note: The setup time calculated is actually setup time referenced to flip-flop F2. Since the path to F2 is longer, this is the worst-case setup time; if you satisfy this setup time you will satisfy the setup time to flip-flop F1. The hold time is referenced to flip-flop F1 (the faster path); if you satisfy this hold time you satisfy the hold time to flip-flop F2. Likewise, SEL tsu = 4 ns, SEL thd = -2 ns
Bob Reese 6/93,SamRuss2/96 13 Timing
Internal Hold Time Example

Assume the following timing parameters: Propagation time though input buffer: 6 ns Propagation time though clock buffer: 6 ns Combinational gates prop time: 3 ns Flip-flop CQ tpd, CQ tpd time: 2 ns Flip-flop hold time: 1 ns
Does an internal hold time violation exist in this circuit? Find shortest register to register path and see if the hold time is violated. The shortest register to register path is from the Q output of flipflop F2 thru gate G1 to the D input of flip-flop F1. So the following must be true in order for no hold time violation: F2 CQ tpd + G1 tpd > F1 hold time 2 + 3 > 1
The equation is true so no internal hold time violation exists.
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Timing
InputtoReg. Clock Cycle Example

Assume the following timing parameters: Propagation time though input buffer: 6 ns Propagation time though clock buffer: 6 ns Combinational gates prop time: 3 ns Flip-flop CQ tpd, CQ tpd time: 2 ns Flip-flop hold time: 1 ns
Input SEL is available 5 ns after the clock rises. DIN is available 4 ns after the clock rises. What is the maximum clock frequency based on inputto-register-setup? Find the longest input-to-register path: Example: SEL to F2 delay = Tdelay + Tpd B1 + Tpd G3 + Tsu F2 = 5 + 6 + 3 + 1 = 15 ns Then subtract clock buffer delay, since input can be late by this extra amount. Tclk period = T Total Delay - Tpd Clock buffer = 15 - 6 = 9 ns Notice that the SEL to F2 delay can be re-written... TSEL to F2 = TdelaySEL + External Setup Time of SEL = 5 + 4 = 9 ns TDIN to F1/F2 = TdelayDIN + External Setup Time of DIN = 4 + 7 = 11 ns Longest = DIN path = 11 ns => Fmax = 1/11 ns = 90.9 MHz
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Timing
ClocktoOutput Clock Cycle Example

EN1 B4 G4 G3 F2 D Q B5 OUT
Clk
B3
Assume the following timing parameters: Propagation time though I/O buffer: 6 ns Propagation time though clock buffer: 6 ns Combinational gates prop time: 3 ns Flip-flop CQ tpd, CQ tpd time: 2 ns Flip-flop hold time: 1 ns
The signal OUT connects to another chip that has an external setup time of 8 ns. What is the clock cycle based on clock-to-output delay? Find the longest path from clock to output, which in this case is through B3 to F2, through G4 and B5, to the next chip. Tclk = B3 Tpd + F2 CQ Tpd + Tpd G4 + Tpd B5 + Tsu Next Chip = 6 + 2 + 3 + 6 + 8 = 25 ns Fclk = 1/25 ns = 40 MHz How early can the output change after a rising clock edge? Find the shortest path from clock to output, which in this case is via the same path. Time = 6 + 2 + 3 + 6 = 17 ns
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Timing
InputtoOutput Clock Cycle Example

EN1 B4
G3
F2 D Q
G4 B5 OUT
The signal OUT connects to another chip that has an external setup time of 8 ns. The signal EN1 is available 5 ns after the clock rises. What is the clock cycle based on input-to-output delay? Find the longest path from any input to any output ...which in this case is from EN1 through B4, G4, and B5, to the next chip. Tclk period = Tdelay + Tpd B4 + Tpd G4 + Tpd B5 + Tsu Next Chip = 5 + 6 + 3 + 6 + 8 = 28 ns Fclk = 1/28 ns = 35.7 MHz Notice how a signal that propagates out of one chip, through a second, and must set up on a third within one clock cycle can create very large delays and very slow clock frequencies. Also notice that the earliest the output can change from the EN1 input is 5 + 6 + 3 + 6 = 20 ns.
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Timing
External HoldTime Violation Example

EN1 B4 G4 G3 F2 D Q B5 OUT
Clk
B3
The signal OUT connects to another chip that has an external hold time of 10 ns. Does a hold time violation exist? There are two paths from the clock to the OUT signal. The first, via the EN1 signal, cannot change earlier than 20 ns after a clock edge. The second, via the F2 flip-flop, cannot change earlier than 17 ns after a clock edge. Thus the output cannot change too soon after a clock edge, and the hold time of the next chip is satisfied.
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Timing
Another Complete Timing Example

Consider the circuit below with delays (in ns) as indicated A
FF1 D Ck Q 7
Dout D Q 9 6
Ck FF2
Clk
8 2
DFFs: tSU = 3 tHD = 4 tCQ = 5
What is the fastest (shortest) allowable clock cycle, based on register-to-register delays? Start at a clock and consider what happens... Flip flop changes, propagates through logic, sets up on DFF Choose longest of two paths: FF2 to FF1 5 + 8 + 3 = 16 ns = Minimum clock period 1/16 ns = 62.5 MHz = Maximum clock frequency
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Timing
Example, continued
What is the external setup time for the A input? Find maximum A tpd = path to FF1 = 8 + 1 = 9 ns Use Formula: External setup = 3 2 + 9 = 10 ns What is the external hold time for the A input? Find minimum A tpd = path to FF2 = 7 + 1 = 8 ns Use Formula: External setup = 4 + 2 8 = 2 ns How late after the clock can Dout change? Find maximum register to output path its a tie! Dont forget to include the time from clocktoQ and clock buffer delay! Total delay = 2 + 5 + 9 + 6 = 22 ns This is also the minimum delay in this example (not usually the case!) Are there any hold time violations? What is the soonest a FF output can propagate to a FF input? ClocktoQ delay and then from FF1 to FF2 = 5 + 7 = 12 ns The FF input only has to stay valid for 4 ns, and so it cannot change too early.
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Timing
Circuit Data Sheet

Show the data sheet for the circuit...
tCLK
Input A
At SU At HD
Output Dout
tOUT
Parameter tCLK fCLK AtSU AtHD tOUT
Description Clock Period Clock Frequency Input A Setup Time Input A Hold Time Dout Output Delay
Minimum 16 10 2 22
Maximum 62.5
22
Units ns MHz ns ns ns
Note that data sheets do not have linear time scales! The path from input A directly to Dout would also be included on a complete data sheet (min = max = 1 + 9 + 6 = 16 ns)
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Timing
Putting the Circuit into a System

Lets consider the effects of inserting the circuit into a complete system. This means that there are external timing constraints imposed on the inputs and the outputs. Input A is available 2 to 8 ns after the clock rises. Output Dout is required 5 ns before the clock rises again. What is the clock cycle time? There are four cases to consider: Path from register to register already considered 16 ns Path from register to output Clock arrives, FF output changes, propagates to output, sets up externally Time = 2 + 5 + 9 + 6 + 5 = 27 ns Path from input to register Input arrives, takes longest path to a FF, sets up on register Time = 8 (worst) + 1 + 8 + 3 = 20 ns BUT...the clock is delayed 2 ns by the clock buffer. Thus the input could arrive 2 ns later and still make it to the flipflop soon enough to set up. Actual time = 20 2 = 18 ns. Path from input to output Input arrives, propagates to output, sets up externally Time = 8 + 1 + 9 + 6 + 5 = 29 ns
Bob Reese 6/93,SamRuss2/96 22 Timing
Clock Path Analysis

Summarizing the results... Registertoregister: Registertooutput: Inputtoregister: Inputtooutput: 16 ns 27 ns 18 ns 29 ns
The longest is inputtooutput. Coincidence? Probably not! The path winds through two buffers and involves an external input delay and an external output setup time. One point to remember: Direct paths from inputs to outputs are SLOW and make for a LONG system clock cycle. Another point: What if a DFF were put on the line between A and Dout? It would cut this critical path in half! DFFs break up long timing paths, allowing the system clock to be faster. This strategy makes the output available in more clock cycles, but it lets the clock run faster, and therefore the system can take in more inputs (and produce more outputs) per second. This strategy is called pipelining.
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Timing
Timing Analysis
There are two methods for doing timing analysis: simulation and static path analysis. Simulation is used to characterize the primitive elements of a cell library. This is Spicelevel simulation done with transistor level implementations of the gates in which the timing values are measured from the simulated waveforms. The timing information derived from this simulation is used to provide delay information for gate level simulation. Circuit delay will vary with voltage, temperature and process parameters (line width, p/n type transistor characteristics). For this reason, timing characterization is usually done at least for typical and worst case environmental parameters; usually timing characterization for primitive library elements is done with several environments. It can be tempting to use gate level simulation to try to characterize a digital system. One way to get maximum operating frequency is to keep increasing the clock frequency until the simulation behaves incorrectly...... For this to work correctly you must be sure that the test inputs (test vectors) which are being used to drive the simulation exercise the longest path!!! If they dont, then you will get an optimistic estimate of the maximum operating frequency.
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Timing
Static Path Timing Analysis

Static Path Analysis is used with gate level design to compute the timing characteristics of a digital system. Static path analysis assumes that all delays of the primitive components are known. Even wiring delays are included if they are known. The term static refers to the fact that no simulation is being done during the timing analysis instead, all paths within the circuit are traced and the delays of these paths computed. The only information required is the netlist and the delays of the primitive components. Timing characteristics which can be computed by a static path analysis tool: Longest paths between user defined pinsets (clock to latch/FF data inputs, external inputs to external outputs, etc). Determine if any internal hold time violations occur (uses shortest register to register path). External setup, hold times of synchronous inputs. Propagation times of outputs from any input or arbitrary point within the circuit.
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Timing
Environmental Conditions
Primitive component delays can vary with environmental conditions. Some typical environmental conditions are: Temperature: the lower the temperature, the faster the circuit. Voltage: the lower the voltage, the slower the circuit (however, power dissipation is also lowered). Speed Grade or Technology: a parameter such as this usually refers to the fabrication technology such as 1.2 micron CMOS versus 0.8 micron CMOS. The 0.8 number refers to the minimum feature size upon which the transistor and line width sizes are based. Smaller transistors and linewidths equate to a faster and denser circuit. Process variation: CMOS transistors are characterized by the four corner model (fast N/fast P transistors which is best case, slow N/slow P transistors which is worst case, and either slow N/fast P or fast N/slow P which is a typical case). Some delay analysis tools allow you to compute delays based upon best, typical or worst case transistor models. When running a static path analysis tool you will want to use the environment(s) which will best match your operating conditions.
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Timing
Back Annotation
The term back annotation can be used in two contexts a schematic simulation context and a timing analysis context. Back annotation in reference to schematic simulation refers to the displaying of simulation values onto nets within the schematic display during the simulation. This aids in debugging simulation problems because one can traverse around the schematic examining simulation values for nets during any point of the simulation. Back annotation in reference to timing analysis means extracting accurate delay information from a physical implementation (FPGA, standard cell, gate array, etc) after the circuit has been mapped to that implementation. This delay information usually includes wiring delay information because the physical placement of gates will affect the length of the connected nets. This delay information is backannotated into the simulation netlist so that the simulator will now produce more accurate delay information. This delay information can be used by either a static path analysis tool or by a gate level simulator.
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Timing

Timing Analysis

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Timing Analysis

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Timing Analysis for Digital Design

Timing For Digital Systems

Bob Reese 6/93,SamRuss2/96

Bob Reese 6/93,SamRuss2/96

Propagation Delay (cont)

Bob Reese 6/93,SamRuss2/96

Setup and Hold Time

Rising edge triggered D flip-flop

Bob Reese 6/93,SamRuss2/96

D FlipFlop Timing Parameters

Bob Reese 6/93,SamRuss2/96

Single Phase Sequential System

Bob Reese 6/93,SamRuss2/96

Maximum Clock Frequency

Comb tpd max = 0 (assume wire delay is negligible)

Bob Reese 6/93,SamRuss2/96

Comb tpd max = 0 (assume wire delay is negligible)

C to Q tpd + Comb tpd min > thd C to Q tpd > thd

Bob Reese 6/93,SamRuss2/96

Setup,Hold Time for External Inputs

Bob Reese 6/93,SamRuss2/96

Finding the External Setup and Hold Time

Bob Reese 6/93,SamRuss2/96

External Setup, Hold Time Example

Bob Reese 6/93,SamRuss2/96

External Setup, Hold Time Example (cont.)

Flip-flop setup time: 1 ns

Internal Hold Time Example

Flip-flop setup time: 1 ns

The equation is true so no internal hold time violation exists.

Bob Reese 6/93,SamRuss2/96

InputtoReg. Clock Cycle Example

Flip-flop setup time: 1 ns

Bob Reese 6/93,SamRuss2/96

ClocktoOutput Clock Cycle Example

Flip-flop setup time: 1 ns

Bob Reese 6/93,SamRuss2/96

InputtoOutput Clock Cycle Example

Flip-flop setup time: 1 ns

Bob Reese 6/93,SamRuss2/96

External HoldTime Violation Example

Flip-flop setup time: 1 ns

Bob Reese 6/93,SamRuss2/96

Another Complete Timing Example

DFFs: tSU = 3 tHD = 4 tCQ = 5

Bob Reese 6/93,SamRuss2/96

Bob Reese 6/93,SamRuss2/96

Circuit Data Sheet

Parameter tCLK fCLK AtSU AtHD tOUT

Bob Reese 6/93,SamRuss2/96

Putting the Circuit into a System

Clock Path Analysis

Bob Reese 6/93,SamRuss2/96

Bob Reese 6/93,SamRuss2/96

Static Path Timing Analysis

Bob Reese 6/93,SamRuss2/96

Bob Reese 6/93,SamRuss2/96

Bob Reese 6/93,SamRuss2/96

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