Documente Academic
Documente Profesional
Documente Cultură
1- PRINCIPES et CLASSIFICATION
2- TECHNOLOGIES
3- ARCHITECTURES ET CIRCUITS
4- CONCEPTION : méthodes et outils
5 - APPLICATIONS: LOGIQUE
RECONFIGURABLE
1- LOGIQUE RECONFIGURABLE : PRINCIPES
2- LOGIQUE RECONFIGURABLE : EXEMPLES
– comparateurs, opérateurs arithmétiques
– filtres, DSP
3- LOGIQUE RECONFIGURABLE : APPLICATIONS
– Prototypage, émulation, vérification
4- RECONFIGURATION STATIQUE et DYNAMIQUE
5- PERSPECTIVES
– Circuits FPGAs complexes
–Logique reconfigurable dans les SOCs
5. 1 Logique reconfigurable :
principes
FPGA
FPGA SRAM :
Reprogrammation statique ou dynamique
Vcc Vcc
Bit line
FPGA-SRAM
!C
A A
A B C
S S
C 0
1
SRAM cells 0
1 MUX S
B 0
C B 1
1
S=A.B ? 1
CONF
CONF
Gnd Gnd
(b) Phase de configuration (c) Phase d’opération
– Exemple: B = 127
– S127 = A7
Architecture :
DSP FPGA
1 1 2 3 4 N
Add Add
X0 PRODUCT
SUM K Multiplies
• X K Sums
C0 CLOCK = Multiply Time
X1
K Sample Rate = Clock Rate
• X
C1
X2
OUTPUT DATA
• X
0
C2
• • IMPLEMENTATION ?
• •
• K COEFFICIENTS •
K TAPS LONG
K SUMS
General-Purpose DSP
1
– PERFORMANCE =
MAC cycle time X Number of Taps
Clock Frequency
PERFORMANCE =
Number of Bits in Sample
10-bit, 20-tap filter using XC4000 at 50 MHz = 5 MHz
Pr. Michel ROBERT logique programmable
5.3 Logique Reconfigurable : Applications
Systèmes :
– co-processeurs reconfigurables
– optimisation d’architectures, à partir de blocs
FPGA “embarqués”
RAM
R
processeur
processeur A
M A/D
D/A
RAM
2 E/S Série
LOGICIEL MATERIEL
Compilation Synthèse
HOST
PC Protocole de communication
CARTE MERE
Carte TIM40
Carte LIRMM Carte mère
(Logic Inside Reconfigurable Micro Machine) Hunt Engineering
SDRAM modules
SDRAM connector
serial ports
USB connector
PS2 ports
Parallel port
CIRCUITS RECONFIGURABLES
- Expérimentation “rapide” :
~ matériels et logiciels
~ adéquation Algo. / Archit.
~ temps réel
FPGA FPGA
FP FP FP
GA GA GA
FP FP FP
GA GA GA
FP FP FP
GA GA GA
Coût et maintenance
élevés Faible Coût
Flexibilité
Architecture figée
Pr. Michel ROBERT logique programmable
PEKEE PROJECT
THE CONCEPT OF HYBRID PLATFORM FOR RESEARCH, EXPERIMENTATION
AND EDUCATION
Ouverte, Evolutive, Modulaire, Autonome
Boîtier
Carte Fille
Coques
Carte PC
embarqué
Carte TP
à Carte châssis
wrapper +
Bus OPP
2 Moteurs
Accumulateurs intelligents
• Communication inter-cartes
•Interface Bus OPP / Bus adresses
données (16 bits R W CS)
(transparente pour l’utilisateur)
Pr. Michel ROBERT logique programmable
Reconfiguration de FPGA-SRAM
S
CONF
CONF Phase de configuration Phase d’opération:
RECONFIGURATION STATIQUE
• Chargement séquentiel de plusieurs architectures Couche OPERATIVE
conf1
• Une architecture par application
Load
A
FPGA
Load
B RUN C
A
B
Load
C
Pr. Michel ROBERT logique programmable
5.4 Reconfiguration statique et dynamique:
New Approach : changing the configuration on the fly,
in real time
FPGA
B
A
Load
D
D
C
Dynamic
Reconfiguration
Time
Temporal plane
of configuration
nth reconfig.
2nd reconfig. y
1st reconfig.
Initial config.
Spatial plane of
configuration
x
E/S
User I/Os
FastMAPtm
User I/Os Function Cell
User I/Os
Interface
Address
Data
Control
User I/Os
CLB Column
IOBs
IOBs
Configuration Columns
2
2
CLB Column
2
2
Center Column
2
2
CLB Column
IOBs GCLKs IOBs
IOBs GCLKs IOBs
logique programmable
2
2
CLB Column
IOBs
IOBs
VIRTEX Architecture
ESB
ESB
ESB ESB
ESB
75K Gates
Available
150K Gates
ESB ESB
ESB ESB
ESB ESB
Available
ACEX™ EP1K100
ESB
APEX EP20K200E
500K Gates
Available
Excalibur NIOS
(soft processor)
Excalibur ARM
(hard processor)
Bloc FPGA
Architectures multi-processeurs
S=>P
RAM ROM
µC
Aujourd’hui DSP REUTILISATION
Demain
ASIC ASIC ASIC
mémoire
Matériel standard « FPGA-based system »
mémoire Analog
• Prototype rapide
“ASIC based system” FPGA FPGA FPGA
• Programmable
µP
FPGA FPGA FPGA
mémoire mémoire
• Reconfigurable
re
TTL µproc.,
co
memory
nf
1967 1987 2007
LSI, ASICs,
igu
1957 1977 1997
MSI accel’s
ra
ble
custom algorithm: fixed algorithm: variable algorithm: variable
resources: fixed resources: fixed resources: variable
DSP
Accélérateurs
Processeurs VLIW
ASIC reconfigurables (filtres…)
reconfigurables
FPGA
Reconfigurable
DSP RAM
Custom Logic
CPU
Reconfigurable Logic
CPUs
Memory
Embedded
Reusable IP Software
Communication network
Reconfigurable Interconnect www
Environment
- Heterogeneous components
- Complex on-chip communication network
- HW/SW trade offs
Pr. Michel ROBERT logique programmable
Heterogeneous Reconfigurable System-on-a-Chip
Reconfigurable
management
Memory
RAM2
core
µP RAM
RAM3
RAM4
Memory Interface
management
Bus Programmable
arbitrer interconnect
Timers, IOs, Timers, IOs, Interface
UARTS… UARTS…
Reg FILE
FPGA
DCT MPEG4
ALU + MULT
DSP
Granularité ?
Switch 1 Switch 2
Switch 3 Switch 4
RISC
N3,1 N3,2 N4,1 N4,2
Fine grain
Reconfigurable logic
SYSTOLIC
CISC VLIW RING
SIMD
Parallelism
Programming difficulty
Pr. Michel ROBERT logique programmable
Activités liées à la recherche : architectures reconfigurables
Registres
Dnode Dnode
Sw
e
Switch
h
tc
r
i tc i 3200 MIPS@200MHz
u
h Sw
t
Dnode Dnode
ru c
Dnode Dnode Dnode Dnode
S t e a u
n
Flot de
An
I/O Switch données Switch I/O
Direct
Dnode Dnode Dnode Dnode
i tc
wit c h
S
Dnode Dnode
+ Reg FILE
ALU + M ULT
+ * S
RAM
CONFIGURATION *
layer 3
2 DATA Host
µP
CONFIG
1
Config MANAGEMENT CODE
Controller
Pr. Michel ROBERT logique programmable
Systolic Ring Dnode : word-level processing unit
Constitution
• Optimized Datapath (16 bits)
µinst.
• Register File (4x16bits)
• Hardwired ALU and multiplier
Reg FILE
Features
• Complex computations in local mode (FIR,IIR, WT…)
• Low silicon area (0.07mm², 0.18µm CMOS process)
• Single-cycle operations (ex:MAC+register load)
ALU + MULT
I/O
Dataflow
D-Node
D node D-Node
Switch components:
Switch
I/O Switch Switch I/O
Direct FIFO connection for Data injection D-Node
D node D-Node
D-Node D-Node
D node
Local mode : stand-alone
Switch
I/O Switch Switch I/O
D-Node
D node D-Node
D node
Global mode : FPGA like
I/O
Pr. Michel ROBERT logique programmable
Systolic Ring architecture Forward dataflow
Peak power : 3200 MIPS@200MHz (16 Dnodes version)
Dnode Dnode
Switch
E/S Switch Switch E/S
Dnode Dnode
Dnode Dnode
Switch
Switch Switch
E/S E/S
Dnode Dnode
Switch 3 Switch 4
CG CG CG CG
CG CLB CLB
Dnode Dnode
Switch
Switch Switch
I/O I/O
Dnode Dnode Dnode Dnode
Switch Switch
Dnode Dnode
I/O I/O
High timing performances
Banque
de Registre
ALU + MULT
Dnode
Pr. Michel ROBERT logique programmable