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Application note
Using the Global Crosstalk Evaluation

Etienne SICARD
Februarv 2006

INTRODUCTION........................................................................................................................ 1
GLOBAL CROSSTALK ALGORITHM.......................................................................................... 2
GLOBAL CROSSTALK EXAMPLES............................................................................................. 3
REFERENCES ........................................................................................................................... 4

Introduction

When a conductor is routed close to another conductor, a crosstalk capacitance, deIined as C
12

is created between the two conductors (Figure 1). More inIormation about the crosstalk
coupling and parasitic eIIects may be Iound in |Sicard 2005|. An in-depth study oI research
papers on this crosstalk eIIect is given in |Caignet 2001|.


Ground plane
Two conductors
over a ground
plane
SurIace
capacitance Cs
Findging
capacitance CI
d
Crosstalk
capacitance C12
Ground plane
dielectric
Crosstalk
capacitance C12

Figure 1. Two conductors above a ground plane



Figure 2 The coupling configuration used to simulate the crosstalk effect (Crosstalk.SCH)


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Far end crosstalk
higher than VDD/2
Near end crosstalk
approching VDD/2
AIIector control
AIIector inverter
output

Figure 3 . Simulation of the crosstalk coupling in a 1mm interconnect (Crosstalk.MSK)

The simulation oI the crosstalk eIIect is based on two inverters, one considered as the
aIIecting signal, the other as the victim signal. The inverters are connected to long
interconnects routed with the minimum distance. The victim is connected to a weak inverter,
and surrounded by two aggressor lines connected to a very powerIul inverter, to create the
maximum crosstalk eIIect (Figure 2).

When the aggressor lines are switching, the coupling is strong enough to increase the voltage
at the Iar end oI the victim line, higher than the switching threshold oI logic gates (Which is
around VDD/2), which may provoke a permanent logic Iault (Figure 3). The noise is quite
impressive. Remember that the line is only 1mm long, which is very common in circuit
design. However, the situation where the 1mm interconnect is driven by a very low drive
inverter is not usual |Sicard 2005|.

Global Crosstalk Algorithm

An evaluation oI the crosstalk eIIect based on analytical approximations oI the coupling
amplitude is available using the command 'Analysis 'Global Crosstalk analysis to
access to this command. The example oI the complete crosstalk calculation oI each
interconnect Ior the layout 'AddBCD.MSK is displayed in Iigure 2. The Iormulations used
Ior the computation oI the crosstalk voltage V are shown below.

victim
x
C
C
C
12
=
affector
affector
victim
victim
W
L
L
W
x =
x C
C
J J
x
x
dd
+ +
=
1
1
1


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With

C12 crosstalk capacitance (Farad)
Cvictim capacitance oI victim (Farad)
W width oI MOS device (m)
L length oI MOS device (m)
Vdd supply voltage (V)
C
aIIector
Substrate (Ground)
C
victim
C
12

Global Crosstalk Examples



Figure 4. Global crosstalk extraction and evaluation of crosstalk noise for three critical nodes
(CrosstalkEvaluation.MSK)

The case study proposed in Iigure 4 corresponds to three identical structures, based on two
unbalanced inverters. The distance between interconnects is 8 lambda (upper structure), 6
lambda (middle structure) and 4 lambda (lower structure). The crosstalk noise is signiIicantly
decreased iI the lateral distance between conductors is increased.
Two nodes are highlight in the screen, Ior which the noise is higher than 30. The node
'victimeNear2 suIIers a 35 voltage noise, and 'victimeNear3 suIIers a 46 noise.

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Figure 5. Global crosstalk extraction and classification of dangerous nodes (AddBCD.MSK)

In Iigure 5, the nodes in red correspond to the highest crosstalk noise, while the nodes in blue
have almost no noise due to lateral coupling. Vss and Vdd nodes may be removed Irom the
list, and interconnects with length less than a user`s deIined value may also be removed.

The values higher that 30 oI VDD may jeopardize the saIe behavior oI signal propagation.
In the list, three internal nodes (i0w9, iow10, iow4) may suIIer noise above that limit.
However, the evaluation takes into account a worst-case situation where all potential
aggressors switch synchronously. A time domain simulation should be conducted including
the evaluation oI crosstalk noise Ior these 3 victim nodes to veriIy that the noise do not reach
this worst-case value.

References

|Sicard 2005| E. Sicard, S. Ben Dhia Basics oI CMOS cell design - Book published by Tata
McGraw Hill, 450 pages, ISBN 0-07-0599335, June 2005

|Caignet 2001| F. Caignet, S. Delmas-Ben Dhia, P. Saintot, E. Sicard "The challenge oI
Signal Integrity in Deep Submicron CMOS technology", IEEE proceedings, April 2001,
special topic "The Iuture oI Interconnects" Vol 89, N4