Lecture 300 Buffered Op Amps (3/21/02)

Page 300-1

LECTURE 300 BUFFERED OP AMPS

(READING: AH 352-368) Objective The objective of this presentation is: 1.) Illustrate the method of lowering the output resistance of simple op amps 2.) Show examples Outline Open-loop, MOSFET buffered op amps Closed-loop MOSFET buffered op amps BJT output op amps Summary Buffered Goal High Frequency To illustrate the degrees of freedom and Differential Output choices of different circuit architectures that can enhance the performance of a Two-Stage given op amp. Op Amp
Low Power Low Voltage
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02)

Low Noise
Fig. 7.0-1

P.E. Allen - 2002 Page 300-2

What is a Buffered Op Amp? A buffered op amp is an op amp with a low value of output resistance, Ro. Typically, 10 Ro 1000 Requirements Generally the same as for the output amplifier: Low output resistance Large output signal swing Low distortion High efficiency Types of Buffered Op Amps Buffered op amps using MOSFETs With and without negative feedback Buffered op amps using BJTs

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

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Source-Follower, Push-Pull Output Op Amp

VDD
M6 IBias M5 R1 M8 M7 R1 + vin M4 M11 M12 M9 M10 M17

I17
M22

VSG18 + M18

+ VDD V GS22 VSS

VSS
vout

Cc M15
R1 M13

M19

CL VSG21 + VDD

+ VGS19 -

M1

M2

I20
M16 M20

M21

M3
M14 VSS

Buffer

Fig. 7.1-1

1 Rout = gm21+gm22 1000, Av(0) = 65dB (IBias=50A), and GB = 60MHz for CL = 1pF Output bias current? M18-M19-M21-M22 loop VSG18+VGS19 = VSG21+VGS22 2I18 2I19 2I21 2I22 which gives + = + KPS18 KNS19 KPS21 KNS22
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02) P.E. Allen - 2002 Page 300-4

Crossover-Inverter, Buffer Stage Op Amp Principle: If the buffer has high output resistance and voltage gain (common source), this is okay if when loaded by a small RL the gain of this stage is approximately unity.
VDD

240 14

M7

144 M3 14

M4

240 14

M6

100A C1=8pF

2400 7.5
vout

C2=5pF

RL
vin + + vin'

M1

M2

M5

Input stage

460 7.5 Cross over stage VSS

360 7.5

1400 14 Output Stage

Fig. 7.1-2

This op amp is capable of delivering 160mW to a 100 load while only dissipating 7mW of quiescent power!

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

Page 300-5

Crossover-Inverter, Buffer Stage Op Amp - Continued How does the output buffer work? The two inverters, M1-M3 and M2-M4 are designed to work over different regions of the buffer input voltage, vin. Consider the idealized voltage transfer characteristic of the crossover inverters:
VDD

240 14

M7

144 M3 14

M4

240 14

M6
vout

VDD

vout M2 Active

C1=8pF 100A
vin'

C2=5pF
M2 M7

M1-M3 M2 SaturInverter M1 Saturated ated

M1 Active

M2-M4 Inverter

M1

460 7.5

360 7.5
VSS

RL

0 VSS

VA

VB

VDD
Fig. 7.1-3

vin'

Crossover voltage VC = VB-VA 0 VC is designed to be small and positive for worst case variations in processing (Maximum value of VC 110mV)

ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02)

P.E. Allen - 2002 Page 300-6

Crossover-Inverter, Buffer Stage Op Amp - Continued Performance Results for the Crossover-Inverter, Buffer Stage CMOS Op Amp Specification Supply Voltage Quiescent Power Output Swing (100 Load) Open-Loop Gain (100 Load) Unity Gainbandwidth Voltage Spectral Noise Density at 1kHz PSRR at 1kHz CMRR at 1kHz Input Offset Voltage (Typical) Performance 6V 7 mW 8.1 Vpp 78.1 dB 260kHz 1.7 V/ Hz 55 dB 42 dB 10 mV

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

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Compensation of Op Amps with Output Amplifiers Compensation of a three-stage amplifier: Poles This op amp introduces a third pole, p3 (what p1' and p2' about zeros?) + v2 + With no compensation, vin -Avo Vout(s) Unbuffered s s Vin(s) = s op amp p - 1 p - 1 p - 1 1 2 3 Illustration of compensation choices:
j p2 Compensated poles Uncompensated poles p2 p3=p3' p2' p1' p1

Pole p3'

x1 Output stage CL RL

vout

Fig. 7.1-4

p3' p3

p2'

p 1' p 1

Miller compensation applied around both the second and the third stage.
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02)

Miller compensation applied around the second stage only. Fig. 7.1-5
P.E. Allen - 2002 Page 300-8

Low Output Resistance Op Amp To get low output resistance using MOSFETs, negative feedback must be used. Ideal implementation:
VDD

Error Gain Amplifier Amplifier viin +

M2 + + CL M1 RL
Fig. 7.1-5A

iout vout

Error Amplifier

VSS

Comments: The output resistance will be equal to rds1||rds2 divided by the loop gain If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is not defined

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

Page 300-9

Low Output Resistance Op Amp - Continued Offset correction circuitry:

VDD
+ vin + -

M16

M6
-A1+

M9

Cc

VOS

vout

Error Loop
M8

Unbuffered op amp
+ VBias -

+ A2

M8A

M10

M17

M13 VSS

M6A M12

M11
Fig. 7.1-6

The feedback circuitry of the two error amplifiers tries to insure that the voltages in the loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust the output for any error in the loop. The circuit works as follows: When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducing IM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreases by an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2.
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02) P.E. Allen - 2002 Page 300-10

Low Output Resistance Op Amp - Continued Error amplifiers:

VDD M6 M3
vin

M4

Cc1 MR1
vout

M1

M2

+ M5 VBias A1 amplifier

M6A VSS
Fig. 7.1-7

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

Page 300-11

Low Output Resistance Op Amp - Complete Schematic

VDD
+ VBiasP -

+ vin -

+ -

M16

M3H M3

M4H M4

MP4 MP5

MP3A MP4A M6 M9 M8A Cc2 MR2

M5A

Cc
MP3 MR1 M1 M2

Cc1

M10

MN3A M6A

M2A M1A

M8 M17
+ VBiasN -

M5

MN3

MN4

MN5A M13 M12 M11 MN4A M4HA

M4A

M3A M3HA

VSS

vout
RC CC

Fig. 7.1-8

Compensation: Uses nulling Miller compensation. Short circuit protection: MP3-MN3-MN4-MP4-MP5 MN3A-MP3A-MP4A-MN4A-MN5A (max. output 60mA)
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02)

gm1
R1

gm6
C1 RL CL

P.E. Allen - 2002 Page 300-12

Low Output Resistance Op Amp - Continued Table 7.1-2 Performance Characteristics of the Low Output Resistance Op Amp:
Specification Power Dissipation Open Loop Voltage Gain Unity Gainbandwidth Input Offset Voltage PSRR+(0)/PSRR-(0) PSRR+(1kHz)/PSRR-(1kHz) THD (Vin = 3.3Vpp) RL = 300 CL = 1000pF THD (Vin = 4.0Vpp) RL = 15K CL = 200pF Settling Time (0.1%) Slew Rate 1/f Noise at 1kHz Broadband Noise Simulated Results 7.0 mW 82 dB 500kHz 0.4 mV 85 dB/104 dB 81 dB/98 dB 0.03% 0.08% 0.05% 0.16% 3 s 0.8 V/s Measured Results 5.0 mW 83 dB 420 kHz 1 mV 86 dB/106 dB 80 dB/98 dB 0.13%(1 kHz) 0.32%(4 kHz) 0.13%(1 kHz) 0.20%(4 kHz) <5 s 0.6 V/s 130 nV/ Hz 49 nV/ Hz

rds6||rds6A 50k Rout Loop Gain 5000 = 10

ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

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Low-Output Resistance Op Amp - Continued Component sizes for the low-resistance op amp: Transistor/Capacitor m/m or pF M16 184/9 M17 66/12 M8 184/6 M1, M2 36/10 M3, M4 194/6 M3H, M4H 16/12 M5 145/12 M6 2647/6 MRC 48/10 11.0 CC M1A, M2A 88/12 M3A, M4A 196/6 M3HA, M4HA 10/12 M5A 229/12 M6A 2420/6 10.0 CF
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02)

Transistor/Capacitor M8A M13 M9 M10 M11 M12 MP3 MN3 MP4 MN4 MP5 MN3A MP3A MN4A MP4A MN5A

m/m or pF 481/6 66/12 27/6 6/22 14/6 140/6 8/6 244/6 43/12 12/6 6/6 6/6 337/6 24/12 20/12 6/6
P.E. Allen - 2002 Page 300-14

Simpler Implementation of Negative Feedback to Achieve Low Output Resistance

VDD

M8 M3 200A 10/1 1/1

M1 10/1

M4

M6 1/1 10/1
vout

+ vin -

M2

CL

10/1
M5

1/1 M10 10/1 M9 1/1 10/1

M7 VSS
Fig. 7.1-9

Output Resistance: Ro Rout = 1+LG where 1 Ro = gds6+gds7 and gm2 |LG| = 2gm4 (gm6+gm7)Ro

Therefore, the output resistance is 1 Rout = gm2 . (gds6+gds7)1 + 2g (gm6+gm7)Ro m4

ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

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Example 7.1-1 - Low Output Resistance Using the Simple Shunt Negative Feedback Buffer Find the output resistance of above op amp using the model parameters of Table 3.1-2. Solution The current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of 1 1000 Ro = ( + )1mA = 0.09 = 11.11k N P To calculate the loop gain, we find that gm2 = 2KN10100A = 469S gm4 = 2KP1100A = 100S and gm6 = 2KP101000A = 1mS Therefore, the loop gain is 469 |LG| = 100 1211.11 = 104.2 Solving for the output resistance, Rout, gives 11.11k Rout = 1 + 104.2 = 106 (Assumes that RL is large)
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02) P.E. Allen - 2002 Page 300-16

BJTs Available in CMOS Technology Illustration of an NPN substrate BJT available in a p-well CMOS technology:

;;; ;; ; ;;; ;;;

Emitter Base
n+ (Emitter)

Collector (VDD) n+

Collector (VDD) Base

p+

p- well (Base)

n- substrate (Collector)

Fig. 7.1-10

Emitter

Comments: gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower Can use the lateral or substrate BJT but since the collector is on ac ground, the substrate BJT is preferred Current is required to drive the BJT

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

Page 300-17

Two-Stage Op Amp with a Class-A BJT Output Buffer Stage Purpose of the M8-M9 source VDD follower: M5 M7 M12 1.) Reduce the output resistance + (includes whatever is seen from vin the base to ground divided by M1 M2 I Bias 1+F) Cc 2.) Reduces the output load at the M4 M3 drains of M6 and M7 M6
M13

M8 Q10

M9 CL M11

vout

RL

Output Buffer VSS Fig. 7.1-11 Small-signal output resistance : r10 + (1/gm9) 1 1 = gm10 + gm9(1+F) Rout 1+F = 51.6+6.7 = 58.3 where I10=500A, I8=100A, W9/L9=100 and F is 100 Maximum output voltage: Ic10 2K P vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD V ln t I8(W 8/L 8) Is10 Voltage gain: gm10RL gm1 gm6 gm9 vout = g g +g 1+g vin g + g + g +g + g R ds4 ds6 ds7 m9 mbs9 ds8 10 m10 L ds2 Compensation will be more complex because of the additional stages.
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02) P.E. Allen - 2002 Page 300-18

Example 7.1-2 - Designing the Class-A, Buffered Op Amp Use the parameters of Table 3.1-2 along with the BJT parameters of Is = 10-14A and F = 100 to design the class-A, buffered op amp to give the following specifications. Assume the channel length is to be 1m. VDD = 2.5V VSS = -2.5V GB = 5MHz Avd(0) 5000V/V Slew rate 10V/s Rout 100 CL = 100pF ICMR = -1V to 2V RL = 500 Solution Because the specifications above are similar to the two-stage design of Ex. 6.3-1, we can use these results for the first two stages of our design. However, we must convert the results of Ex. 6.3-1 to a PMOS input stage. The results of doing this give W 1= W 2 = 6m, W3 = W4 = 7m, W5 = 11m, W6 = 43m, and W7 = 34m. BJT follower: SR = 10V/s and 100pF capacitor give I11 = 1mA. If W13 = 44m, then W11 = 44m(1000A/30A) = 1467m. I11 = 1mA 1/gm10 = 0.0258V/1mA = 25.8 MOS follower: To source 1mA, the BJT must provide 2mA which requires 20A from the MOS follower. Therefore, select a bias current of 100A for M8. If W12 = 44m, then W8 = 44m(100A/30A) = 146m.
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

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Example 7.1-2 - Continued If 1/gm10 is 25.8, then design gm9 as 1 1 gm9=R - (1/g )(1+ ) = (100-25.8)(101) = 133.4S gm9 and I9 W/L = 0.809 m10 F out Let us select W/L = 10 for M9 in order to make sure that the contribution of M9 to the output resistance is sufficiently small and to increase the gain closer to unity. This gives a transconductance of M9 of 469S. To calculate the voltage gain of the MOS follower we need to find gmbs9. gm 9N 4690.4 gmbs9 = = = 57.1S 2 2F + VBS9 2 0.7+2 where we have assumed that the value of VSB9 is approximately 2V. 469S AMOS = 469S+57.1S+4S+5S = 0.8765 V/V. The voltage gain of the BJT follower is 500 ABJT = 25.8+500 = 0.951 V/V Thus, the gain of the op amp is Avd(0) = (7777)(0.8765)(0.951) = 6483 V/V The power dissipation of this amplifier is, Pdiss. = 5V(1255A) = 6.27mW
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02) P.E. Allen - 2002 Page 300-20

Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage This amplifier can reduce the quiescent power dissipation.
VDD M5 M7

M10 + vin IBias

M3

Q8
M1 M2

95A Cc 133A
vout

M4 M6 VSS

M9 Output Buffer

CL

RL

Fig. 7.1-12

Slew Rate: IOUT (1 + F)I7 SR+ = CL = CL

+

and

SR-

9(VDD 1V + |VSS| VT0)2 = 2CL

If F = 100, CL = 1000pF and I7 = 95A then SR+ = 8.59V/s. Assuming a W9/L9 = 60 (I9 = 133A), 2.5V power supplies and CL = 1000pF gives SR= 35.9V/s. (The current is not limited by I7 as it is for the positive slew rate.)
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 300 Buffered Op Amps (3/21/02)

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Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage Small-signal characteristics: Cc
+ gmIVin R1 V1 gmIIV2 -

Nodal equations: gmIVin = (GI + sCc)V1 sCcV2 + 0Vout 0 = (gmII sCc)V1 + (GII + g + sCc + sC)V2 (g + sC)Vout 0 gm9V1 (gm13 + sC)V2 + (gm13 + sC)Vout where g > G3 The approximate voltage transfer function is: V 9(s) (s/z1) 1 ( s /z 2 ) 1 A v 0 Vin(s) (s/p1) 1 (s/p2) 1 where gmIgmII gm13 gmII gm9 1 Av0 = GIGII z1 = C z2 = C + Cc 1 + gmII C g c m9 1 + gmII gmII gm13 gm13gmII C GIGII -1 GIGII gm9 p1 = gmIICc + p 1 + g 2 (gmII + gm9)C F mII Cc gm13gmII

+ V + R2 V 2 - gm8V

R3

gm9V1

Vout
Fig. 7.1-13

ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02)

P.E. Allen - 2002 Page 300-22

vOUT (Volts)

Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage - Continued Output stage current, IC8: S9 60 IC8 = ID9 = S6ID6 = 43 95A = 133A Small-signal output resistance: r + RII 19.668k + 116.96k rout = 1 + F = =1353 101 if I6 =I7 = 95A, and F = 100. 2 Loading effect of RL on the voltage transfer curve (increasing W9/L9 will 1 improve the negative part at the cost of power dissipation): R = 1000
0
L

RL = 100

RL =50

-1 -2 -3 -2

-1.5

-1

-0.5 0 0.5 vIN (Volts)

Fig. 7.1-14A
P.E. Allen - 2002

1.5

ECE 6412 - Analog Integrated Circuit Design - II

Lecture 300 Buffered Op Amps (3/21/02)

Page 300-23

Example 7.1-3 - Performance of the Two-Stage, Class AB Output Buffer Using the transistor currents given above for the output stages (output stage of the two-stage op amp and the buffer stage), find the small-signal output resistance and the maximum output voltage when RL = 50. Use the W/L values of Example 7.1-2 and assume that the NPN BJT has the parameters of F = 100 and IS = 10fA. Solution It was shown on the previous slide that the small-signal output resistance is r + rds6||rds7 19.668k + 116.96k = = 1353 rout = 1+F 101 Obviously, the MOS buffer of Fig. 7.1-11 would decrease this value. The maximum output voltage is given above is only valid if the load current is small. If this is not the case, then a better approach is to assume that all of the current in M7 becomes base current for Q8. This base current is multiplied by 1+F to give the sourcing current. If M9 is off, then all this current flows through the load resistor to give an output voltage of vOUT(max) (1+F)I7RL If the value of vOUT(max) is close to VDD, then the source-drain voltage across M7 may be too small to be in saturation causing I7 to decrease. Using the above equation, we calculate vOUT(max) as (101)95A50 or 0.48V which is close to the simulation results shown using the parameters of Table 3.1-2.
ECE 6412 - Analog Integrated Circuit Design - II Lecture 300 Buffered Op Amps (3/21/02) P.E. Allen - 2002 Page 300-24

SUMMARY A buffered op amp requires an output resistance between 10 Ro 1000 Output resistance using MOSFETs only can be reduced by, - Source follower output (1/gm) - Negative shunt feedback (frequency is a problem in this approach) Use of substrate (or lateral) BJTs can reduce the output resistance because gm is larger than the gm of a MOSFET Adding a buffer stage to lower the output resistance will most like complicate the compensation of the op amp

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002