Lab Two 4 BIT Shifter

by

Asif Subhan

ITCS 3181L Due: September 17, 2013 Lab Date: September 13, 2013 Section: L01

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Purpose:
The purpose of this is to design a circuit that will shift four bit binary number to left, right or dont shift. In this lab I will use four 2 variable multiplexer and two AND gates. This design will have four inputs for the four bit number, D0 to D3. Two inputs for control S0 and S1. And two input for shift, right or left. The output will include 4 bit number Q0 to Q1. And two outputs for shift left out and shift right out. Once all the data is inputted. The 2 variable multiplexer will decide which data to output based on S0 and S1. Shift left will only activate when S0 is one, and Shift Right when S0 is one. The multiplexer has a longer delay than AND gates but all multiplexers are in parallel to each other so it takes the same amount of time to process data. The delay doesnt matter when reading results from Q0 to Q1. The function of this design was as I expected. I used multiplexer because it seem easier this way, and more efficient. The experience with this lab has helped me understand the multiplexer more, and how I could use multiplexer in other designs. We could use this shifter to multiply two or more number with doing a whole lot of addition, multiplication was the first application of bit shifter that came to mind when I was designing this circuit. But for Multiplication we would probably have to use D-Latches in order to save the data. We could also use shifter to square or divide a number just by shifting. For example the number 2 which is 10 will become 100 when shifted left with shift in 0, or become 101 with 1 shift in. we can use this technique to manipulate the binary number as we want it.

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4 Bit Shifter
Schematics

Symbol

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CMD File and Expected Results

Shift Left Right No Left Right Left left Right Left No

S 1 0 1 0 0 1 0 0 1 0 0

S 0 1 0 0 1 0 1 1 0 1 0

SR_IN 0 1 1 0 0 0 1 1 0 1

SL_IN 1 0 1 0 0 1 1 0 0 1

D 0 0 0 1 1 1 0 1 1 0 0

D 1 0 0 0 0 0 0 0 0 1 1

D 2 0 0 1 1 1 1 0 0 0 1

D 3 0 0 0 0 0 0 1 1 0 0

Q 0 1 0 1 0 0 1 1 0 0 0

Q 1 0 0 0 1 1 0 1 0 0 1

Q 2 0 0 1 0 0 0 0 1 1 1

Q 3 0 1 0 1 0 1 0 1 0 0

SL_OU T 0 0 0 0 0 0 1 0 0 0

SR_OU T 0 0 0 0 1 0 0 1 0 0

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Simulation (Read Components)

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Appendix
TABLE OF CONTENTS
MUX SCHEMATICS
CMD FILE AND EXPECTED RESULTS SIMULATION BUILT IN AND MOTOROLA

7 7 8 8 9 9 9 9 10 10 10 10 11 11 11 11 12 12 12 12

4 INPUT OR SCHEMATICS
CMD FILE AND EXPECTED RESULTS SIMULATION BUILT IN AND MOTOROLA

3 INPUT AND GATE SCHEMATICS

CMD FILE AND EXPECTED RESULTS SIMULATION

AND GATE SCHEMATICS

CMD FILE AND EXPECTED RESULTS SIMULATION

OR GATE SCHEMATICS
CMD FILE AND EXPECTED RESULTS SIMULATION

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2 Variable Multiplexer
Schematics

Symbol

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CMD File and Expected Results

Simulation

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4 Input OR Gate
Schematics

Symbol

CMD File and Expected Results

Simulation

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3 Input AND Gate

Schematics

Symbol

CMD File and Expected Results

Simulation

10 | P a g e

AND Gate
Schematics

AND Gate CMD file Expected Results Expected Results A B 0 0 0 1 1 0 1 1 AND Gate Simulation

Q 0 0 0 1

11 | P a g e

OR Gate
Schematics

OR Gate CMD file and expected results

Expected Results A 0 0 1 1 OR Gate Simulation

B 0 1 0 1

Q 0 1 1 1

12 | P a g e