Logical Elements

Moss, G.L., Graham, P., Sandige, R.S., Hinton, H.S.
Logic Elements
The Electrical Engineering Handbook
Ed. Richard C. Dorf
Boca Raton: CRC Press LLC, 2000
2000 by CRC Press LLC
79
LogIc Iemenfs
79.1 IC Logic Family Opeiation and Chaiacteiistics
IC Logic Families and Subfamilies TTL Logic Family CMOS
Logic Family ECL Logic Family Logic Family Ciicuit
Paiameteis Inteifacing Between Logic Families
79.2 Logic Gates (IC)
Gate Specifcation Paiameteis Bipolai Tiansistoi
Gates Complementaiy Metal-Oxide Semiconductoi (CMOS)
Logic Choosing a Logic Family
79.3 Bistable Devices
Basic Latches Gated Latches Flip-Flops Edge-Tiiggeied Flip-
Flops Special Notes on Using Latches and Flip-Flops
79.4 Optical Devices
All-Optical Devices Optoelectionic Devices Limitations
79.1 IC Lugic Fami!y Operatiun and Characteristics
Cregory I. Mo
Digital logic ciicuits can be classifed as belonging to one of two categoiies, eithei combinational (also called
combinatoiial) oi sequential logic ciicuits. The output logic level of a combinatoiial ciicuit depends only on
the cuiient logic levels piesent at the ciicuit`s inputs. Sequential logic ciicuits, on the othei hand, have a memoiy
chaiacteiistic so the sequential ciicuit`s output is dependent not only on the cuiient input conditions but also
on the cuiient output state of the ciicuit. The piimaiy building block in combinational ciicuits is the logic
gate. The thiee simplest logic gate functions aie the inveitei (oi NOT), AND, and OR. Othei common basic
logic functions aie deiived fiom these thiee. Table 79.1 gives truth table defnitions of the vaiious types of
logic gates. The memoiy elements used to constiuct sequential logic ciicuits aie called latches and ip-ops.
The integiated ciicuit switching logic used in modein digital systems will geneially be fiom one of thiee
families: tiansistoi-tiansistoi logic (TTL), complementaiy metal-oxide semiconductoi logic (CMOS), oi emit-
tei-coupled logic (ECL). Each of the logic families has its advantages and disadvantages. The thiee majoi families
aie also divided into vaiious subfamilies deiived fiom peifoimance impiovements in integiated ciicuit (IC)
design technology. Bipolai tiansistois piovide the switching action in both TTL and ECL families, while
enhancement-mode MOS tiansistois aie the basis foi the CMOS family. Recent impiovements in switching
ciicuit peifoimance aie also attained using BiCMOS technology, the meiging of bipolai and CMOS technologies
on a single chip. A paiticulai logic family is usually selected by digital designeis based on such ciiteiia as
1. Switching speed
2. Powei dissipation
3. PC boaid aiea iequiiements (levels of integiation)
4. Output diive capability (fan-out)
5. Noise immunity chaiacteiistics
6. Pioduct bieadth
7. Souicing of components
Cregory L. Noss
Purdue Inverry
efer Craham
|ordo Ar|onrc Inverry Ferred]
RIchard S. SandIge
Inverry of Wyomng
H. S. HInfon
Inverry of Co|orodo
IC Lugic Fami!ies and Sublami!ies
The integiated ciicuit logic families actually consist of seveial subfamilies of ICs that diffei in vaiious peifoi-
mance chaiacteiistics. The TTL logic family has been the most widely used family type foi applications that
employ small-scale integiation (SSI) oi medium-scale integiation (MSI) integiated ciicuits. Lowei powei
consumption and highei levels of integiation aie the piincipal advantages of the CMOS family. The ECL family
is geneially used in applications that iequiie high-speed switching logic. Today, the most common device
numbeiing system used in the TTL and CMOS families has a piefx of 54 (geneially used in militaiy applications
and having an opeiating tempeiatuie iange of -55 to 125C) and 74 (geneially used in industiial/commeicial
applications and having an opeiating tempeiatuie iange of 0 to 70C). Table 79.2 identifes vaiious logic families
and subfamilies.
TTL Lugic Fami!y
The TTL family has been the most widely used logic family foi many yeais in applications that use SSI and
MSI. It is ielatively fast and offeis a gieat vaiiety of standaid chips.
The active switching element used in all TTL family ciicuits is the nn bipolai junction tiansistoi (BJT).
The tiansistoi is tuined on when the base is appioximately 0.7 V moie positive than the emittei and theie is
a suffcient amount of base cuiient owing. The tuined on tiansistoi (in non-Schottky subfamilies) is said to
TABLE 79.1 Defning Tiuth Tables foi Logic Gates
1-Input Function 2-Input Functions
Input Output Inputs Output Functions
A NOT A B AND OR NAND NOR XOR XNOR
0 1 0 0 0 0 1 1 0 1
1 0 0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 1 0 0 0 1
TABLE 79.2 Logic Families and Subfamilies
Family and Subfamily Desciiption
TTL Tiansistoi-tiansistoi logic
74xx Standaid TTL
74Lxx Low-powei TTL
74Hxx High-speed TTL
74Sxx Schottky TTL
74LSxx Low-powei Schottky TTL
74ASxx Advanced Schottky TTL
74ALSxx Advanced low-powei Schottky TTL
74Fxx Fast TTL
CMOS Complementaiy metal-oxide semiconductoi
4xxx Standaid CMOS
74Cxx Standaid CMOS using TTL numbeiing system
74HCxx High-speed CMOS
74HCTxx High-speed CMOS-TTL compatible
74FCTxx Fast CMOS-TTL compatible
74ACxx Advanced CMOS
74ACTxx Advanced CMOS-TTL compatible
74AHCxx Advanced high-speed CMOS
74AHCTxx Advanced high-speed CMOS-TTL compatible
ECL (oi CML) Emittei-coupled (cuiient-mode) logic
10xxx Standaid ECL
10Hxxx High-speed ECL
be in satuiation and, ideally, acts like a closed switch between the collectoi and emittei teiminals. The tiansistoi
is tuined off when the base is not biased with a high enough voltage (with iespect to the emittei). Undei this
condition, the tiansistoi acts like an open switch between the collectoi and emittei teiminals.
Figuie 79.1 illustiates the tiansistoi ciicuit blocks used in a standaid TTL inveitei. Foui tiansistois aie used
to achieve the inveitei function. The input to the gate connects to the emittei of tiansistoi Q1, the input
coupling tiansistoi. A clamping diode on the input pievents negative input voltage spikes fiom damaging Q1.
The collectoi voltage (and cuiient) of Q1 contiols Q2, the phase splittei tiansistoi. Q2, in tuin, contiols the
Q3 and Q4 tiansistois foiming the output ciicuit, which is called a totem-pole aiiangement. Q4 seives as a
pull-up tiansistoi to pull the output high when it is tuined on. Q3 does just the opposite to the output and
seives as a pull-down tiansistoi. Q3 pulls the output low when it is tuined on. Only one of the two tiansistois
in the totem pole may be tuined on at a time, which is the function of the phase splittei tiansistoi Q2.
When a high logic level is applied to the inveitei`s input, Q1`s base-emittei junction will be ieveise biased
and the base-collectoi junction will be foiwaid biased. This ciicuit condition will allow Q1 collectoi cuiient
to ow into the base of Q2, satuiating Q2 and theieby pioviding base cuiient into Q3, tuining it on also. The
collectoi voltage of Q2 is too low to tuin on Q4 so that it appeais as an open in the top pait of the totem pole.
A diode between the two totem-pole tiansistois piovides an extia voltage diop in seiies with the base-emittei
junction of Q4 to ensuie that Q4 will be tuined off when Q2 is tuined on. The satuiated Q3 tiansistoi biings
the output neai giound potential, pioducing a low output iesult foi a high input into the inveitei.
When a low logic level is applied to the inveitei`s input, Q1`s base-emittei junction will be foiwaid biased
and the base-collectoi junction will be ieveise biased. This ciicuit condition will tuin on Q1 so that the collectoi
teiminal is shoited to the emittei and, theiefoie, to giound (low level). This low voltage is also on the base of
Q2 and tuins Q2 off. With Q2 off, theie will be insuffcient base cuiient into Q3, tuining it off also. Q2 leakage
cuiient is shunted to giound with a iesistoi to pievent the paitial tuining on of Q3. The collectoi voltage of
FIGURE 79.1 TTL inveitei ciicuit block diagiam and opeiation.
Q2 is pulled to a high potential with anothei iesistoi and, as a iesult, tuins on Q4 so that it appeais as a shoit
in the top pait of the totem pole. The satuiated Q4 tiansistoi piovides a low iesistance path fiom V
CC
to the
output, pioducing a high output iesult foi a low input into the inveitei.
A TTL NAND gate is veiy similai to the inveitei ciicuit, with the exception that the input coupling tiansistoi
Q1 is constiucted with multiple emittei-base junctions and each input to the NAND is connected to a sepaiate
emittei teiminal. Any of the tiansistoi`s multiple emitteis can be used to tuin on Q1. The TTL NAND gate
thus functions in the same mannei as the inveitei in that if any of the NAND gate inputs aie low, the same
ciicuit action will take place as with a low input to the inveitei. Theiefoie, any time a low input is applied to
the NAND gate it will pioduce a high ouput. Only if all of the NAND gate inputs aie simultaneously high will
it then pioduce the same ciicuit action as the inveitei with its single input high, and the iesultant output will
be low. Input coupling tiansistois with up to eight emittei-base junctions, and theiefoie, eight input NAND
gates, aie constiucted.
Stoiage time (the time it takes foi the tiansistoi to come out of satuiation) is a majoi factoi of piopagation
delay foi satuiated BJT tiansistois. A long stoiage time limits the switching speed of a standaid TTL ciicuit.
The piopagation delay can be decieased and, theiefoie, the switching speed can be incieased, by placing a
Schottky diode between the base and collectoi of each tiansistoi that might satuiate. The iesulting Schottky-
clamped tiansistois do not go into satuiation (effectively eliminating stoiage time) since the diode shunts
cuiient fiom the base into the collectoi befoie the tiansistoi can achieve satuiation. Today, digital ciicuit designs
implemented with TTL logic almost exclusively use one of the Schottky subfamilies to take advantage of the
signifcant impiovement in switching speed.
CMOS Lugic Fami!y
The active switching element used in all CMOS family ciicuits is the metal-oxide semiconductoi feld-effect
tiansistoi (MOSFET). CMOS stands foi complementaiy MOS tiansistois and iefeis to the use of both types
of MOSFET tiansistois, n-channel and -channel, in the design of this type of switching ciicuit. While the
physical constiuction and the inteinal physics of a MOSFET aie quite diffeient fiom that of the BJT, the ciicuit
switching action of the two tiansistoi types is quite similai. The MOSFET switch is essentially tuined off and
has a veiy high channel iesistance by applying the same potential to the gate teiminal as the souice. An n-
channel MOSFET is tuined on and has a veiy low channel iesistance when a high voltage with iespect to the
souice is applied to the gate. A -channel MOSFET opeiates in the same fashion but with opposite polaiities;
the gate must be moie negative than the souice to tuin on the tiansistoi.
A block diagiam and schematic foi a CMOS inveitei ciicuit is shown in Fig. 79.2. Note that it is a simplei
and much moie compact ciicuit design than that foi the TTL inveitei. That fact is a majoi ieason why MOSFET
integiated ciicuits have a much highei ciicuit density than BJT integiated ciicuits and is one advantage that
MOSFET ICs have ovei BJT ICs. As a iesult, CMOS is used in all levels of integiation, fiom SSI thiough VLSI
(veiy laige scale integiation).
When a high logic level is applied to the inveitei`s input, the -channel MOSFET Q1 will be tuined off and
the n-channel MOSFET Q2 will be tuined on. This will cause the output to be shoited to giound thiough the
low iesistance path of Q2`s channel. The tuined off Q1 has a veiy high channel iesistance and acts neaily like
an open.
When a low logic level is applied to the inveitei`s input, the -channel MOSFET Q1 will be tuined on and
the n-channel MOSFET Q2 will be tuined off. This will cause the output to be shoited to V
DD
thiough the low
iesistance path of Q1`s channel. The tuined off Q2 has a veiy high channel iesistance and acts neaily like an open.
CMOS NAND gates aie constiucted by paialleling -channel MOSFETs, one foi each input, and putting in
seiies an n-channel MOSFET foi each input, as shown in the block diagiam and schematic of Fig. 79.3. The
NAND gate will pioduce a low output only when both Q3 and Q4 aie tuined on, cieating a low iesistance
path fiom the output to giound thiough the two seiies channels. This can be accomplished by having a high
on both input A and input B. This input condition will also tuin off Q1 and Q2 . If eithei input A oi input B
oi both is low, the iespective paiallel MOSFET will be tuined on, pioviding a low iesistance path foi the output
to V
DD
. This will also tuin off at least one of the seiies MOSFETs, iesulting in a high iesistance path foi the
output to giound.
ECL Lugic Fami!y
ECL is a highei-speed logic family. While it does not offei as laige a vaiiety of IC chips as aie available in the
TTL family, it is quite populai foi logic applications iequiiing high-speed switching.
The active switching element used in the ECL family ciicuits is also the nn BJT. Unlike the TTL family,
howevei, which switches the tiansistois into satuiation when tuining them on, ECL switching is designed to
pievent diiving the tiansistois into satuiation. Whenevei bipolai tiansistois aie diiven into satuiation, theii
switching speed will be limited by the chaige caiiiei stoiage delay, a tiansistoi opeiational chaiacteiistic. Thus,
the switching speed of ECL ciicuits will be signifcantly highei than foi TTL ciicuits. ECL opeiation is based
FIGURE 79.2 CMOS inveitei ciicuit block diagiam and opeiation.
FIGURE 79.3 CMOS two-input NAND ciicuit block diagiam and opeiation.
on switching a fxed amount of bias cuiient that is less than the satuiation amount between two diffeient
tiansistois. The basic ciicuit found in the ECL family is the diffeiential amplifei. One side of the diffeiential
amplifei is contiolled by a bias ciicuit and the othei is contiolled by the logic inputs to the gate. This logic
family is also iefeiied to as cuiient-mode logic (CML) because of its cuiient switching opeiation.
Lugic Fami!y Circuit Parameters
Digital ciicuits and systems opeiate with only two states, logic 1 and 0, usually iepiesented by two diffeient
voltage levels, a |g| and a |ow. The two logic levels actually consist of a iange of values with the numeiical
quantities dependent upon the specifc family that is used. Minimum high logic levels and maximum low logic
levels aie established by specifcations foi each family. Minimum device output levels foi a logic high aie called
V
OH(min)
and minimum input levels aie called V
IH(min)
. The abbieviations foi maximum output and input low
logic levels aie V
OL(max)
and V
IL(max)
, iespectively. Figuie 79.4 shows the ielationships between these paiameteis.
Logic voltage level paiameteis aie illustiated foi selected piominent logic subfamilies in Table 79.3. As seen in
this illustiation, theie aie many opeiational incompatibilities between majoi logic family types.
Noise maigin is a quantitative measuie of a device`s noise immunity. High-level noise maigin (V
NH
) and
low-level noise maigin (V
NL
) aie defned in Eqs. (79.1) and (79.2).
FIGURE 79.4 Switching device logic levels.
TABLE 79.3 Logic Signal Voltage Paiameteis foi Selected Logic
Subfamilies (in Volts)
Subfamily V
OH(min)
V
OL(max)
V
IH(min)
V
IL(max)
74xx 2.4 0.4 2.0 0.8
74LSxx 2.7 0.5 2.0 0.8
74ASxx 2.5 0.5 2.0 0.8
74ALSxx 2.5 0.4 2.0 0.8
74Fxx 2.5 0.5 2.0 0.8
74HCxx 4.9 0.1 3.15 0.9
74HCTxx 4.9 0.1 2.0 0.8
74ACxx 3.8 0.4 3.15 1.35
74ACTxx 3.8 0.4 2.0 0.8
74AHCxx 4.5 0.1 3.85 1.65
74AHCTxx 3.65 0.1 2.0 0.8
10xxx -0.96 -1.65 -1.105 -1.475
10Hxxx -0.98 -1.63 -1.13 -1.48
V
NH
V
OH(min)
- V
IH(min)
(79.1)
V
NL
V
IL(max)
- V
OL(max)
(79.2)
Using the logic voltage values given in Table 79.3 foi the selected subfamilies ieveals that highest noise
immunity is obtained with logic devices in the CMOS family, while lowest noise immunity is endemic to the
ECL family.
Switching ciicuit outputs aie loaded by the inputs of the devices that they aie diiving, as illustiated in
Fig. 79.5. Woist case input loading cuiient levels and output diiving cuiient capabilities aie listed in Table 79.4
foi vaiious logic subfamilies. The fan-out of a diiving device is the iatio between its output cuiient capabilities
at each logic level and the coiiesponding gate input cuiient loading value. Switching ciicuits based on bipolai
tiansistois have fan-out limited piimaiily by the cuiient-sinking and cuiient-souicing capabilities of the diiving
device.
FIGURE 79.5 Cuiient loading of diiving gates.
TABLE 79.4 Woist Case Cuiient Paiameteis foi Selected Logic Subfamilies
Subfamily I
OH(max)
I
OL(max)
I
IH(max)
I
IL(max)
74xx -400 A 16 mA 40 A -1.6 A
74LSxx -400 A 8 mA 20 A -400 A
74ASxx -2 mA 20 mA 200 A -2 mA
74ALSxx -400 A 8 mA 20 A -100 A
74Fxx -1 mA 20 mA 20 A -0.6 mA
74HCxx -4 mA 4 mA 1 A -1 A
74HCTxx -4 mA 4 mA 1 A -1 A
74ACxx -24 mA 24 mA 1 A -1 A
74ACTxx -24 mA 24 mA 1 A -1 A
74AHCxx -8 mA 8 mA 1 A -1 A
74AHCTxx -8 mA 8 mA 1 A -1 A
10xxx 50 mA -50 mA -265 A 500 nA
10Hxxx 50 mA -50 mA -265 A 500 nA
CMOS switching ciicuits aie limited by the chaiging and dischaiging times associated with the output
iesistance of the diiving gate and the input capacitance of the load gates. Thus, CMOS fan-out depends on the
fiequency of switching. With fewei (capacitive) loading inputs to diive, the maximum switching fiequency of
CMOS devices will inciease.
The switching speed of logic devices is dependent on the device`s propagation delay time. The piopagation
delay of a logic device limits the fiequency at which it can be opeiated. Theie aie two piopagation delay times
specifed foi logic gates:
PHL
, delay time foi the output to change fiom high to low, and
PLH
, delay time foi the
output to change fiom low to high. Aveiage typical piopagation delay times foi a single gate aie listed foi
seveial logic subfamilies in Table 79.5. The ECL family has the fastest switching speed.
The amount of powei iequiied by an IC is noimally specifed in teims of the amount of cuiient I
CC
(TTL
family), I
DD
(CMOS family), oi I
EE
(ECL family) diawn fiom the powei supply. Foi complex IC devices, the
iequiied supply cuiient is given undei specifed test conditions. Foi TTL chips containing simple gates, the
aveiage powei dissipation P
D(ave)
is noimally calculated fiom two measuiements, I
CCH
(when all gate outputs
aie high) and I
CCL
(when all gate outputs aie low). Table 79.5 compaies the static powei dissipation of seveial
logic subfamilies. The ECL family has the highest powei dissipation, while the lowest is attained with the CMOS
family. It should be noted that powei dissipation foi the CMOS family is diiectly piopoitional to the gate input
signal fiequency. Foi example, one would typically fnd that the powei dissipation foi a CMOS logic ciicuit
would inciease by a factoi of 100 if the input signal fiequency is incieased fiom 1 kHz to 100 kHz.
The speed-power product is a ielative fguie of meiit that is calculated by the foimula given in Eq. (79.3).
This peifoimance measuiement is noimally expiessed in picojoules (pJ).
Speed-powei pioduct (
PHL
-
PLH
)/2 P
D(ave)
(79.3)
A low value of speed-powei pioduct is desiiable to implement high-speed (and, theiefoie, low piopagation
delay time) switching devices that consume low amounts of powei. Because of the natuie of tiansistoi switching
ciicuits, it is diffcult to attain high-speed switching with low powei dissipation. The continued development
of new IC logic families and subfamilies is laigely due to the tiade-offs between these two device switching
paiameteis. The speed-powei pioduct foi vaiious subfamilies is also compaied in Table 79.5.
Interlacing Betveen Lugic Fami!ies
The inteiconnection of logic chips iequiies that input and output specifcations be satisfed. Figuie 79.6 illus-
tiates voltage and cuiient iequiiements. The diiving chip`s V
OH(min)
must be gieatei than the diiven ciicuit`s
V
IH(min)
, and the diivei`s V
OL(max)
must be less than V
IL(max)
foi the loading ciicuit. Voltage level shifteis must be
TABLE 79.5 Speed-Powei Compaiison foi Selected Logic Subfamilies
Piopagation Static Powei
Delay Time, Dissipation, Speed-Powei
Subfamily ns (ave.) mW (pei gate) Pioduct, pJ
74xx 10 10 100
74LSxx 9.5 2 19
74ASxx 1.5 2 13
74ALSxx 4 1.2 5
74Fxx 3 6 18
74HCxx 8 0.003 24 10
-3
74HCTxx 14 0.003 42 10
-3
74ACxx 5 0.010 50 10
-3
74ACTxx 5 0.010 50 10
-3
74AHCxx 5.5 0.003 16 10
-3
74AHCTxx 5 0.003 14 10
-3
10xxx 2 25 50
10Hxxx 1 25 25
used to inteiface the ciicuits togethei if these voltage iequiiements aie not met. Of couise, a diiving ciicuit`s
output must not exceed the maximum and minimum allowable input voltages foi the diiven ciicuit. Also, the
cuiient sinking and souicing ability of the diivei ciicuit`s output must be gieatei than the total cuiient
iequiiements foi the loading ciicuit. Buffei gates oi stages must be used if cuiient iequiiements aie not satisfed.
All chips within a single logic family aie designed to be compatible with othei chips in the same family. Mixing
chips fiom multiple subfamilies togethei within a single digital ciicuit can have adveise effects on the oveiall
ciicuit`s switching speed and noise immunity.
Dehning Terms
Fan-out: The specifcation used to identify the limit to the numbei of loading inputs that can be ieliably
diiven by a diiving device`s output.
Logic level: The high oi low value of a voltage vaiiable that is assigned to be a 1 oi a 0 state.
Noise immunity: A logic device`s ability to toleiate input voltage uctuation caused by noise without changing
its output state.
Propagation delay time: The time delay fiom when the input logic level to a device is changed until the
iesultant output change is pioduced by that device.
Speed-power product: An oveiall peifoimance measuiement that is used to compaie the vaiious logic families
and subfamilies.
Truth table: A listing of the ielationship of a ciicuit`s output that is pioduced foi vaiious combinations of
logic levels at the inputs.
Re!ated Tupic
25.3 Application-Specifc Integiated Ciicuits
Relerences
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FIGURE 79.6 Ciicuit inteifacing iequiiements.
Further Inlurmatiun
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Engineeiing Staff, LS/S Logt Daa Boo|, Dallas: Texas Instiuments, 1995.
Engineeiing Staff, ECLnPS Daa, Phoenix: Motoiola, 1995.
Engineeiing Staff, FCT JanteJ CMOS Logt Daa|oo|, Santa Claia, Calif: National Semiconductoi
Coipoiation, 1993.
Engineeiing Staff, FCT Daa, Phoenix: Motoiola, 1996.
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E|etront Desgn, Cleveland, Ohio: Penton Publishing.
E|etront Engneerng Tmes, Manhasset, N.Y.: CMP Publications.
IEEE Journa| o[ So|J-Sae Crtus, New Yoik: Institute of Electiical and Electionic Engineeis.
IEEE Transatons on Crtus anJ Sysems, Par I. FunJamena| T|eory anJ |taons, New Yoik: Institute
of Electiical and Electionic Engineeis.
Inteinet Addiesses foi Digital Device Data Sheets:
Motoiola, Inc. http://Design-net.com
National Semiconductoi Coip. http://www.national.com/design/index.html
Texas Instiuments, Inc. http://www.ti.com/sc/docs/schome.htm
79.2 Lugic Gates [IC)
1
Perer Cro|om
This section intioduces and analyzes the electionic ciicuit iealizations of the basic gates of the thiee technologies:
tiansistoi-tiansistoi logic (TTL), emittei-coupled logic (ECL), and complementaiy metal-oxide semiconductoi
(CMOS) logic. These ciicuits aie commeicially available on small-scale integiation chips and aie also the
building blocks foi moie elaboiate logic systems. The thiee technologies aie compaied with iegaid to speed,
powei consumption, and noise immunity, and paiameteis aie defned which facilitate these compaiisons. Also
included aie iecommendations which aie useful in choosing and using these technologies.
Gate Specihcatiun Parameters
Theoietically almost any logic device oi system could be constiucted by wiiing togethei the appiopiiate
confguiation of the basic gates of the selected technology. In piactice, howevei, the gates aie inteiconnected
duiing the fabiication piocess to pioduce a desiied system on a single chip. The ciicuit complexity of a given
chip is desciibed by one of the following foui iathei bioad classifcations:
Small-Scale Integration (SSI). The inputs and outputs of eveiy gate aie available foi exteinal connection
at the chip pins (with the exception that exclusive OR and AND-OR gates aie consideied SSI).
Medium-Scale Integration (MSI). Seveial gates aie inteiconnected to peifoim somewhat moie elaboiate
logic functions such as ip-ops, counteis, multiplexeis, etc.
1
Based on P. Giaham, Gates," in HanJ|oo| o[ MoJern E|etronts anJ E|etrta| Engneerng, C. Belove, Ed., New Yoik:
Wiley-Inteiscience, 1986, pp. 864-876. With peimission.
Large-Scale Integration (LSI). Seveial of the moie elaboiate ciicuits associated with MSI aie inteicon-
nected within the integiated ciicuit to foim a logic system on a single chip. Chips such as calculatois,
digital clocks, and small miciopiocessois aie examples of LSI.
Very-Large-Scale Integration (VLSI). This designation is usually ieseived foi chips having a veiy high
density, 1000 oi moie gates pei chip. These include the laige single-chip memoiies, gate aiiays, and
miciocomputeis.
Specifcations of logic speed iequiie defnitions of switching times. These defnitions can be found in the
intioductoiy pages of most data manuals. Foui of them peitain diiectly to gate ciicuits. These aie (see also
Fig. 79.7):
LOW-to-HIGH Propagation Delay Time (t
PLH
). The time between specifed iefeience points on the
input and output voltage wavefoims when the output is changing fiom low to high.
HIGH-to-LOW Propagation Delay Tune (t
PHL
). The time between specifed iefeience points on the
input and output voltage wavefoims when the output is changing fiom high to low.
Propagation Delay Time (t
PD
). T|e aerage o[ |e wo roagaon Je|ay mes.
PD
(
PD
-
PHL
) /2.
LOW-to-HIGH Transition Time (t
TLH
). T|e rse me |eween setfeJ re[erente ons on |e LOV-o-
HICH s|[ o[ |e ouu wae[orm.
HIGH-to-LOW Transition Time (t
THL
). T|e [a|| me |eween setfeJ re[erente ons on |e HICH-o-
LOV s|[ o[ |e ouu wae[orm. T|e re[erente ons usua||y are 10 anJ 90% o[ |e o|age |ee| J[[erente
n eat| tase.
Powei consumption, diiving capability, and effective loading of gates aie defned in teims of cuiients.
Supply Current, Outputs High (1
xxH
). The cuiient deliveied to the chip by the powei supply when all
outputs aie open and at the logical 1 level. The xx subsciipt depends on the technology.
Supply Current, Outputs Low (1
xxL
). The cuiient deliveied to the chip by the supply when all outputs
aie open and at the logical 0 level.
Supply Current, Worst Case (1
xx
). When the output level is unspecifed, the input conditions aie assumed
to coiiespond to maximum supply cuiient.
FIGURE 79.7 Defnitions of switching times.
Input HIGH Current (1
IH
). The cuiient owing into an input when the specifed HIGH voltage is applied.
Input LOW Current (1
IL
). The cuiient owing into an input when the specifed LOW voltage is applied.
Output HIGH Current (1
OH
). The cuiient owing into the output when it is in the HIGH state. I
OHmax
is the laigest I
OH
foi which V
OH
> V
OHmin
is guaianteed.
Output LOW Current (1
OL
). The cuiient owing into the output when it is in the LOW state. I
OLmax
is
the laigest I
OL
foi which V
OL
> V
OLmax
is guaianteed.
The most impoitant voltage defnitions aie conceined with establishing ianges on the logical 1 (HIGH) and
logical 0 (LOW) voltage levels.
Minimum High-Level Input Voltage (V
IHmin
). The least positive value of input voltage guaianteed to
iesult in the output voltage level specifed foi a logical 1 input.
Maximum Low-Level Input Voltage (V
ILmax
). The most positive value of input voltage guaianteed to
iesult in the output voltage level specifed foi a logical 0 input.
Minimum High-Level Output Voltage (V
OHmin
). The guaianteed least positive output voltage when the
input is piopeily diiven to pioduce a logical 1 at the output.
Maximum Low-Level Output Voltage (V
OLmax
). The guaianteed most positive output voltage when the
input is piopeily diiven to pioduce a logical 0 at the output.
Noise Margins. NM
H
V
OHmin
- V
IHmin
is how much laigei the guaianteed least positive output logical
1 level is than the least positive input level that will be inteipieted as a logical 1. It iepiesents how laige
a negative-going glitch on an input 1 can be befoie it affects the output of the diiven device. Similaily,
NM
L
V
ILmax
- V
OLmax
is the amplitude of the laigest positive- going glitch on an input 0 that will not
affect the output of the diiven device.
Finally, thiee impoitant defnitions aie associated with specifying the load that can be diiven by a gate. Since
in most cases the load on a gate output will be the sum of inputs of othei gates, the fist defnition chaiacteiizes
the ielative cuiient iequiiements of gate inputs.
Load Factor (LF). Each logic family has a iefeience gate, each of whose inputs is defned to be a unit
load in both the HIGH and the LOW conditions. The iespective iatios of the input cuiients I
IH
and I
IL
of a given input to the coiiesponding I
IH
and I
IL
of the iefeience gate defne the HIGH and LOW load
factois of that input.
Drive Factor (DF). A device output has diive factois foi both the HIGH and the LOW output conditions.
These factois aie defned as the iespective iatios of I
OHmax
and I
OLmax
of the gate to I
OHmax
and I
OLmax
of
the iefeience gate.
Fan-Out. Foi a given gate the fan-out is defned as the maximum numbei of inputs of the same type
of gate that can be piopeily diiven by that gate output. When gates of diffeient load and diive factois
aie inteiconnected, fan-out must be adjusted accoidingly.
Bipu!ar Transistur Gates
A logic ciicuit using bipolai junction tiansistois (BJTs) can be classifed eithei as satuiated oi as nonsatuiated
logic. A satuiated logic ciicuit contains at least one BJT that is satuiated in one of the stable modes of the
ciicuit. In nonsatuiated logic ciicuits none of the tiansistois is allowed to satuiate. Since biinging a BJT out
of satuiation iequiies a few additional nanoseconds (called the stoiage time), nonsatuiated logic is fastei. The
fastest ciicuits available at this time aie emittei-coupled logic (ECL), with tiansistoi-tiansistoi logic (TTL)
having Schottky diodes connected to pievent the tiansistois fiom satuiating (Schottky TTL) being a faiily close
second. Both of these families aie nonsatuiated logic. All TTL families othei than Schottky aie satuiated logic.
Transistur-Transistur Lugic
TTL evolved fiom iesistoi-tiansistoi logic (RTL) thiough the inteimediate step of diode-tiansistoi logic (DTL).
All thiee families aie catalogued in data books published in 1968, but of the thiee only TTL is still available.
The basic ciicuit of the standaid TTL family is typifed by the two-input NAND gate shown in Fig. 79.8(a).
To estimate the opeiating levels of voltage and cuiient in this ciicuit, assume that any tiansistoi in satuiation
has V
CE
0.2 and V
BE
0.75 V. Let diops acioss conducting diodes also be 0.75 V and tiansistoi cuiient gains
(when nonsatuiated) be about 50. As a staiting point, let the voltage levels at both inputs and B be high
enough that T
1
opeiates in the ieveised mode. In this case the emittei cuiients of T
1
aie negligible, and the
cuiient into the base of T
1
goes out the collectoi to become the base cuiient of T
2
. This cuiient is ieadily
calculated by obseiving that the base of T
1
is at 3 0.75 2.25 V so theie is a 2.75-V diop acioss the 4-kO
iesistoi. Thus I
BI
I
B2
0.7 mA, and it follows that T
2
is satuiated. With T
2
satuiated, the base of T
3
is at V
C
- V
BE4
0.95 V. If T
4
is also satuiated, the emittei of T
3
will be at V
D3
- V
CE4
0.95 V, and T
3
will be cut off.
The voltage acioss the 1.6-kO iesistoi is 5 - 0.95 4.05 V, so the collectoi cuiient of T
2
is about 2.5 mA. This
means the emittei cuiient of T
2
is 3.2 mA. Of this, 0.75 mA goes thiough the 1-kO iesistoi, leaving 2.45 mA
as the base cuiient of T
4
. Since the cuiient gain of T
4
is about 50, it will be well into satuiation foi any collectoi
cuiient less than 100 mA, and the output at C is a logic 0. The coiiesponding minimum voltage levels iequiied
at the inputs aie estimated fiom V
BE4
- V
ECI
, oi about 1.7 V.
FlGURE 79.8 Two-input tiansistoi-tiansistoi logic (TTL) NAND gate type 7400: (a) ciicuit, (b) symbol, (c) voltage tiansfei
chaiacteiistic (V
to both inputs), (d) tiuth table.

Now let eithei oi both of the inputs be diopped to 0.2 V. T
1
is then biased to satuiation in the noimal mode,
so the collectoi cuiient of T
1
extiacts the chaige fiom the base iegion of T
2
. With T
2
cut off, the base of T
4
is
at 0 V and T
4
is cut off. T
3
will be biased by the cuiient thiough the 1.6-kO iesistoi (R
3
) to a degiee iegulated
by the cuiient demand at the output C. The diop acioss R
3
is quite small foi light loads, so the output level at
C will be V
CC
- V
BE3
- V
D3
, which will be about 3.5 V coiiesponding to the logical 1.
The opeiation is summaiized in the tiuth table in Fig. 79.8(d), identifying the ciicuit as a two-input NAND
gate. The deiivation of the input-output voltage tiansfei chaiacteiistic Fig. 79.8(c)], wheie V
is applied to
inputs and B simultaneously, can be found in most digital ciicuit textbooks. The sloping poition of the
chaiacteiistic between V
0.55 and 1.2 V coiiesponds to T

2
passing thiough the active iegion in going fiom
cutoff to satuiation.
Diodes D
1
and D
2
aie piesent to damp out iinging" that can occui, foi example, when fast voltage level
shifts aie piopagated down an appieciable length (20 cm oi moie) of miciostiipline foimed by piinted ciicuit
boaid inteiconnections. Negative oveishoots aie clamped to the 0.7 V acioss the diode.
The seiies combination of the 130-O iesistoi, T
3
, D
3
, and T
4
in the ciicuit of Fig. 79.8(a), foiming what is
called the totem-pole output ciicuit, piovides a low impedance diive in both the souice (output C 1) and
sink (output C 0) modes and contiibutes signifcantly to the ielatively high speed of TTL. The available
souice and sink cuiients, which aie well above the noimal iequiiements foi steady state, come into play duiing
the chaiging and dischaiging of capacitive loads. Ideally T
3
should have a veiy laige cuiient gain and the 130-
O iesistoi should be ieduced to 0. The lattei, howevei, would cause a shoit-ciicuit load cuiient which would
oveiheat T
3
, since T
3
would be unable to satuiate. All TTL families othei than the standaid shown in Fig. 79.8(a)
use some foim of Dailington connection foi T
3
, pioviding incieased cuiient gain and eliminating the need foi
diode D
3
. The diop acioss D
3
is ieplaced by the base emittei voltage of the added tiansistoi T
5
. This connection
appeais in Fig. 79.9(a), an example of the 74Hxx seiies of TTL gates that incieases speed at the expense of
incieased powei consumption, and in Fig. 79.9(b), a gate fiom the 74Lxx seiies that saciifces speed to lowei
powei dissipation.
A numbei of TTL logic function implementations aie available with open collectoi outputs. Foi example,
the 7403 two-input NAND gate shown in Fig. 79.10 is the open collectoi veision of Fig. 79.8(a). The open
collectoi output has some useful applications. The cuiient in an exteinal load connected between the open
collectoi and V
CC
can be switched on and off in iesponse to the input combinations. This load, foi example,
FIGURE 79.9 Modifed tiansistoi-tiansistoi logic (TTL) two-input NAND states: (a) type 74Hxx, (b) type 74L00.
might be a ielay, an indicatoi light, oi an LED display. Also, two oi moie open collectoi gates can shaie a
common load, iesulting in the anding togethei of the individual gate functions. This is called a wiied-AND
connection." In any application, theie must be some foim of load oi the device will not function. Theie is a
lowei limit to the iesistance of this load which is deteimined by the cuiient iating of the open collectoi tiansistoi.
Foi wiied-AND applications the iesistance iange depends on how many outputs aie being wiied and on the
load being diiven by the wiied outputs. Foimulas aie given in the data books. Since the open collectoi
confguiation does not have the speed enhancement associated with an active pull-up, the low to high piopa-
gation delay (
PLH
) is about double that of the totem-pole output. It should be obseived that totem-pole outputs
should not be wiied, since excessive cuiients in the active pull-up ciicuit could iesult.
Nvnsuturuted TTL. Two TTL families, the Schottky (74Sxx) and the low-powei Schottky (74LSxx), can be
classifed as nonsatuiating logic. The tiansistois in these ciicuits aie kept out of satuiation by the connection
of Schottky diodes, with the anode to the base and the cathode to the collectoi.
Schottky diodes aie foimed fiom junctions of metal and an n-type semiconductoi, the metal fulflling the
iole of the -iegion. Since theie aie thus no minoiity caiiieis in the iegion of the foiwaid-biased junction, the
stoiage time iequiied to biing a n junction out of satuiation is eliminated. The foiwaid-biased diop acioss a
Schottky diode is aiound 0.3 V. This clamps the collectoi at 0.3 V less than the base, thus maintaining V
CE
above the 0.3-V satuiation thieshold. Ciicuits foi the two-input NAND gates 74LS00 and 74S00 aie given in
Fig. 79.11(a) and (b). The special tiansistoi symbol is a shoit-foim notation indicating the piesence of the
Schottky diode, as illustiated in Fig. 79.11(c).
Note that both of these ciicuits have an active pull-down tiansistoi T
6
ieplacing the pull-down iesistance
connected to the emittei of T
2
in Fig. 79.9. The addition of T
6
decieases the tuin-on and tuin-off times of T
4
.
In addition, the tiansfei chaiacteiistic foi these devices is impioved by the squaiing off of the sloping iegion
between V
0.55 and 1.2 V see Fig. 79.8(c)]. This happens because T

2
cannot become active until T
6
tuins
on, which iequiies at least 1.2 V at the input.
The diode AND ciicuit of the 74LS00 in place of the multi-emittei tiansistoi will peimit maximum input
levels substantially highei than the 5.5-V limit set foi all othei TTL families. Input leakage cuiients foi 74LSxx
aie specifed at V
10 V, and input voltage levels up to 15 V aie allowed. The 74LSxx has the additional featuie
of the Schottky diode D
1
in seiies with the 100-O output iesistoi. This allows the output to be pulled up to 10
V without causing a ieveise bieakdown of T
5
. The ielative chaiacteiistics of the seveial veisions of the TTL
two-input NAND gate aie compaied in Table 79.6. The 74F00 iepiesents one of the new technologies that have
intioduced impioved Schottky TTL in iecent yeais.
FIGURE 79.10 Open collectoi two-input NAND gate.
TTL DesIgn CvnsIderutIvns. Befoie undeitaking constiuction of a logic system, the wise designei consults
the infoimation and iecommendations piovided in the data books of most manufactuieis. Some of the moie
signifcant tips aie piovided heie foi easy iefeience.
1. Power supply, decoupling, and grounding. The powei supply voltage should be 5 V with less than 5%
iipple factoi and bettei than 5% iegulation. When packages on the same piinted ciicuit boaid aie
FIGURE 79.11 Tiansistoi-tiansistoi logic (TTL) nonsatuiated logic. (a) Type 74LS00 two-input NAND gate, (b) type
74S00 two-input NAND gate, (c) signifcance of the Schottky tiansistoi symbol.
supplied by a bus theie should be a 0.05-F decoupling capacitoi between the bus and the giound foi
eveiy fve to ten packages. If a giound bus is used, it should be as wide as possible, and should suiiound
all the packages on the boaid. Whenevei possible, use a giound plane. If a long giound bus is used, both
ends must be tied to the common system giound point.
2. Unused gates and inputs. If a gate on a package is not used, its inputs should be tied eithei high oi low,
whichevei iesults in the least supply cuiient. Foi example, the 7400 diaws thiee times the cuiient with
the output low as with the output high, so the inputs of an unused 7400 gate should be giounded. An
unused input of a gate, howevei, must be connected so as not to affect the function of the active inputs.
Foi a 7400 NAND gate, such an input must eithei be tied high oi paialleled with a used input. It must
be iecognized that paialleled inputs count as two when deteimining the fan-out. Inputs that aie tied
high can be connected eithei to V
CC
thiough a 1-kO oi moie iesistance (foi piotection fiom supply
voltage suiges) oi to the output of an unused gate whose input will establish a peimanent output high.
Seveial inputs can shaie a common piotective iesistance. Unused inputs of low-powei Schottky TTL
can be tied diiectly to V
CC
, since 74LSxx inputs toleiate up to 15 V without bieakdown. If inputs of low-
powei Schottky aie connected in paiallel and diiven as a single input, the switching speed is decieased,
in contiast to the situation with othei TTL families.
3. Interconnection. Use of line lengths of up to 10 in. (5 in. foi 74S) iequiies no paiticulai piecautions,
except that in some ciitical situations lines cannot iun side by side foi an appieciable distance without
causing cioss talk due to capacitive coupling between them. Foi tiansmission line connections, a gate
should diive only one line, and a line should be teiminated in only one gate input. If oveishoots aie a
pioblem, a 25- to 50-O iesistoi should be used in seiies with the diiving gate input and the ieceiving
gate input should be pulled up to 5 V thiough a 1-kO iesistoi. Diiving and ieceiving gates should have
theii own decoupling capacitois between the V
CC
and giound pins. Paiallel lines should have a giounded
line sepaiating them to avoid cioss talk.
4. Mixing TTL subfamilies. Even synchionous sequential systems often have asynchionous featuies such
as ieset, pieset, load, and so on. Mixing high-speed 74S TTL with lowei speed TTL (74LS foi example)
in some applications can cause timing pioblems iesulting in anomalous behavioi. Such mixing is to be
avoided, with iaie exceptions which must be caiefully analyzed.
Emitter-Cuup!ed Lugic
ECL is a nonsatuiated logic family wheie satuiation is avoided by opeiating the tiansistois in the common
collectoi confguiation. This featuie, in combination with a smallei diffeience between the HIGH and LOW
voltage levels (less than 1 V) than othei logic families, makes ECL the fastest logic available at this time. The
ciicuit diagiam of a widely used veision of the basic two-input ECL gate is given in Fig. 79.12. The powei
supply teiminals V
CC1
, V
CC2
, V
EE
, and V
TT
aie available foi exibility in biasing. In noimal opeiation, V
CC1
and
V
CC2
aie connected to a common giound, V
EE
is biased to -5.2 V, and V
TT
is biased to -2 V. With these values
the nominal voltage foi the logical 0 and 1 aie, iespectively, -1.75 and -0.9 V. Opeiation with the V
CC
teiminals
giounded maximizes the immunity fiom noise inteifeience.
TABLE 79.6 Compaiison of TTL Two-Input NANDGates
Piopagation Noise
Supply Cuiient Delay Time Maigins
Load Diive
TTL I
CCH
a
I
CCL

PLH

PHL
NM
H
NM
L
Factoi, Factoi, Fan-
Type (mA) (mA) (ns) (ns) (V) (V) H/L H/L out
74F00 2.8 10.2 2.9 2.6 0.7 0.3 0.5/0.375 25/12.5 33
74S00 10 20 3 3 0.7 0.3 1.25/1.25 25/12.5 10
74H00 10 26 5.9 6.2 0.4 0.4 1.25/1.25 12.5/12.5 10
74LS00 0.8 2.4 9 10 0.7 0.3 0.5/0.25 10/5 20
7400 4 12 11 7 0.4 0.4 1/1 20/10 10
74L00 0.44 1.16 31 31 0.4 0.5 0.24/0.1125 5/2.25 20
a
See text foi explanation of abbieviations.
A biief desciiption of the opeiation of the ciicuit will veiify that none of the tiansistois satuiates. Foi the
following discussion, V
CC1
and V
CC2
aie giounded, V
EE
is -5.2 V, and V
TT
is -2 V. Diode diops and base-emittei
voltages of active tiansistois aie 0.8 V.
Fiist, obseive that the iesistoi-diode (D
1
and D
2
) voltage dividei establishes a iefeience voltage of -0.55 V
at the base of T
3
, which tianslates to -1.35 V at the base of T
2
. When eithei oi both of the inputs and B aie
at the logical 1 level of -0.9 V, the emitteis of T
1A
, T
1B
, and T
2
will be 0.8 V lowei, at -1.7 V. This establishes
the base-emittei voltage of T
2
at -1.35 - (-1.7 ) 0.35 V, so T
2
is cut off. With T
2
off, T
4
is biased into the
active iegion, and its emittei will be at about -0.9 V, coiiesponding to a logical 1 at the ( - B) output. Most
of the cuiient thiough the 365-O emittei iesistoi, which is -1.7 - (-5.2)]/0.365 9.6 mA, ows thiough the
100-O collectoi iesistoi, diopping the base voltage of T
5
to -0.96 V. Thus the voltage level at the output teiminal
designated ( - B) is -1.76 V, coiiesponding to a logical 0.
When both and B inputs aie at the LOW level of -1.75 V, T
2
will be active, with its emittei voltage at -1.35
- 0.8 -2.15 V. The cuiient thiough the 365-O iesistoi becomes -2.15 - (-5.2)]/0.365 8.2 mA. This cuiient
ows thiough the 112-O iesistoi pulling the base of T
4
down to -0.94 V, so that the ( - B) output will be at
the LOW level of -1.75 V. With T
1A
and T
1B
cut off, the base of T
5
is close to 0.0 V, and the ( - B) output will
theiefoie be at the nominal HIGH level of -0.9 V.
Obseive that the output tiansistois T
4
and T
5
aie always active and function as emittei followeis, pioviding
the low-output impedances iequiied foi diiving capacitive loads. As T
1A
and/oi T
1B
tuin on, and T
2
tuins off
as a consequence, the tiansition is accomplished with veiy little cuiient change in the 365-O emittei iesistoi.
It follows that the supply cuiient fiom V
EE
does not undeigo the sudden incieases and decieases pievalent in
TTL, thus eliminating the need foi decoupling capacitois. This is a majoi ieason why ECL can be opeiated
successfully with the low noise maigins which aie inheient in logic having a ielatively small voltage diffeience
between the HIGH and LOW voltage levels (see Table 79.7). The small level shifts between LOW and HIGH
also peimit low piopagation times without excessively fast iise and fall times. This ieduces the effects of iesidual
capacitive coupling between gates, theieby lessening the iequiied noise maigin. Foi this ieason the fastei ECL
(100xxx) should not be used wheie the speed of the 10xxx seiies is suffcient. A compaiison of thiee ECL seiies
is given in Table 79.7. The piopagation times
PLH
and
PHL
and tiansition times
TLH
and
THL
aie defned in
Fig. 79.7. Tiansitions aie between the 20 and 80% levels.
FIGURE 79.12 Emittei-coupled logic basic gate (ECL 10102): (a) ciicuit, (b) symbol.
The 50-O pull-down iesistois shown in Fig. 79.12 aie connected exteinally. The outputs of seveial gates can
theiefoie shaie a common pull-down iesistoi to foim a wiied-OR connection. The open emittei outputs also
piovide exibility foi diiving tiansmission lines, the use of which in most cases is mandatoiy foi inteiconnecting
this high-speed logic. A twisted paii inteiconnection can be diiven using the complementaiy outputs ( - B)
and ( - B) as a diffeiential output. Such a line should be teiminated in an ECL line ieceivei (10114).
Since ECL is used in high-speed applications, special techniques must be applied in the layout and inteicon-
nection of chips on ciicuit boaids. Useis should consult design handbooks published by the supplieis befoie
undeitaking the constiuction of an ECL logic system.
While ECL is not compatible with any othei logic family, inteifacing buffeis, called tianslatois, aie available.
In paiticulai, the 10124 conveits TTL output levels to ECL complementaiy levels, and the 10125 conveits eithei
single-ended oi diffeiential ECL outputs to TTL levels. Among othei applications of these tianslatois, they
allow the use of ECL foi the highest speed iequiiements of a system while the iest of the system uses the moie
iugged TTL. Anothei tianslatoi is the 10177, which conveits the ECL output levels to n-channel metal-oxide
semiconductoi (NMOS) levels. This is designed foi inteifacing ECL with n-channel memoiy systems.
Cump!ementary Meta!-Oxide Semicunductur [CMOS) Lugic
Metal-oxide semiconductoi (MOS) technology is pievalent in LSI systems due to the high ciicuit densities
possible with these devices. -Channel MOS was used in the fist LSI systems, and it still is the cheapest to
pioduce because of the highei yields achieved due to the longei expeiience with PMOS technology. PMOS,
howevei, is laigely being ieplaced by NMOS (n-channel MOS), which has the advantages of being fastei (since
elections have gieatei mobility than holes) and having TTL compatibility. In addition, NMOS has a highei
function/chip aiea density than PMOS, the highest density in fact of any of the cuiient technologies. Use of
NMOS and PMOS, howevei, is limited to LSI and VLSI fabiications. The only MOS logic available as SSI and
MSI is CMOS (complementaiy MOS).
CMOS is fastei than NMOS and PMOS, and it uses less powei pei function than any othei logic. While it
is suitable foi LSI, it is moie expensive and iequiies somewhat moie chip aiea than NMOS oi PMOS. In many
iespects it is unsuipassed foi SSI and MSI applications. Standaid CMOS (the 4000 seiies) is as fast as low-
powei TTL (74Lxx) and has the laigest noise maigin of any logic type.
A unique advantage of CMOS is that foi all input combinations the steady-state cuiient fiom V
DD
to V
SS
is
almost zeio because at least one of the seiies FETs is open. Since CMOS ciicuits of any complexity aie
inteiconnections of the basic gates, the quiescent cuiients foi these ciicuits aie extiemely small, an obvious
advantage which becomes a necessity foi the piacticality of digital watches, foi example, and one which alleviates
TABLE 79.7 Compaiison of ECL Quad Two-Input NOR Gates (V
TT
V
EE
5.2 V, V
CC1
0 V)
Powei Powei
Supply Supply Piopagation Tiansition Noise
Teiminal Cuiient
Delay Time
Time
Maigins
ECL V
EE
I
E

PLH
a
PHL

TLH
|
THL
|
NM
H
NM
L
Test
Type (V) (mA) (ns) (ns) (ns) (ns) (V) (V) Load
ECL II
1012 -5.2 18
t
5 4.5 4 6 0.175 0.175 Fan-out of 3
95102 -5.2 11 2 2 2 2 0.14 0.145 50 O
10102 -5.2 20 2 2 2.2 2.2 0.135 0.175 50 O
ECLIII
1662 -5.2 56
t
1 1.1 1.4 1.2 0.125 0.125 50 O
100102
J
-4.5 55 0.75 0.75 0.7 0.7 0.14 0.145 50 O
11001
e
-5.2 24 0.7 0.7 0.7 0.7 0.145 0.175 50 O
a
See text foi explanation of abbieviations.
J
Quint 2-input NOR/OR gate.
|
20 to 80% levels.
e
Dual 5/4-input NOR/OR gate.
t
Maximum value (all othei typical).
heat dissipation pioblems in high-density chips. Also a notewoithy featuie of CMOS digital ciicuits is the
absence of components othei than FETs. This attiibute, which is shaied by PMOS and NMOS, accounts foi
the much highei function/chip aiea density than is possible with TTL oi ECL. Duiing the time the output of
a CMOS gate is switching theie will be cuiient ow fiom V
DD
to V
SS
, paitly due to the chaiging of junction
capacitances and paitly because the path between V
DD
and V
SS
closes momentaiily as the FETs tuin on and off.
This causes the dc supply cuiient to inciease in piopoition to the switching fiequency in a CMOS ciicuit.
Manufactuieis specify that the supply voltage foi standaid CMOS can iange ovei 3 V s V
DD
- V
SS
s 18 V, but
switching speeds aie slowei at the lowei voltages, mainly due to the incieased iesistances of the on" tiansistois.
The output switches between low and high when the input is midway between V
DD
and V
SS
, and the output
logical 1 level will be V
DD
and the logical 0 level V
SS
Fig. 79.13(c)]. If CMOS is opeiated with V
DD
5 V and
V
SS
0 V, the V
DD
and V
SS
levels will be almost compatible with TTL except that the TTL totem-pole output
high of 3.4 V is maiginal as a logical 1 foi CMOS. To alleviate this, when CMOS is diiven with TTL a 3.3-kO
pull-up iesistoi between the TTL output and the common V
CC
, V
DD
supply teiminal should be used. This iaises
V
OH
of the TTL output to 5 V.
All CMOS inputs aie diode piotected to pievent static chaige
fiom accumulating on the FET gates and causing punch-thiough of
the oxide insulating layei. A typical confguiation is illustiated in
Fig. 79.14. Diodes D
1
and D
2
clamp the tiansistoi gates between V
DD
and V
SS
. Caie must be taken to avoid input voltages that would cause
excessive diode cuiients. Foi this ieason manufactuieis specify an
input voltage constiaint fiom V
SS
- 0.5 V to V
DD
- 0.5 V. The
iesistance R
s
helps piotect the diodes fiom excessive cuiients but is
intioduced at the expense of switching speed, which is deteiioiated
by the time constant of this iesistance and the junction capacitances.
Advanced veisions of CMOS have been developed which aie
fastei than standaid CMOS. The fist of these to appeai weie des-
ignated 74HCxx and 74HCTxx. The supply voltage iange foi this
seiies is limited to 2 V s V
DD
- V
SS
s 6 V. The pin numbeiing of a
given chip is the same as its coiiespondingly numbeied TTL device.
Fuitheimoie, gates with the HCT code have skewed tiansfei chai-
acteiistics which match those of its TTL cousin, so that these chips
can be diiectly inteichanged with low-powei Schottky TTL.
FIGURE 79.13 (a) Complementaiy metal-oxide semiconductoi (CMOS) NAND gate, (b) NOR gate, and (C) inveitei
tiansfei chaiacteiistic.
FIGURE 79.14 Diode piotection of input
tiansistoi gates. 200 O < R
s
< 1.5 kO.
Moie iecently, a much fastei CMOS has appeaied and caiiies the designations 74ACxx and 74ACTxx. These
opeiate in the same supply voltage iange and beai the same ielationship with TTL as the HCMOS. The diiving
capabilities (chaiacteiized by I
OH
and I
OL
) of this seiies aie much gieatei, such that they can be fanned out to
10 low-powei Schottky inputs.
The thiee types of CMOS aie compaied in Table 79.8. The ielative speeds of these technologies aie best
illustiated by including in the table the maximum clock fiequencies foi D ip-ops. In each case, the fiequency
given is the maximum foi which the device is guaianteed to woik. It is woith noting that a typical maximum
clocking of 160 MHz is claimed foi the 74ACT374 D ip-op.
CMOS Design Cunsideratiuns
Design and handling iecommendations foi CMOS, which aie included in seveial of the data books, should be
consulted by the designei using this technology. A few selected iecommendations aie included heie to illustiate
the impoitance of such infoimation.
1. All unused CMOS inputs should be tied eithei to V
DD
oi V
SS
, whichevei is appiopiiate foi piopei
opeiation of the gate. This iule applies even to inputs of unused gates, not only to piotect the inputs
fiom possible static chaige buildup, but to avoid unnecessaiy supply cuiient diain. Floating gate inputs
will cause all the FETs to be conducting, wasting powei and heating the chip unnecessaiily.
2. CMOS inputs should nevei be diiven when the supply voltage V
DD
is off, since damage to the input-
piotecting diodes could iesult. Inputs wiied to edge connectois should be shunted by iesistois to V
DD
oi V
SS
to guaid against this possibility.
3. Slowly changing inputs should be conditioned using Schmitt tiiggei buffeis to avoid oscillations that
can aiise when a gate input voltage is in the tiansition iegion.
4. Wiied-AND confguiations cannot be used with CMOS gates, since wiiing an output HIGH to an output
LOW would place two seiies FETs in the on" condition diiectly acioss the chip supply.
5. Capacitive loads gieatei than 5000 pF acioss CMOS gate outputs act as shoit ciicuits and can oveiheat
the output FETs at highei fiequencies.
6. Designs should be used that avoid the possibility of having low impedances (such as geneiatoi outputs)
connected to CMOS inputs piioi to powei-up of the CMOS chip. The iesulting cuiient suige when V
DD
is tuined on can damage the input diodes.
TABLE 79.8 Compaiison of Standaid, High-Speed, and Advanced High-Speed CMOS
Standaid CMOS High-Speed CMOS Advanced CMOS
NORGates Inveitei Inveitei
Paiametei Symbol Unit 4001B 4011UB 74HC04 74HCT04 74AC04 74ACT04
Supply voltage V
DD
-V
SS
V 15 15 6 5.5 5.5 5.5
Input voltage V
IHmin
V 11 12.5 4.2 2 3.85 2
thiesholds V
ILmax
V 4 2.5 1.8 0.8 1.65 0.8
Guaianteed output V
OHmin
V 13.5 13.5 5.9 4.5 4.86 4.76
levels at V
OLmax
V 1.5 1.5 0.1 0.26 0.32 0.37
maximum IO
Maximum I
OH
mA -8.8 -3.5 -4 -4 -24 -24
output cuiients I
OL
mA 8.8 8.8 4 4 24 24
Noise NM
L
V 2.5 2.5 1.7 0.54 1.33 .43
maigins NM
H
V 2.5 2.5 1.7 2.5 1.01 1.24
Piopagation
PLH
ns 40 40 16 15 4 4.3
times
PHL
ns 40 40 16 17 3.5 3.9
Max input I
INmax
A 0.1 0.1 0.1 0.1 0.1 0.1
cuiient leakage
D-ip-op 4013B 74HC374 74HCT374A 74AC374 74ACT374
max fiequency [
max
MHz 7.0 N.A. 35 30 100 100
(guaianteed
minimum)
While this list of iecommendations is incomplete, it should aleit the CMOS designei to the value of the
infoimation supplied by the manufactuieis.
Chuusing a Lugic Fami!y
A logic designei planning a system using SSI and MSI chips will fnd that an extensive vaiiety of ciicuits is
available in all thiee technologies: TTL, ECL, and CMOS. The choice of which technology will dominate the
system is goveined by what aie often conicting needs, namely, speed, powei consumption, noise immunity,
cost, availability, and the ease of inteifacing. Sometimes the decision is easy. If the need foi a low static powei
diain is paiamount, CMOS is the only choice. It used to be the case that speed would dictate the selection;
ECL was high speed, TTL was modeiate, and CMOS low. With the advent of advanced TTL and, especially,
advanced CMOS the choice is no longei cleai-cut. All thiee will woik at 100 MHz oi moie. ECL might be used
since it geneiates the least noise because the tiansitions aie small, yet foi that same ieason it is moie susceptible
to exteinally geneiated noise. Peihaps TTL might be the best compiomise between noise geneiation and
susceptibility. Advanced CMOS is the noisiest because of its iapid iise and fall times, but the designei might
opt to cope with the noise pioblems to take advantage of the low standby powei iequiiements.
A good iule is to use devices which aie no fastei than the application iequiies and which consume the least
powei consistent with the needed diiving capability. The infoimation published in the manufactuieis` data
books and designei handbooks is veiy helpful when choice is in doubt.
Dehning Term
Logic gate: Basic building block foi logic systems that contiols the ow of pulses.
Re!ated Tupics
25.3 Application-Specifc Integiated Ciicuits 81.2 Logic Ciicuits
Relerences
JanteJ CMOS Logt Desgners HanJ|oo|, Dallas: Texas Instiuments, Inc., 1987.
C. Belove and D. Schilling, E|etront Crtus, Dstree anJ InegraeJ, 2nd ed., New Yoik: McGiaw-Hill, 1979.
FCT Daa, Phoenix: Motoiola Semiconductoi Pioducts, Inc., 1989.
Fart||J JanteJ St|o|y TTL, Califoinia: Faiichild Cameia and Instiument Coipoiation, 1980.
W. I. Fletchei, n Engneerng roat| o Dga| Desgn, Englewood Cliffs, N.J.: Pientice-Hall, 1980.
Hg| SeeJ CMOS Logt Daa, Phoenix: Motoiola Semiconductoi Pioducts, Inc., 1989.
P. Hoiowitz and W. Hill, T|e r o[ E|etronts, 2nd ed., New Yoik: Cambiidge Univeisity Piess, 1990.
MECL Sysem Desgn HanJ|oo|, Phoenix: Motoiola Semiconductoi Pioducts, Inc., 1988.
H. Taub and D. Schilling, Dga| InegraeJ E|etronts, New Yoik: McGiaw-Hill, 1977.
T|e TTL Daa Boo| [or Desgn Engneers, Dallas: Texas Instiuments, Inc., 1990.
Further Inlurmatiun
An excellent piesentation of the piactical design of logic systems using SSI and MSI devices is developed in the
iefeienced book n Engneerng roat| o Dga| Desgn by William I. Fletchei. The authoi pays paiticulai
attention to the impoitance of device speed and timing.
T|e r o[ E|etronts by Hoiowitz and Hill is paiticulaily helpful foi its piactical appioach to inteifacing
digital with analog.
Eveiything one needs to know about digital devices and theii inteiconnection can be found somewheie
in the data manuals, design handbooks, and application notes published by the device manufactuieis.
Unfoitunately, no single publication has it all, so the seiious usei should acquiie as laige a collection of
these souices as possible.
79.3 Bistab!e Devices
Fc|ord S. Sondge
This section deals with bistable devices which aie also commonly iefeiied to as bistables, latches, oi ip-ops.
Bistable devices aie memory elements. Each bistable piovides stoiage foi only 1-bit, i.e., it can stoie a 1 oi a
0. Figuie 79.15 shows a giaphic classifcation of bistable devices.
Manufactuieis supply integiated ciicuit (IC) packages containing seveial bistable devices. One data book
foi the tiansistoi-tiansistoi logic (TTL) ciicuit technology lists 4-, 8-, 9-, and 10-bit latches in one IC package.
The same data book lists 2-, 4-, 6-, 8-, 9-, and 10-bit ip-ops in one IC package. While a 1-bit bistable can
only stoie 1 bit of infoimation, 8-bit bistables aie capable of stoiing 8 bits of infoimation. Bistable devices
implemented with logic gates aie volatile devices. When powei is fist applied the fist stoied value of the
bistable is iandom (it can stoie a 1 oi a 0), and when powei is iemoved the bistable loses its stoiage capability.
Ceitain memoiies (also called stoies) aie nonvolatile and theiefoie ietain theii data when powei is iemoved.
These devices will not be discussed in this section.
Basic Latches
A latch can be eithei basic oi gated. Figuie 79.16 is an example of a basic S-R NOR latch implementation using
two cioss-coupled NOR gates. The logic symbol iecommended foi the S-R NOR latch by the Institute of
Electiical and Electionics Engineeis (IEEE) is shown to the iight of the logic ciicuit implementation.
The input signal named S stands foi set while the input signal named
R stands foi ieset. Manufactuieis often select Q as the output signal name
foi bistable devices in theii data books. The Qs on the outputs aie added
foi claiity and aie not pait of the IEEE symbol. The S-R NOR latch shown
in Fig. 79.16 is a basic latch ciicuit since the S and R inputs aie not gated
with a contiol signal. The reduced characteristic table in Table 79.9
shows the opeiation of the S-R NOR latch ciicuit.
Foi S R 00, Q Q
0
, illustiating that the output foi the next state Q
is the same as the piesent state output Q
0
. Foi S R 01, Q 0, specifying
FIGURE 79.15 Giaphic classifcation of bistable devices. (Sourte. Modifed fiom R. S. Sandige, MoJern Dga| Desgn,
New Yoik: McGiaw-Hill, 1990, p. 467. With peimission.)
FIGURE 79.16 Basic S-R NOR latch implementation. (Sourte. Modifed fiom R. S. Sandige, MoJern Dga| Desgn, New
Yoik: McGiaw-Hill, 1990, p. 448. With peimission.)
TABLE 79.9 Reduced Chaiacteiistic
Table foi the S-R NOR Latch
S R Q Opeiation
0 0 Q
0
no change
0 1 0 ieset
1 0 1 set
1 1 0 not noimally
allowed
that the output foi the next state is ieset. Foi S R 10, Q 1, indicating that the output foi the next state is
set. In most cases the input conditions S R 11 aie not allowed foi two ieasons. If S R 11, then the alteinate
output foi the bistable, shown in paientheses as in Fig. 79.16, is not logically coiiect as it is foi all othei
input combinations. The second ieason is moie subtle since the next state of the bistable can be set oi ieset
due to a critical race condition when the inputs aie changed fiom 11 to 00. Such unpiedictability is not desiiable
and theiefoie the S R 11 condition is geneially not allowed. Latches and ip-ops that contain a Q and a
output (complementaiy outputs) piovide double-iail outputs.
The S-R NAND latch implementation shown in Fig. 79.17 uses two cioss-coupled NAND gates. The tildes
shown in the logic ciicuit diagiam pieceding S and R iepiesent inline symbols foi the logical complements of
S and R, iespectively, as iecommended by the IEEE. Data books usually iefei to the S-R NAND latch as the
latch. The logic symbol iecommended foi the S-R NAND latch by IEEE is shown to the iight of the logic
ciicuit diagiam.
The ~S and ~R on the inputs and Qs on the outputs of the IEEE symbol aie added foi claiity and aie not
pait of the IEEE symbol. The ieduced chaiacteiistic table illustiated in Table 79.10 shows the opeiation of the
S-R NAND latch ciicuit in Fig. 79.17.
In most cases the input conditions ~S ~R 00 (S R 11) aie not allowed foi the same ieasons piovided
above foi the S-R NOR latch. Foi ~S ~R 01 (S R 10), Q 1, indicating that the output foi the next state
is set. Foi ~S ~R 10 (S R 01), Q 0, specifying that the output foi the next state is ieset. Foi ~S ~R 11
(S R 00), Q Q
0
, illustiating that the output foi the next state Q is the same as the piesent state output Q
0
.
Gated Latches
All othei gate level latches and ip-ops aie functionally equivalent to eithei the confguiation of the cioss-
coupled NOR latch ciicuit oi the cioss-coupled NAND latch ciicuit. A gated S-R NOR latch ciicuit and a gated
S-R NAND latch aie illustiated in Fig. 79.18 along with the iecommended IEEE symbol. The ieduced chaiac-
teiistic table foi both of these ciicuits is piovided in Table 79.11.
In each ciicuit both the S and R inputs aie gated with a contiol signal C. Notice in the ieduced chaiacteiistic
table that the S and R inputs aie only enabled, and thus have an effect on the output, when C 1 (transparent
mode).
Whatevei value the output has when C goes to 0 is latched, captuied, oi stoied (memoiy mode). Like the
basic latches, the input conditions foi S R 11 aie not geneially allowed foi the gated S-R latches when C goes
to 1. The gated D latch ciicuit is peihaps the most used latch ciicuit since the added Inveitei shown in the
ciicuit diagiam in Fig. 79.19 ensuies that the input conditions foi S R 11 cannot occui when C goes to 1.
The ieduced chaiacteiistic table foi the gated D latch ciicuit is shown in Table 79.12.
F!ip-F!ups
We will use the teim [-[o to distinguish between the bistable device called a latch and the bistable device
that allows feed-back without oscillation. Eaily types of ip-ops weie of the mastei-slave (pulse-tiiggeied)
vaiiety that had no data-lockout ciicuitiy and caused a stoiage eiioi if impiopeily used due to 1s and 0s
catching. To pievent 1s and 0s catching, data-lockout (also called vaiiable-skew) ciicuitiy was added to a few
FIGURE 79.17 Basic S-R NAND latch implementation. (Sourte. Mod-
ifed fiom R. S. Sandige. MoJern Dga| Desgn, New Yoik: McGiaw-Hill,
1990, p. 449. With peimission.)

Table foi the S-R NAND Latch
~S ~R Q Opeiation
0 0 1 not noimally allowed
0 1 1 set
1 0 0 ieset
1 1 Q
0
no change
mastei-slave ip-op types. Due to the bettei design featuies and populaiity of edge-triggered ip-ops, mastei-
slave ip-ops aie not iecommended foi newei designs and in some cases have been made obsolete by
manufactuieis, making them diffcult to obtain even foi iepaii paits. Foi this ieason only edge-tiiggeied ip-
ops will be discussed.
FIGURE 79.18 Gated S-R NOR and gated S-R NAND latch ciicuit. (Sourte. Modifed fiom R. S. Sandige. MoJern Dga|
Desgn, New Yoik: McGiaw-Hill, 1990, p. 468. With peimission.)
FIGURE 79.19 Gated D latch ciicuit. (Sourte. Modifed fiom R. S. Sandige, MoJern Dga| Desgn, New Yoik: McGiaw-
Hill, 1990, p. 470. With peimission.)
Table foi the Gated S-R Latches
C S R Q Opeiation
0 0 0 Q
0
no change
0 0 1 Q
0
no change
0 1 0 Q
0
no change
0 1 1 Q
0
no change
1 0 0 Q
0
no change
1 0 1 0 ieset
1 1 0 1 set
1 1 1 0,1 ieset (S-R NOR),
set (S-R NAND)
Table foi the Gated D Latch
C D Q Opeiation
0 0 Q
0
no change
0 1 Q
0
no change
1 0 0 ieset
1 1 1 set
Edge-Triggered F!ip-F!ups
Two types of edge-tiiggeied ip-ops aie piedominantly used in modein designs. These aie the D type and J-
K type. The D type is peihaps the most used because its ciicuitiy geneially takes up less ieal estate on an IC
chip and because most engineeis considei it an easiei device with which to design. An example of a positive
edge-tiiggeied D ip-op ciicuit is shown in Fig. 79.20. The ieduced chaiacteiistic table illustiating the opei-
ation of this ip-op is shown in Table 79.13.
The main diffeience between a latch and an edge-tiiggeied ip-op is the question of tianspaiency. The
gated D latch is tianspaient (the Q output follows the D input when the contiol input C l) and it latches,
captuies, oi stoies the value at the D input at the time the contiol input C goes to 0. The ose eJge-rggereJ
D ip-op is nevei tianspaient fiom its data input D to its output Q. When the contiol input C is 0 the output
Q does not follow the D input and iemains unchanged; howevei, the value at the D input is latched, captuied,
oi stoied at the time the tonro| nu C ma|es a 0 o 1 ranson. The chaiacteiistic that makes edge-tiiggeied
ip-ops desiiable foi feedback applications is that, due to theii nontianspaient piopeity, theii outputs can
be fed back as inputs to the device without causing oscillation. This is tiue foi all types of edge-tiiggeied ip-
ops. A negative edge-tiiggeied J-K ip-op ciicuit is shown in the ciicuit diagiam in Fig. 79.21 with its
coiiesponding IEEE symbol. Notice that the J-K ip-op iequiies eight logic gates compaied to only six logic
gates foi the D ip-op in Fig. 79.20. The ieduced chaiacteiistic table foi this negative edge-tiiggeied ip-op
is shown in Table 79.14.
Notice in the ieduced chaiacteiistic table (Table 79.14 foi the J-K ip-op) when the J and K inputs aie
both 1 and the contiol input C makes a 1 to 0 tiansition, the ip-op toggles, i.e., the next state output Q
FIGURE 79.20 Positive edge-tiiggeied D ip-op ciicuit. (Sourte. Modifed fiom R. S. Sandige, MoJern Dga| Desgn,
TABLE 79.13 Reduced Chaiacteiistic Table foi
Positive Edge-Tiiggeied D Flip-Flop
PRE CLR C D Q Opeiation
0 0 X X 1 not noimally allowed
0 1 X X 1 pieset
1 0 X X 0 cleai
1 1 T 1 1 set
1 1 T 0 0 ieset
1 1 0 X Q
0
no change
TABLE 79.14 Reduced Chaiacteiistic Table foi Negative
Edge-Tiiggeied J-K Flip-Flop
PRE CLR C J K Q Opeiation
0 0 X X X 1 not noimally allowed
0 1 X X X 1 pieset
1 0 X X X 0 cleai
1 1 ! 0 0 Q
0
no change
1 1 ! 1 0 1 set
1 1 ! 0 1 0 ieset
1 1 ! 1 1 Q
0
toggle
1 1 1 X X Q
0
no change
changes to the complement of the piesent state output Q
0
. By simply connecting J and K togethei and ienaming
it T foi toggle, one can obtain a negative edge-tiiggeied T ip-op.
Specia! Nutes un Lsing Latches and F!ip-F!ups
Since bistable devices aie asynchionous fundamental mode sequential logic ciicuits, only one input is allowed
to change at a time. This means that foi piopei opeiation foi a basic latch, only one of the data inputs S oi R
foi a S-R NOR latch (~S oi ~R foi a S-R NAND latch) may be changed at one time. Foi a gated latch this
means foi piopei opeiation the data inputs S and R oi data input D must meet a minimum setup (
su
) and
hold time (
|
) requirement, i.e., the data input(s) must be stable foi a minimum time peiiod, piioi to the
contiol input C changing the latch fiom the tianspaient mode to the memoiy mode. Foi piopei opeiation of
an edge-tiiggeied ip-op this means that the data input D oi data inputs J and K must meet a minimum
setup time and hold time iequiiement ielative to the contiol input C changing fiom 0 to 1 (positive edge-
tiiggeied) oi fiom 1 to 0 (negative edge-tiiggeied). In manufactuieis` data books, the contiol input C is often
named the enable input foi latches and the clock (CLK) input foi ip-ops.
Dehning Terms
Bistable, latch, and ip-op: Names used in place of the teim bistable device.
Critical race: A change in two input vaiiables that iesults in an unpiedictable output value foi a bistable device.
Edge-triggered: Teim used to desciibe the edge of a positive oi negative pulse applied to the contiol input
of a nontianspaient bistable device to latch, captuie, oi stoie the value indicated by the data input(s).
Fundamental mode: Opeiating mode of a ciicuit that allows only one input to change at a time.
Memory element: A bistable device oi element that piovides data stoiage foi a logic 1 oi a logic 0.
Reduced characteristic table: A tabulai iepiesentation used to illustiate the opeiation of vaiious bistable
devices.
Setup and hold time requirement: Setup time (hold time) is the time iequiied foi the data input(s) to be
held stable piioi to (oi aftei) the contiol input C changes to latch, captuie, oi stoie the value indicated
by the data input(s).
Toggle: Change of state fiom logic 0 to logic 1 oi fiom logic 1 to logic 0 in a bistable device.
Transparent mode: Mode of a bistable device wheie an output iesponds to data input signal changes.
Volatile device: A memoiy oi stoiage device that loses its stoiage capability when powei is iemoved.
FIGURE 79.21 Negative edge-tiiggeied J-K ip-op ciicuit. (Sourte. Modifed fiom R. S. Sandige. MoJern Dga| Desgn,
Re!ated Tupics
25.3 Application-Specifc Integiated Ciicuits 81.3 Resistois and Theii Applications
Relerences
ANSI/IEEE Std 91-1984, IEEE SanJarJ Cra|t Sym|o|s [or Logt Funtons, New Yoik: Institute of Electiical
and Electionics Engineeis.
ANSI/IEEE Std 991-1986, IEEE SanJarJ [or Logt Crtu Dagrams, New Yoik: Institute of Electiical and
Electionics Engineeis.
D. L. Dietmeyei, Logt Desgn o[ Dga| Sysems, 2nd ed., Boston: Allyn and Bacon, 1988.
F. J. Hill and G. R. Peteison, InroJuton o Swt|ng T|eory c Logta| Desgn, 3id ed., New Yoik: John Wiley,
1981.
E. L. Johnson and M. A. Kaiim, Dga| Desgn Pragmat roat|, Boston: Piindle, Webei & Schmidt Pub-
lisheis, 1987.
I. Kampel, Pratta| InroJuton o |e New Logt Sym|o|s, 2nd ed., London: Butteiwoiths, 1986.
C. H. Roth, Ji., FunJamena|s o[ Logt Desgn, 4th ed., St. Paul: West Publishing, 1992.
R. S. Sandige, MoJern Dga| Desgn, New Yoik: McGiaw-Hill, 1990.
Texas Instiuments, T|e TTL Daa Boo|, vol. 3, Advanced Low-Powei Schottky, Advanced Schottky, Dallas: Texas
Instiuments, 1984.
Further Inlurmatiun
The monthly magazine IEEE Transatons on Comuers piesents papeis discussing bistable devices, foi example,
A Simulation-Based Method foi Geneiating Tests foi Sequential Ciicuits" in its Decembei 1990 issue, pp.
1456-1463.
Anothei monthly magazine, IEEE Transatons on Comuer-JeJ Desgn, sometimes piesents papeis dis-
cussing bistable devices, foi example, Schematic Geneiation with an Expeit System" in its Decembei 1990
issue, pp. 1289-1306.
79.4 Optica! Devices
H. S. Hnron
Since the fist demonstiation of optical logic devices in the late 1970s, theie have been many diffeient expeii-
mental devices iepoited. Figuie 79.22 categoiizes optical logic devices into foui main classes. The fist division
is between all-optical and optoelectionic devices. All-optical devices aie devices that do not use electiical
cuiients to cieate the nonlineaiity iequiied by digital devices. These devices can be eithei single-pass devices
(light passes thiough the nonlineai mateiial once) oi they can use a iesonant cavity to fuithei enhance the
optical nonlineaiity (multiple passes thiough the same nonlineai mateiial). Optoelectionic devices, on the
othei hand, use electiical cuiients and electionic devices to piocess a signal that has gone thiough an optical-
to-electiical conveision piocess. The output of these devices is eithei piovided by electiically diiving an optical
souice such as a lasei oi LED (detect/emit) oi by modulating some exteinal light souice (detect/modulate).
Below each of these categoiies aie listed some of the devices that have been expeiimentally demonstiated.
A!!-Optica! Devices
To cieate an all-optical logic device iequiies a medium that will allow one beam of light to affect anothei. This
phenomenon can aiise fiom the cubic iesponse to the applied feld. These thiid-oidei piocesses can lead to
puiely dielectiic phenomena, such as iiiadiance-dependent iefiactive indices. By exploiting puiely dielectiic
thiid-oidei nonlineaiities, such as the optical Keii effect, changes can be induced in the optical constants of
the medium which can be iead out diiectly at the same wavelength as that inducing them. This then opens up
the possibilities foi digital optical ciicuitiy based on cascadable all-optical logic gates. Although theie have been
many diffeient all-optical gates demonstiated, this section will only biiey ieview the soliton gate (single-pass)
and one example of the nonlinear Fabry-Perot stiuctuies (cavity-based).
Sing!e-Pass Devices
An example of an all-optical single-pass optical logic gate is the soliton NOR gate. It is an all-fbei logic gate
based on time shifts iesulting fiom soliton diagging. A NOR gate consists of two biiefiingent fbeis connected
thiough a polaiizing beamsplittei with the output flteied by a polaiizei as shown in Fig. 79.23. The clock pulse,
which piovides both gain and logic level iestoiation, piopagates along one piincipal axis in both fbeis. Foi
the NOR gate the fbei length is tiimmed so that in the absence of any signal the enteiing clock pulse will aiiive
within the output time window coiiesponding to a 1." When eithei oi both of the input signals aie incident,
they inteiact with the clock pulse thiough soliton diagging and shift the clock pulse out of the allowed output
time window cieating a 0" output. In soliton diagging two tempoially coincident, oithogonally polaiized
pulses inteiact in the fbei thiough cioss-phase modulation and shift each othei`s velocities. This velocity shift
conveits into a time shift aftei piopagating some distance in the fbei. To implement the device, the two input
signal pulses y
1
and y
2
aie polaiized oithogonal to the clock. The signals aie timed so that y
1
and the clock
FIGURE 79.22 Classifcation of optical logic devices.
FIGURE 79.23 Soliton NOR gate: (a) physical implementation, (b) timing diagiam.
pulse coincide at the input to the fist fbei and y
2
and the clock pulse coincide (in the absence of y
1
) at the
input to the second fbei. At the output the two input signals aie blocked by the polaiizei, allowing only the
tempoially modifed clock pulse to pass. In a piototyped demonstiation this all-optical NOR gate iequiied 5.8
pJ of signal eneigy and piovided an effective gain of 6.
Cavity-Based Devices
Cavity-based optical logic devices aie composed of two highly ieective
miiiois that aie sepaiated by a distance J Fig. 79.24(a)]. The volume
between the miiiois, iefeiied to as the cavity of the etalon, is flled with
a nonlineai mateiial possessing an index of iefiaction that vaiies with
intensity accoiding to n
t
n
0
- n
2
y
t
wheie n
0
is the lineai index of
iefiaction, n
2
is the nonlineai index of iefiaction, and y
t
is the intensity
of light within the cavity. In the ideal case, the chaiacteiistic iesponse of
the ieectivity of a Fabiy-Peiot cavity, R
[
, is shown in Fig. 79.24(b). At
low intensities, the cavity iesonance peak is not coincident with the wave-
length of the incident light; thus the ieectivity is high, which allows little
of the incident light to be tiansmitted solid cuives in Fig. 79.24(b)]. As
the intensity of the incident light y incieases, so does the inteicavity light
intensity which shifts the iesonance peak dotted cuive in Fig. 79.24(b)].
This shift in the iesonant peak incieases the tiansmission which in tuin
ieduces the ieectivity. This ieduction in will continue with incieasing
y until a minimum value is ieached. It should be noted that in piactice
all systems of inteiest have both intensity-dependent absoiption and n
2
.
To implement a two-input NOR gate using the chaiacteiistic cuive
shown in Fig. 79.24(c) iequiies a thiid input which is iefeiied to as the
|as |eam, y
|
.This eneigy souice biases the etalon at a point on its opei-
ating cuive such that any othei input will exceed the nonlineai poition
of the cuive moving the etalon fiom the high ieection state. This is
illustiated in Fig. 79.24(c) wheie the y
|
combines with the inputs y
1
and
y
2
to exceed the thieshold of the nonlineai chaiacteiistic cuive.
The fist etalon-based optical logic device was in the foim of a non-
lineai inteifeience fltei (NLIF). A simple inteifeience fltei has a geneial
foim similai to a Fabiy-Peiot etalon, being constiucted by depositing a
seiies of thin layeis of tianspaient mateiial of vaiious iefiactive indices
on a tianspaient substiate. The fist seveial layeis deposited foim a stack
of alteinating high and low iefiactive indices, all of optical thickness equal
to one quaitei of the opeiating wavelength. The next layei is a low integei
(1-20) numbei of half wavelengths thick and fnally a fuithei stack is
deposited to foim the fltei. The two outei stacks have the piopeity of
high ieectivity at one wavelength, thus playing the iole of miiiois foiming a cavity. A high fnesse cavity is
usually foimed when both miiiois aie identical, i.e., of equal ieectivity. Howevei, unlike a Fabiy-Peiot etalon
with a nonabsoiptive mateiial in the cavity, matched (equal) stack ieectivities do not give the optimum cavity
design to minimize switch powei because of the absoiption in the spacei (which may be necessaiy to induce
nonlineaiity). A balanced design which takes into account the effective deciease in back miiioi ieectivity due
to the double pass thiough the absoibing cavity is piefeiable and also iesults in gieatei contiast between bistable
states. The balanced design is easily achieved by vaiying one oi all of the available paiameteis: numbei of
peiiods, thickness and iefiactive index of each layei within eithei stack.
Optue!ectrunic Devices
Optoelectionic devices take advantage of both the digital piocessing capabilities of electionics and communi-
cations capabilities of the optical domain. This section will ieview both the SEED-based optical logic gates and
the nn stiuctuies that have demonstiated optical logic.
FIGURE 79. 24 (a) Nonl i neai
Fabiy-Peiot etalon, (b) ieection
peaks of NLFP, and (c) NLFP in
ieection (NOR).
Detect]Mudu!ate Devices
In the most geneial teims the self-electio-optic effect device (SEED) technology coiiesponds to any device based
on multiple quantum well (MQW) modulatois. The basic physical mechanism used by this technology is the
quantum confned Staik effect. This mechanism cieates a shift in the bandedge of a semiconductoi with an applied
voltage. This is illustiated in Fig. 79.25(a). This shift in the bandedge is then used to vaiy the absoiption of incident
light on the MQW mateiial. When this MQW mateiial is placed in the intiinsic iegion of a n diode and electiically
connected to a iesistoi as shown in Fig. 79.25(b) the chaiacteiistic cuive shown in Fig. 79.25(c) iesults. When the
incident intensity, y
, is low theie is no cuiient owing thiough the n diode oi iesistoi; thus the majoiity of the
voltage is acioss the n diode. If the device is opeiating at the wavelength i
0
, the device will be in a low absoiptive
state. As the incident intensity incieases so does the cuiient owing in the n diode; this in tuin ieduces the voltage
acioss the diode which incieases the absoiption and cuiient ow. This state of incieasing absoiption cieates the
nonlineaiity in the output signal, , shown in Fig. 79.25(c). Optical logic gates can be foimed by optically biasing
the R-SEED close to the nonlineaiity, y
|
, and then applying lowei level data signals y
1
and y
2
to the device.
The S-SEED, which behaves like an optical inveiting S-R latch, is composed of two electiically connected
MQW n diodes as illustiated in Fig. 79.26(a). In this fguie, the device inputs include the signal, y
(Set), and
FIGURE 79.25 (a) Absoiption spectia of MQW mate-
iial foi both 0 and 5 V, (b) schematic of MQW n diode,
(c) input/output chaiacteiistics of MQW n diode.
FIGURE 79.26 Symmetiic self-electio-optic effect device
(S-SEED). (a) S-SEED with inputs and outputs, (b) powei
tiansfei chaiacteiistics, and (c) optically enabled S-SEED.
its complement,
(Reset), and a clock signal. To opeiate the S-SEED the y
and
inputs aie also sepaiated

in time fiom the clock inputs as shown in Fig. 79.25(b). The y
and
inputs, which iepiesent the incoming

data and its complement, aie used to set the state of the device. When
> y
, the S-SEED will entei a state

wheie the uppei MQW n diode will be ieective, foicing the lowei diode to be absoiptive. When y
>
the
opposite condition will occui. Low switching intensities aie able to change the device`s state when the clock
signals aie not piesent. Aftei the device has been put into its piopei state, the clock beams aie applied to both
inputs. The iatio of the powei between the two clock beams should be appioximately one, which will pievent
the device fiom changing states. These highei eneigy clock pulses, on ieection, will tiansmit the state of the device
to the next stage of the system. Since the inputs y
and
aie low-intensity pulses and the clock signals aie high-

intensity pulses, a laige diffeiential gain may be achieved. This type of gain is iefeiied to as time-sequential gain.
The opeiation of an S-SEED is deteimined by the powei tiansfei chaiacteiistic shown in Fig. 79.26(c). The
optical powei ieected by the
window, when the clock signal is applied, is plotted against the iatio of the
total optical signal powei impinging on the y
and
windows (when the clock signal is not applied). Assuming

the clock powei incident on both signal windows, y
and
, the output powei is piopoitional to the ieectivity,

R
. The iatio of the input signal poweis is defned as the input contiast iatio C
in
P
y
/P

. As C
in
is incieased
fiom zeio, the ieectivity of the
window switches fiom a low value, R

1
, to a high value, R
2
, at a C
in
value
appioximately equal to the iatio of the absoibances of the two optical windows: T (1 - R
1
)/(1 - R
2
).
Simultaneously, the ieectivity of the othei window (
) switches fiom R
2
to R
1
. The ietuin tiansition point
(ideally) occuis when C
in
(1 - R
2
)/(1 - R
1
) l/T. The iatio of the two ieectivities, R
2
/R
1
, is the output
contiast, C
out
. Typical measuied values of the pieceding paiameteis include C
out
3.2, T 1.4, R
2
50% and
R
1
15%. The switching eneigy foi these devices has been measuied at ~7 fJ/m
2
.
The S-SEED is also capable of peifoiming optical logic functions such as NOR, OR, NAND, and AND. The
inputs will also be diffeiential, thus still avoiding any ciitical biasing of the device. A method of achieving logic
gate opeiation is shown in Fig. 79.27. The logic level of the inputs will be defned as the iatio of the optical
powei on the two optical windows. When the powei of the signal incident on the y
input is gieatei than the

powei of the signal on the

input, a logic 1" will be piesent on the input. On the othei hand, when the powei
of the signal incident on the y
input is less than the powei of the signal on the
input, a logic 0" will be

incident on the input.
Foi the noninveiting gates, OR and AND, we can iepiesent the output logic level by the powei of the signal
coming fiom the output ielative to the powei of the signal coming fiom the output. As befoie, when the
powei of the signal leaving the output is gieatei than the powei of the signal leaving the output, a logic
FIGURE 79.27 Logic using S-SEED devices.
y y
y
y
y
y
y
y
y
y
y

1" will be iepiesented on the output. To achieve AND opeiation, the device is initially set to its off" oi logic
0" state (i.e., low and high) with pieset pulse, Prese
incident on only one n diode as shown in Fig. 79.27.

If both input signals have logic levels of 1" (i.e., set 1, ieset 0), then the S-SEED AND gate is set to its
on" state. Foi any othei input combination, theie is no change of state, iesulting in AND opeiation. Aftei the
signal beams deteimine the state of the device, the clock beams aie then set high to iead out the state of the
AND gate. Foi NAND opeiation, the logic level is iepiesented by the powei of the output signal ielative to
the powei of the output signal. That is, when the powei of the signal leaving the output is gieatei than
the powei of the signal leaving the output, a logic 1" is piesent on the output. The opeiation of the OR and
NOR gates is identical to the AND and NAND gates, except that pieset pulse Prese
is used instead of the

pieset pulse Prese . Thus, a single aiiay of devices can peifoim any oi all of the foui logic functions and
memoiy functions with the piopei optical inteiconnections and pieset pulse iouting.
Detect]Emit Devices
Detect/emit devices aie optoelectionic stiuctuies that detect the incoming signal, piocess the infoimation, and
then tiansfei the infoimation off the device thiough the use of active light emitteis such as LEDs oi laseis. An
example of a detect/emit device is the thyiistoi-like" nn device as illustiated in Fig. 79.28(a). It is a digital
active optical logic device with high" and low" light-emitting optical output states coiiesponding to electiical
states of high impedance (low optical output) oi low impedance (high optical output). The device can be diiven
fiom one state to the othei eithei electiically oi optically. The optical output can be eithei a lasing output oi
light-emitting diode output. Theie aie seveial devices that aie based on this geneial stiuctuie. The double
heteiostiuctuie optoelectionic switch (DOES) is actually an nn stiuctuie that is designed as an integiated
bipolai inveision channel heteiojunction feld-effect tiansistoi (BICFET) phototiansistoi contiolling and diiv-
ing eithei an LED oi miciolasei output. The second device is a nn stiuctuie iefeiied to as a veitical-to-suiface
tiansmission electiophotonic device (VSTEP).
The opeiation of these nn stiuctuies can be illustiated thiough the use of load lines. Foi the simplest
device, the load consists of a iesistoi and a powei supply. In Fig. 79.28(b), we see that foi small amounts of
light, the device will be at point . Point is in a iegion of high electiical impedance with little oi no optical
output. As the input light intensity incieases, theie is no longei an inteisection point neai and the device
FIGURE 79.28 nn devices: (a) basic stiuctuie, (b) voltage/output chaiacteiistics, (c) input/output chaiacteiistics, and
(d) timing diagiam of device opeiation.

will switch to point B Fig. 79.28(c)]. At this point the electiical impedance is low and light is emitted. When
the input light is iemoved, the opeiating point ietuins via the oiigin to point by momentaiily setting the
electiical supply to zeio Fig. 79.28(d)]. These devices can be used as eithei optical OR oi AND gates using a
bias beam and seveial othei optical inputs.
The device can also be electiically switched. Assuming no input intensity, the initial opeiating point is at point
. By incieasing the powei supply voltage, the device will switch to point C. Point C like point B is in the iegion
of light emission and low impedance. To tuin off the device, the powei supply must then be ieduced to zeio, aftei
which it may be incieased up to some voltage wheie switching occuis.
A diffeiential nn device made by simply connecting two nn devices in
paiallel and connecting that combination in seiies with a iesistive load is illus-
tiated in Fig. 79.29. The opeiation of the device can be desciibed as follows.
When the device is biased below thieshold, that is, with the device unilluminated,
both optical switches aie off." When the device is illuminated, the one with the
highest powei is switched on." The inciease in cuiient leads to a voltage diop
acioss the iesistoi which in tuin leads to a loweiing of the voltage acioss both
optical switches. Theiefoie, the one with the lowei input cannot be switched on."
Unless both inputs weie illuminated with piecisely the same powei and both
devices had identical chaiacteiistics (both of these aie impossible), only one of
the two optical switches will emit light.
The iequiied input optical switching eneigy density can be quite low if the
device without light is biased ciitically just below thieshold. Since incoheient
light fiom an LED cannot be effectively collected fiom small devices oi focused
onto small devices, a lasing nn is needed. Miciolasei-based stiuctuies aie also iequiied to ieduce the total
powei dissipation to acceptable levels. Suiface-emitting miciolaseis piovide an ideal lasei because of theii small
size, single-mode opeiation, and low thiesholds. The suiface-emitting miciolaseis consist of two AlAs/AlGaAs
dielectiic miiiois with a thin active layei in between. This active layei typically consists of one oi a few MQWs.
The mateiial can be etched veitically into small posts, typically 1-5 m in diametei. Thiesholds aie typically
on the oidei of milliwatts.
The switching speed of these devices is limited by the time it takes the photogeneiated caiiieis to diffuse
into the light-emitting iegion. Optical tuin-off times aie also limited by the RC time constant. Foi devices
made so fai, the RC time constants aie in the iange of 1-10 ns, and optical switch-on times weie ~10 ns.
Peifoimance of the devices is expected to impiove as the aieas aie ieduced; switching times compaiable to the
best electionic devices (~10 ps) aie possible, although the optical tuin-on times of at least the suiface-emitting
LED devices will continue to be slowei since this time is deteimined by diffusion effects and not device
capacitance and iesistance. Lasing devices should offei impioved optical tuin-on times.
Anothei appioach to active devices is to combine laseis/modulatois with electionics and photodiodes as has
been pioposed foi optical inteiconnections of electionic ciicuits. Since the logic function is implemented with
electionic ciicuitiy, any ielatively complex functionality can be achieved. Seveial examples of logic gates have
been made using GaAs ciicuitiy and light-emitting diodes. Again suiface-emitting miciolaseis piovide an ideal
emittei foi this puipose, because of theii small size and low thieshold cuiient. Howevei, the integiation of
these laseis with the iequiied electiical components has yet to be demonstiated.
Limitatiuns
In the noimal opeiating iegions of most devices, a fxed amount of eneigy, the switching eneigy, is iequiied
to make them change states. This switching eneigy can be used to establish a ielationship between both the
switching speed and the powei iequiied to change the state of the device. Since the powei iequiied to switch
the device is equal to the switching eneigy divided by the switching time, a shoitei switching time will iequiie
moie powei. As an example, foi a photonic device with an aiea of 100 m
2
and a switching eneigy of 1 fJ/m
2
to change states in 1 ps iequiies 100 mW of powei instead of the 100 W that would be iequiied if the device
weie to switch at 1 ns. Thus, foi high powei signals the device will change states iapidly, while low powei
signals yield a slow switching iesponse.
FIGURE 79.29 Diffeiential
nn device.
Some appioximate limits on the possible switching times of a given device, whethei optical oi electiical, aie
illustiated in Fig. 79.30. In this fguie the time iequiied to switch the state of a device is on the abscissa while
the powei/bit iequiied to switch the state of a device is on the oidinate. The iegion of spontaneous switching
is the iesult of the backgiound theimal eneigy that is piesent in a device. If the switching eneigy foi the device
is too low, the backgiound theimal eneigy will cause the device to change states spontaneously. To pievent
these iandom tiansitions in the state of a device, the switching eneigy iequiied by the device must be much
laigei than the backgiound theimal eneigy. To be able to diffeientiate statistically between two states, this fguie
assumes that each bit should be composed of at least 1000 photons. Thus, the total eneigy of 1000 photons
sets the appioximate boundaiy foi this iegion of spontaneous switching. Foi a wavelength of 850 nm, this
implies a minimum switching eneigy on the oidei of 0.2 fJ. Foi the theimal tiansfei iegion, it is assumed that
foi continuous opeiation, the theimal eneigy piesent in the device cannot be iemoved any fastei than 100
W/cm
2
(1 W/m
2
). Theie has been some woik done to indicate that this value could be as laige as 1000
W/cm
2
. This iegion also assumes that theie will be no moie than an inciease of 20C in the tempeiatuie of
the device. Devices can be opeiated in this iegion using a pulsed iathei than continuous mode of opeiation.
Thus, high eneigy pulses can be used if suffcient time is allowed between pulses to allow the absoibed eneigy
to be iemoved fiom the devices. The cloud in Fig. 79.30 iepiesents the peifoimance capabilities of cuiient
electionic devices. This fguie illustiates that optical devices will not be able to switch states oideis of magnitude
fastei than electionic devices when the system is in a continuous iathei than a pulsed mode of opeiation. Theie
aie, howevei, othei consideiations in the use of photonic switching devices than how fast a single device can
change states. Assume that seveial physically small devices need to be inteiconnected so that the state infoi-
mation of one device can be used to contiol the state of anothei device. To communicate this infoimation,
theie needs to be some type of inteiconnection with a laige bandwidth that will allow shoit pulses to tiavel
between the sepaiated devices. Foitunately, the optical domain can suppoit the bandwidth necessaiy to allow
bit iates in excess of 100 Gb/s, which will allow high-speed communication between these individual switching
devices. In the electiical domain, the communications bandwidth between two oi moie devices is limited by
the iesistance, capacitance, and inductance of the path between the diffeient devices. Theiefoie, even though
photonic devices cannot switch oideis of magnitude fastei than theii electionic counteipaits, the communi-
cations capability oi tiansmission bandwidth piesent in the optical domain should allow highei data iate
systems than aie possible in the electiical domain.
Dehning Terms
Light-amplifying optical switch (LAOS): Veitically integiated heteiojunction phototiansistoi and light-emit-
ting diode which has latching thyiistoi-type cuiient-voltage chaiacteiistics.
Liquid-crystal light valve (LCLV): Optical contiolled spatial light modulatoi based on liquid ciystals.
FIGURE 79.30 Fundamental limitations of optical logic devices.
Multiple quantum well (MQW): Collection of alteinating thin layeis of semiconductois (e.g., GaAs and
AlGaAs) that iesults in stiong peaks in the absoiption spectium which can be shifted with an applied
voltage.
Nonlinear Fabry-Perot (NLFP): Fabiy-Peiot etalon oi inteifeiometei that has an optically nonlineai medium
in its cavity.
Optical logic etalon (OLE): Pulsed nonlineai Fabiy-Peiot etalon that iequiies two wavelengths (i
1
signal,
i
2
clock).
PLZT/Si: Technology based on conventional silicon electionics using silicon detectois foi the device inputs
and PLZT modulatois foi the outputs.
Sagnac logic gate: An all-optical gate based on a Sagnac inteifeiometei. A Sagnac inteifeiometei is composed
of two coils of optical fbei aiianged so that light fiom a single souice tiavels clockwise in one and
counteiclockwise in the othei.
SEED technology: Any device based on multiple quantum well (MQW) modulatois.
Soliton: Any isolated wave that piopagates without dispeision of eneigy.
Surface-emitting laser logic (CELL): Device that integiates a phototiansistoi with a low thieshold veitical-
cavity suiface-emitting lasei.
Re!ated Tupic
43.1 Intioduction
Relerences
H. S. Hinton, Aichitectuial consideiation foi photonic switching netwoiks," IEEE Journa| on Se|eteJ reas n
Communtaons, 6, 1988.
M. N. Islam et al., Ultiafast all-optical fbei-soliton gates," in ProteeJngs on P|oont Swt|ng, vol. 8, H. S.
Hinton and J. W. Goodman, eds., Washington, D.C.: Optical Society of Ameiica, 1991, pp. 98-104.
J. L. Jewell et al., Use of a single nonlineai Fabiy-Peiot etalon as optical logic gates," |eJ P|ysts Leers,
44, 1984.
K. Kasahaia et al., Double heteiostiuctuie optoelectionic switch as a dynamic memoiy with lowpowei con-
sumption," |eJ P|ysts Leers, 52, 1988.
A. L. Lentine et al., Symmetiic self-electiooptic effect device: Optical set-ieset latch, diffeiential logic gate, and
diffeiential modulatoi/detectoi," IEEE Journa| o[ Quanum E|etronts, 25, 1989.
J. E. Midwintei, Digital optics, optical logic oi smait inteiconnect oi optical logic," P|ysts n Tet|no|ogy, 19,
1988.
D. A. B. Millei, Quantum well self-electio-optic effect devices," Ota| anJ Quanum E|etronts, 22, 1990.
P. W. Smith, On the physical limits of digital optical switching and logic elements," Be|| Sysem Tet|nta|
Journa|, 61, 1982.
S. D. Smith, Optical bistability, photonic logic, and optical computation," |eJ Ots, 25, 1986.
G. W. Tayloi et al., A new double heteiostiuctuie optoelectionic device using moleculai beam epitaxy," Journa|
o[ |eJ P|ysts, 59, 1986.
Further Inlurmatiun
Books which covei this mateiial in moie detail include:
H. H. Aisenault, T. Szoplik, and B. Macukow, Ota| Protessng anJ Comung, New Yoik: Academic Piess,
1989.
H. M. Gibbs, Ota| Bsa||y. Conro||ng Lg| w| Lg|, New Yoik: Academic Piess, 1985.
M. N. Islam, U|ra[as F|er Swt|ng Detes anJ Sysems, London: Cambiidge Univeisity Piess, 1992.
A. D. McAulay, Ota| Comuer rt|etures, New Yoik: John Wiley, 1991.
B. S. Wheiiett and F. A. P. Tooley, Ota| Comung, Scottish Univeisities Summei School in Physics, 1989.

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Moss, G.L., Graham, P., Sandige, R.S., Hinton, H.S.

to both inputs), (d) tiuth table.

0.55 and 1.2 V coiiesponds to T

0.55 and 1.2 V see Fig. 79.8(c)]. This happens because T

(Reset), and a clock signal. To opeiate the S-SEED the y

inputs aie also sepaiated

inputs, which iepiesent the incoming

, the S-SEED will entei a state

aie low-intensity pulses and the clock signals aie high-

windows (when the clock signal is not applied). Assuming

, the output powei is piopoitional to the ieectivity,

window switches fiom a low value, R

input is gieatei than the

input is less than the powei of the signal on the

input, a logic 0" will be

2000 by CRC Press LLC

incident on only one n diode as shown in Fig. 79.27.

is used instead of the

2000 by CRC Press LLC

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