1. What is metastability?

When setup or hold window is violated in an flip flop then signal attains a unpredictable value or state known as metastability. 2. What is MTBF? What it signifies? MTBF-Mean Time Before Failure Average time to next failure 3. How chance of metastable state failure can be reduced? Lowering clock frequency Lowering data speed Using faster flip flop 4. What are the advantages of using synchronous reset ? No metastability problem with synchronous reset (provided recovery and removal time for reset is taken care). Simulation of synchronous reset is easy. 5. What are the disadvantages of using synchronous reset ? Synchronous reset is slow. Implementation of synchronous reset requires more number of gates compared to asynchronous reset design. An active clock is essential for a synchronous reset design. Hence you can expect more power consumption. 6. What are the advantages of using asynchronous reset ? Implementation of asynchronous reset requires less number of gates compared to synchronous reset design. Asynchronous reset is fast. Clocking scheme is not necessary for an asynchronous design. Hence design consumes less power. Asynchronous design style is also one of the latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities. 7. What are the disadvantages of using asynchronous reset ? Metastability problems are main concerns of asynchronous reset scheme (design). Static timing analysis and DFT becomes difficult due to asynchronous reset. 8. What are the 3 fundamental operating conditions that determine the delay characteristics of gate? How operating conditions affect gate delay? Process Voltage Temperature 9. Is verilog/VHDL is a concurrent or sequential language? Verilog and VHDL both are concurrent languages. Any hardware descriptive language is concurrent in nature. 10. In a system with insufficient hold time, will slowing down the clock frequency help? No. Making data path slower can help hold time but it may result in setup violation. 11. In a system with insufficient setup time, will slowing down the clock frequency help? Yes. Making data path faster can also help setup time but it may result in hold violation. Physical Design Objective Type of Questions and Answers 1) Chip utilization depends on ___.

a. Only on standard cells b. Standard cells and macros c. Only on macros d. Standard cells macros and IO pads 2) In Soft blockages ____ cells are placed. a. Only sequential cells b. No cells c. Only Buffers and Inverters d. Any cells 3) Why we have to remove scan chains before placement? a. Because scan chains are group of flip flop b. It does not have timing critical path c. It is series of flip flop connected in FIFO d. None 4) Delay between shortest path and longest path in the clock is called ____. a. Useful skew b. Local skew c. Global skew d. Slack 5) Cross talk can be avoided by ___. a. Decreasing the spacing between the metal layers b. Shielding the nets c. Using lower metal layers d. Using long nets 6) Prerouting means routing of _____. a. Clock nets b. Signal nets c. IO nets d. PG nets 7) Which of the following metal layer has Maximum resistance? a. Metal1 b. Metal2 c. Metal3 d. Metal4 8) What is the goal of CTS? a. Minimum IR Drop b. Minimum EM c. Minimum Skew d. Minimum Slack 9) Usually Hold is fixed ___. a. Before Placement b. After Placement c. Before CTS d. After CTS 10) To achieve better timing ____ cells are placed in the critical path. a. HVT b. LVT c. RVT d. SVT 11) Leakage power is inversely proportional to ___. a. Frequency b. Load Capacitance c. Supply voltage d. Threshold Voltage 12) Filler cells are added ___. a. Before Placement of std cells b. After Placement of Std Cells c. Before Floor planning d. Before Detail Routing 13) Search and Repair is used for ___. a. Reducing IR Drop b. Reducing DRC c. Reducing EM violations d. None 14) Maximum current density of a metal is available in ___. a. .lib b. .v c. .tf d. .sdc 15) More IR drop is due to ___. a. Increase in metal width b. Increase in metal length c. Decrease in metal length d. Lot of metal layers 16) The minimum height and width a cell can occupy in the design is called as ___. a. Unit Tile cell b. Multi heighten cell c. LVT cell d. HVT cell 17) CRPR stands for ___. a. Cell Convergence Pessimism Removal b. Cell Convergence Preset Removal c. Clock Convergence Pessimism Removal d. Clock Convergence Preset Removal 18) In OCV timing check, for setup time, ___. a. Max delay is used for launch path and Min delay for capture path b. Min delay is used for launch path and Max delay for capture path c. Both Max delay is used for launch and Capture path d. Both Min delay is used for both Capture and Launch paths 19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.

a. Utilization b. Aspect Ratio c. OCV d. Antenna Ratio 20) The Solution for Antenna effect is ___. a. Diode insertion b. Shielding c. Buffer insertion d. Double spacing 21) To avoid cross talk, the shielded net is usually connected to ___. a. VDD b. VSS c. Both VDD and VSS d. Clock 22) If the data is faster than the clock in Reg to Reg path ___ violation may come. a. Setup b. Hold c. Both d. None 23) Hold violations are preferred to fix ___. a. Before placement b. After placement c. Before CTS d. After CTS 24) Which of the following is not present in SDC ___? a. Max tran b. Max cap c. Max fanout d. Max current density 25) Timing sanity check means (with respect to PD)___. a. Checking timing of routed design with out net delays b. Checking Timing of placed design with net delays c. Checking Timing of unplaced design without net delays d. Checking Timing of routed design with net delays 26) Which of the following is having highest priority at final stage (post routed) of the design ___? a. Setup violation b. Hold violation c. Skew d. None 27) Which of the following is best suited for CTS? a. CLKBUF b. BUF c. INV d. CLKINV 28) Max voltage drop will be there at(with out macros) ___. a. Left and Right sides b. Bottom and Top sides c. Middle d. None 29) Which of the following is preferred while placing macros ___? a. Macros placed center of the die b. Macros placed left and right side of die c. Macros placed bottom and top sides of die d. Macros placed based on connectivity of the I/O 30) Routing congestion can be avoided by ___. a. placing cells closer b. Placing cells at corners c. Distributing cells d. None 31) Pitch of the wire is ___. a. Min width b. Min spacing c. Min width - min spacing d. Min width + min spacing 32) In Physical Design following step is not there ___. a. Floorplaning b. Placement c. Design Synthesis d. CTS 33) In technology file if 7 metals are there then which metals you will use for power? a. Metal1 and metal2 b. Metal3 and metal4 c. Metal5 and metal6 d. Metal6 and metal7 34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ? a. Metal1 and metal2 b. Metal3 and metal4 c. Metal4 and metal5 d. Metal6 and metal7 35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombodelay is 5ns and Tsetup is 0.5ns then the clock period should be ___. a. 1ns b. 3ns c. 5ns d. 6ns 36) Difference between Clock buff/inverters and normal buff/inverters is __. a. Clock buff/inverters are faster than normal buff/inverters b. Clock buff/inverters are slower than normal buff/inverters c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to

normal buff/inverters d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters. 37) Which configuration is more preferred during floorplaning ? a. Double back with flipped rows b. Double back with non flipped rows c. With channel spacing between rows and no double back d. With channel spacing between rows and double back 38) What is the effect of high drive strength buffer when added in long net? a. Delay on the net increases b. Capacitance on the net increases c. Delay on the net decreases d. Resistance on the net increases. 39) Delay of a cell depends on which factors ? a. Output transition and input load b. Input transition and Output load c. Input transition and Output transition d. Input load and Output Load. 40) After the final routing the violations in the design ___. a. There can be no setup, no hold violations b. There can be only setup violation but no hold c. There can be only hold violation not Setup violation d. There can be both violations. 41) Utilisation of the chip after placement optimisation will be ___. a. Constant b. Decrease c. Increase d. None of the above 42) What is routing congestion in the design? a. Ratio of required routing tracks to available routing tracks b. Ratio of available routing tracks to required routing tracks c. Depends on the routing layers available d. None of the above 43) What are preroutes in your design? a. Power routing b. Signal routing c. Power and Signal routing d. None of the above. 44) Clock tree doesn't contain following cell ___. a. Clock buffer b. Clock Inverter c. AOI cell d. None of the above Answers: 1)b 2)c 3)b 4)c 5)b 6)d 7)a 8)c 9)d 10)b 11)d 12)d 13)b 14)c 15)b 16)a 17)c 18)a 19)d 20)a 21)b 22)b 23)d 24)d 25)c 26)b 27)a 28)c 29)d 30)c 31)d 32)c 33)d 34)c 35)d 36)c 37)a 38)c 39)b 40)d 41)c 42)a 43)a 44)c CMOS Design Interview Questions Below are the important VLSI CMOS interview questions. This set of interview questions may be updated in future. Answers will be posted one by one as and when i prepare them ! Readers are encouraged to post answers in comment section. Here we go......... Draw Vds-Ids curve for an MOSFET. How it varies with a) increasing Vgs b)velocity saturation c)Channel length modulation d)W/L ratio. What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs? What is latch-up in CMOS design and what are the ways to prevent it? What is Noise Margin? Explain with the help of Inverter. What happens to delay if you increase load capacitance? Give the various techniques you know to minimize power consumption for CMOS logic? What happens when the PMOS and NMOS are interchanged with one another in an inverter? What is body effect? Why is NAND gate preferred over NOR gate for fabrication? What is Noise Margin? Explain the procedure to determine Noise Margin Explain sizing of the inverter? How do you size NMOS and PMOS transistors to increase the threshold voltage? What happens to delay if we include a resistance at the output of a CMOS circuit? What are the limitations in increasing the power supply to reduce delay? How does Resistance of the metal lines vary with increasing thickness and increasing length? What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?

 Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? Give the expression for CMOS switching power dissipation? Why is the substrate in NMOS connected to ground and in PMOS to VDD? What is the fundamental difference between a MOSFET and BJT ? Which transistor has higher gain- BJT or MOS and why? Why PMOS and NMOS are sized equally in a Transmission Gates? What is metastability? When/why it will occur? What are the different ways to avoid this? Explain zener breakdown and avalanche breakdown? * What happens if Vds is increased over saturation? In the I-V characteristics curve, why is the saturation curve flat or constant? What happens if a resistor is added in series with the drain in a CMOS transistor? What are the different regions of operation in a CMOS transistor? What are the effects of the output characteristics for a change in the beta ( ) value? What is the effect of body bias? What is hot electron effect and how can it be eliminated? What is channel length modulation? What is the effect of temperature on threshold voltage? What is the effect of temperature on mobility? What is the effect of gate voltage on mobility? What are the different types of scaling? What is stage ratio? What is charge sharing on a bus? What is electron migration and how can it be eliminated? Can both PMOS and NMOS transistors pass good 1 and good 0? Explain. Why is only NMOS used in pass transistor logic? What are the different methodologies used to reduce the charge sharing in dynamic logic? What are setup and hold time violations? How can they be eliminated? Explain the operation of basic SRAM and DRAM. Which ones take more time in SRAM: Read operation or Write operation? Why? What is meant by clock race? What is meant by single phase and double phase clocking? If given a choice between NAND and NOR gates, which one would you pick? Explain. Explain the origin of the various capacitances in the CMOS transistor and the physical reasoning behind it. Why should the number of CMOS transistors that are connected in series be reduced? What is charge sharing between bus and memory element? What is crosstalk and how can it be avoided? Realize an XOR gate using NAND gate. What are the advantages and disadvantages of Bi-CMOS process? Draw an XOR gate with using minimum number of transistors and explain the operation. What are the critical parameters in a latch and flip-flop? What is the significance of sense amplifier in an SRAM? Explain Domino logic. What are the advantages of depletion mode devices over the enhancement mode devices? How can the rise and fall times in an inverter be equated? What is meant by leakage current? Realize an OR gate using NAND gate. Realize an NAND gate using a 2:1 multiplexer. Realize an NOR gate using a 2:1 multiplexer. Draw the layout of a simple inverter. What are the substrates of PMOS and NMOS transistors connected to and explain the results if the connections are interchanged with the other. What are repeaters? What is tunneling problem? What is meant by negative biased instability and how can it be avoided? What is Elmore delay algorithm? What is meant by metastability? What is the effect of Vdd on delay?

What is the effect of delay, rise and fall times with increase in load capacitance? What is the value of mobility of electrons? What is value of mobility of holes? Give insights of an inverter. Draw Layout. Explain the working.

* Give insights of a 2 input NOR gate. Draw Layout. Explain the working. Give insights of a 2 input NAND gate. Draw layout. Explain the working? Implement F= not (AB+CD) using CMOS gates. What is a pass gate. Explain the working? Why do we need both PMOS and NMOS transistors to implement a pass gate? What does the above code synthesize to? Draw cross section of a PMOS transistor. Draw cross section of an NMOS transistor. What is a D-latch? Implement D flip-flop with a couple of latches? Implement a 2 input AND gate using transmission gate? Explain various adders and difference between them? How can you construct both PMOS and NMOS on a single substrate? What happens when the gate oxide is very thin? What is SPICE? What are the differences between IRSIM and SPICE? What are the differences between netlist of HSPICE and Spectre? Implement F = AB+C using CMOS gates? What is hot electron effect? Define threshold voltage? List out the factors affecting power consumption on a chip? What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths? What is clock feed through? Implement an Inverter using a single transistor? What is Fowler-Nordheim Tunneling? Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why? Draw the Differential Sense Amplifier and explain its working. How to size this circuit? What happens if we use an Inverter instead of the Differential Sense Amplifier? Draw the SRAM Write Circuitry How did you arrive at sizes of transistor in SRAM? How does the size of PMOS pull up transistors for bit and bitbar lines affect SRAMs performance? What is the critical path in a SRAM? Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal? Give a big picture of the entire SRAM layout showing placements of SRAM cells, row decoders, column decoders, read circuit, write circuit and buffers. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

Design For Test-DFT In scan chains if some flip flops are +ve edge triggered and remaining flip flops are -ve edge triggered how it behaves? Answer: For designs with both positive and negative clocked flops, the scan insertion tool will always route the scan chain so that the negative clocked flops come before the positive edge flops in the chain. This avoids the need of lockup latch. For the same clock domain the negedge flops will always capture the data just captured into the posedge flops on the posedge of the clock. For the multiple clock domains, it all depends upon how the clock trees are balanced. If the clock domains are completely asynchronous, ATPG has to mask the receiving flops. What you mean by scan chain reordering? Answer1: Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsis

and can reorder to optimize it.... it maintains the number of flops in a chain. Answer2: During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion. This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock domains. Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be redone by reading the new net list. what are the differences between SIMULATION and SYNTHESIS Simulation synthesis <= <= Check verify for your your design. timing

Simulation is used to verify the functionality of the circuit.. a)Functional Simulation:study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met. Synthesis:One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components Can u tell me the differences between latches & flipflops? There 1. 2. Sequential Latches and flipflops both come under the category of "sequential circuits", whose output depends not only on the current inputs, but also on previous inputs and outputs. Difference: Latches are level-sensitive, whereas, FF are edge sensitive. By edge sensitive, I mean O/p changes only when there is a clock transition.( from 1 to 0, or from 0 to 1) Example: In a flipflop, inputs have arrived on the input lines at time= 2 seconds. But, output won't change immediately. Flip-flops 1.Positive 2. negative edge triggered 1)fllipflops 2) latch so does not take twice automatically have a clock the delay signal, nymber is whereas of more a flip-flop gates for always as latches flipflops does. At time = 3 seconds, are clock transition of edge takes place. After 2 that, O/P will change. types: triggered are 2 types of circuits: Combinational

3)power consumption is also more What is slack? The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path. Slack may be +ve or -ve. Equivalence between VHDL and C? There is concept of understanding in C there is structure.Based upon requirement structure provide facility to store collection of different data types. In VHDL we have direct access to memory so instead of using pointer in C (and member of structure) we can write interface store data in memory and access it. RTL and Behavioral Register transfer language means there should be data flow between two registers and logic is in between them for end registers data should flow.

Behavioral means how hardware behave determine the exact way it works we write using HDL syntax.For complex projects it is better mixed approach or more behavioral is used. VHDL QUESTIONS 1. 2. 3. 4. 5. 6. 7. 8. 9. 1. 2. 3. 4. 5. 6. What is the difference between using direct instantiations and component ones except that you need to What is the use of BLOCKS? What is the use of PROCEDURES? What is the usage of using more then one architecture in an entity? What is a D-latch? Write the VHDL Code for it? Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop? Differences between Signals and Variables in VHDL? If the same code is written Differences between functions and Procedures in VHDL? Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same? Give two ways of converting a two input NAND gate to an inverter Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can What are set up time & hold time constraints? What do they signify? Which one is critical for estimating Give a circuit to divide frequency of clock cycle by two Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the using Signals and declare the component?

Variables what does it synthesize to?

Digital Design interview questions:

expect any sequential ckt) maximum clock frequency of a circuit?

delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors) 7. 8. 9. The answer to the above question is breaking the combinational circuit and pipelining it. What will be What are the different Adder circuits you studied? Give the truth table for a Half Adder. Give a gate level implementation of the same. affected if you do this?

10. Draw a Transmission Gate-based D-Latch. 11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) 12. How do you detect if two 8-bit signals are same? 13. How do you detect a sequence of "1101" arriving serially from a signal line? 14. Design any FSM in VHDL or Verilog. Intel interview questions The following questions are used for screening the candidates during the first interview. The questions apply mostly to fresh college grads pursuing an engineering career at Intel. 1. latency 3. of Have an instruction many you in a bit 5 stage studied machine? What buses? is the What throughput there in of this a types? machine ? 2. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the How combinations are byte?

4. For a single computer processor computer system, what is the purpose of a processor cache and describe its

operation? 5. Explain the operation considering a two processor computer system with a cache for each processor. 6. What are the main issues associated with multiprocessor caches and how might you solve them? 7. 8. 9. heads. 11. In what cases do you need to double clock a signal before presenting it to a synchronous state machine? 12. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem? 13. What are the total number of lines written by you in C/C++? What is the most complicated/valuable program written 14. 15. 16. 17. were What What Are types of is you CMOS What the difference familiar memories have in compiler between with you designed? = VHDL What were was and == and/or their size? in C/C++? used? C? Verilog? Speed? used? Explain Are Are the difference you you between familiar familiar write with with through the and the write term term back cache. MESI? snooping?

10. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in

18. What work have you done on full chip Clock and Power distribution? What process technology and budgets 19. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements? 20. Process technology? What package was used and how did you model the package/system? What parasitic effects 21. 23. 24. What What What types products was your of have role in high you the were speed designed silicon CMOS which have circuits entered ramp? have high What you volume tools did considered? designed? production? you use?

22. What transistor level design tools are you proficient with? What types of designs were they used on? evaluation/product

25. If not into production, how far did you follow the design and why did not you see it into production? VLSI Design Interview questions 1. 2. 3. 4. 5. 6. 7. 8. 9. Explain why & how a MOSFET works Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with Explain the various MOSFET Capacitances & their significance Draw a CMOS Inverter. Explain its transfer characteristics Explain sizing of the inverter How do you size NMOS and PMOS transistors to increase the threshold voltage? What is Noise Margin? Explain the procedure to determine Noise Margin Give the expression for CMOS switching power dissipation What is Body Effect?

increasing transistor width (c) considering Channel Length Modulation

10. Describe the various effects of scaling 11. Give the expression for calculating Delay in CMOS circuit 12. What happens to delay if you increase load capacitance? 13. What happens to delay if we include a resistance at the output of a CMOS circuit?

14. What are the limitations in increasing the power supply to reduce delay? 15. How does Resistance of the metal lines vary with increasing thickness and increasing length? 16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other 17. What happens if we increase the number of contacts or via from one metal layer to the next? 18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times 19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 20. Draw the stick diagram of a NOR gate. Optimize it 21. For CMOS logic, give the various techniques you know to minimize power consumption 22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus 23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? 24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width? 25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) 26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram 27. Why don't we use just one NMOS or PMOS transistor as a transmission gate? 28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD 29. Draw a 6-T SRAM Cell and explain the Read and Write operations 30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation) 31. What happens if we use an Inverter instead of the Differential Sense Amplifier? 32. Draw the SRAM Write Circuitry 33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes? 34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance? 35. What's the critical path in a SRAM? 36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal? 37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers 38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? 39. How can you model a SRAM at RTL Level? 40. Whats the difference between Testing & Verification? 41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) 42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? Verilog Interview Questions What is the difference between $display and $monitor and $write and $strobe? What is the difference between code-compiled simulator and normal simulator? What is the difference between wire and reg?

What is the difference between blocking and non-blocking assignments? What is the significance Timescale directivbe? What is the difference between bit wise, unary and logical operators? What is the difference between task and function? What is the difference between casex, casez and case statements? Which one preferred-casex or casez? For what is defparam used? What is the difference between = = and = = = ? What is a compiler directive like include and ifdef? Write a verilog code to swap contents of two registers with and without a temporary register? What is the difference between inter statement and intra statement delay? What is delta simulation time? What is difference between Verilog full case and parallel case? What you mean by inferring latches? How to avoid latches in your design? Why latches are not preferred in synthesized design? How blocking and non blocking statements get executed? Which will be updated first: is it variable or signal? What is sensitivity list? If you miss sensitivity list what happens? In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why? In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why? What is general structure of Verilog code you follow? What are the difference between Verilog and VHDL? What are system tasks? List some of system tasks and what are their purposes? What are the enhancements in Verilog 2001? Write a Verilog code for synchronous and asynchronous reset? What is pli? why is it used? What is file I/O? What is difference between freeze deposit and force? Will case always infer priority register? If yes how? Give an example. What are inertial and transport delays ? What does `timescale 1 ns/ 1 ps signify in a verilog code? How to generate sine wav using verilog coding style? How do you implement the bi-directional ports in Verilog HDL? How to write FSM is verilog? What is verilog case (1)? What are Different types of Verilog simulators available? What is Constrained-Random Verification ? How can you model a SRAM at RTL Level?

Physical Design Questions and Answers I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to provide detailed answer to all questions in my available spare time. Hence i decided to give "short and sweet" one line answers to the questions so that readers can immediately benefited. Detailed answers will be posted in later stage.I have given answers to some of the physical design questions here. Enjoy ! What parameters (or aspects) differentiate Chip Design and Block level design? Chip design has I/O pads; block design has pins. Chip design uses all metal layes available; block design may not use all metal layers. Chip is generally rectangular in shape; blocks can be rectangular, rectilinear. Chip design requires several packaging; block design ends in a macro.

How do you place macros in a full chip design? First check flylines i.e. check net connections from macro to macro and macro to standard cells. If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries. If input pin is connected to macro better to place nearer to that pin or pad. If macro has more connection to standard cells spread the macros inside core. Avoid criscross placement of macros. Use soft or hard blockages to guide placement engine. Differentiate between a Hierarchical Design and flat design? Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells. Hierarchical design takes more run time; Flattened design takes less run time. Which is more complicated when u have a 48 MHz and 500 MHz clock design? 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design. Name few tools which you used for physical verification? Herculis from Synopsys, Caliber from Mentor Graphics. What are the input files will you give for primetime correlation? Netlist, Technology library, Constraints, SPEF or SDF file. If the routing congestion exists between two macros, then what will you do? Provide soft or hard blockage How will you decide the die size? By checking the total area of the design you can decide die size. If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem? Poly If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM? Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage. In your project what is die size, number of metal layers, technology, foundry, number of clocks? Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !! Metal layers: See your tech file. generally for 90nm it is 7 to 9. Technology: Again look into tech files. Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc Clocks: Look into your design and SDC file ! How many macros in your design? You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!! What is each macro size and number of standard cell count? Depends on your design. What are the input needs for your design? For synthesis: RTL, Technology library, Standard cell library, Constraints

 For Physical design: Netlist, Technology library, Constraints, Standard cell library What is SDC constraint file contains? Clock definitions Timing exception-multicycle path, false path Input and Output delays How did you do power planning? How to calculate core ring width, macro ring width and strap or trunk width? How to find number of power pad and IO power pads? How the width of metal and number of straps calculated for power and ground? Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later. How to find total chip power? Total chip power=standard cell power consumption,Macro power consumption pad power consumption. What are the problems faced related to timing? Prelayout: Setup, Max transition, max capacitance Post layout: Hold How did you resolve the setup and hold problem? Setup: upsize the cells Hold: insert buffers In which layer do you prefer for clock routing and why? Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay. If in your design has reset pin, then itll affect input pin or output pin or both? Output pin. During power analysis, if you are facing IR drop problem, then how did you avoid? Increase power metal layer width. Go for higher metal layer. Spread macros or standard cells. Provide more straps. Define antenna problem and how did you resolve these problem? Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem. Decrease the length of the net by providing more vias and layer jumping. Insert antenna diode. How delays vary with different PVT conditions? Show the graph. P increase->dealy increase P decrease->delay decrease V increase->delay decrease V decrease->delay increase

 T increase->delay increase T decrease->delay decrease Explain the flow of physical design and inputs and outputs for each step in flow. Physical Design Flow

The physical design flow is generally explained in the Figure (1.). In each section of the flow EDA tools available from the two main EDA companies-Synopsys and Cadence is also listed. In each and every step of the flow timing and power analysis can be carried out. If timing and power requirements are not met then either the whole flow has to be re-exercised or going back one or two steps and optimizing the design or incremental optimization may meet the requirements What is cell delay and net delay? Gate delay Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma] Gate delay =function of(i/p transition time, Cnet+Cpin). Cell delay is also same as Gate delay. Cell delay For any gate it is measured between 50% of input transition to the corresponding 50% of output transition. Intrinsic delay Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell. It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor. This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors. Net Delay (or wire delay) The difference between the time a signal is first applied to the net and the time it reaches other devices

connected to that net. It is due to the finite resistance and capacitance of the net.It is also known as wire delay. Wire delay =fn(Rnet , Cnet+Cpin) What are delay models and what is the difference between them? Linear Delay Model (LDM) Non Linear Delay Model (NLDM) What is wire load model? Wire load model is NLDM which has estimated R and C of the net. Why higher metal layers are preferred for Vdd and Vss? Because it has less resistance and hence leads to less IR drop. What is logic optimization and give some methods of logic optimization. Upsizing Downsizing Buffer insertion Buffer relocation Dummy buffer placement What is the significance of negative slack? negative slack==> there is setup voilation==> deisgn can fail What is signal integrity? How it affects Timing? IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues. If Idrop is more==>delay increases. crosstalk==>there can be setup as well as hold voilation. What is IR drop? How to avoid? How it affects timing? There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop. If IR drop is more==>delay increases. What is EM and it effects? Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration. Affects: Either short or open of the signal line or power line. What are types of routing? Global Routing Track Assignment Detail Routing What is latency? Give the types? Source Latency It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design". Delay from clock source to beginning of clock tree (i.e. clock definition point). The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point

in the design. Network latency It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register". The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin. What is track assignment? Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets. What is congestion? If the number of routing tracks available for routing is less than the required tracks then it is known as congestion. Whether congestion is related to placement or routing? Routing What are clock trees? Distribution of clock from the clock source to the sync pin of the registers. What are clock tree types? H tree, Balanced tree, X tree, Clustering tree, Fish bone What is cloning and buffering? Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell. Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.

ASIC Different Types of Delays in ASIC or VLSI design Source Delay/Latency Network Delay/Latency Insertion Delay Transition Delay/Slew: Rise time, fall time Path Delay Net delay, wire delay, interconnect delay Propagation Delay Phase Delay Cell Delay Intrinsic Delay Extrinsic Delay Input Delay Output Delay Exit Delay Latency (Pre/post CTS)

 Uncertainty (Pre/Post CTS) Unateness: Positive unateness, negative unateness Jitter: PLL jitter, clock jitter Gate delay Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma] Gate delay =function of(i/p transition time, Cnet+Cpin). Cell delay is also same as Gate delay. Source Delay (or Source Latency) It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design". Delay from clock source to beginning of clock tree (i.e. clock definition point). The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design. Network Delay(latency) It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register". The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin. Insertion delay The delay from the clock definition point to the clock pin of the register. Transition delay It is also known as "Slew". It is defined as the time taken to change the state of the signal. Time taken for the transition from logic 0 to logic 1 and vice versa . or Time taken by the input signal to rise from 10%(20%) to the 90%(80%) and vice versa. Transition is the time it takes for the pin to change state. Slew Rate of change of logic.See Transition delay. Slew rate is the speed of transition measured in volt / ns. Rise Time Rise time is the difference between the time when the signal crosses a low threshold to the time when the signal crosses the high threshold. It can be absolute or percent. Low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level. Fall Time Fall time is the difference between the time when the signal crosses a high threshold to the time when the signal crosses the low threshold. The low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level. For an ideal square wave with 50% duty cycle, the rise time will be 0.For a symmetric triangular wave, this is reduced to just 50%.

 The rise/fall definition is set on the meter to 10% and 90% based on the linear power in Watts. These points translate into the -10 dB and -0.5 dB points in log mode (10 log 0.1) and (10 log 0.9). The rise/fall time values of 10% and 90% are calculated based on an algorithm, which looks at the mean power above and below the 50% points of the rise/fall times Path delay Path delay is also known as pin to pin delay. It is the delay from the input pin of the cell to the output pin of the cell. Net Delay (or wire delay) The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. It is due to the finite resistance and capacitance of the net.It is also known as wire delay. Wire delay =fn(Rnet , Cnet+Cpin) Propagation delay For any gate it is measured between 50% of input transition to the corresponding 50% of output transition. This is the time required for a signal to propagate through a gate or net. For gates it is the time it takes for a event at the gate input to affect the gate output. For net it is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net. It is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2. Phase delay Same as insertion delay Cell delay For any gate it is measured between 50% of input transition to the corresponding 50% of output transition. Intrinsic delay Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell. It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor. This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors. Extrinsic delay Same as wire delay, net delay, interconnect delay, flight time. Extrinsic delay is the delay effect that associated to with interconnect. output pin of the cell to the input pin of the next cell. Input delay Input delay is the time at which the data arrives at the input pin of the block from external circuit with respect to reference clock. Output delay Output delay is time required by the external circuit before which the data has to arrive at the output pin of the block with respect to reference clock. Exit delay It is defined as the delay in the longest path (critical path) between clock pad input and an output. It determines the maximum operating frequency of the design. Latency (pre/post cts)

 Latency is the summation of the Source latency and the Network latency. Pre CTS estimated latency will be considered during the synthesis and after CTS propagated latency is considered. Uncertainty (pre/post cts) Uncertainty is the amount of skew and the variation in the arrival clock edge. Pre CTS uncertainty is clock skew and clock Jitter. After CTS we can have some margin of skew + Jitter. Unateness A function is said to be unate if the rise transition on the positive unate input variable causes the ouput to rise or no change and vice versa. Negative unateness means cell output logic is inverted version of input logic. eg. In inverter having input A and output Y, Y is -ve unate w.r.to A. Positive unate means cell output logic is same as that of input. These +ve ad -ve unateness are constraints defined in library file and are defined for output pin w.r.to some input pin. A clock signal is positive unate if a rising edge at the clock source can only cause a rising edge at the register clock pin, and a falling edge at the clock source can only cause a falling edge at the register clock pin. A clock signal is negative unateif a rising edge at the clock source can only cause a falling edge at the register clock pin, and a falling edge at the clock source can only cause a rising edge at the register clock pin. In other words, the clock signal is inverted. A clock signal is not unate if the clock sense is ambiguous as a result of non-unate timing arcs in the clock path. For example, a clock that passes through an XOR gate is not unate because there are nonunate arcs in the gate. The clock sense could be either positive or negative, depending on the state of the other input to the XOR gate. Jitter The short-term variations of a signal with respect to its ideal position in time. Jitter is the variation of the clock period from edge to edge. It can varry +/- jitter value. From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. This can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform. Sources of Jitter Common sources of jitter include: Internal circuitry of the phase-locked loop (PLL) Random thermal noise from a crystal Other resonating devices Random mechanical noise from crystal vibration Signal transmitters Traces and cables Connectors Receivers Skew The difference in the arrival of clock signal at the clock pin of different flops. Two types of skews are defined: Local skew and Global skew. Local skew The difference in the arrival of clock signal at the clock pin of related flops. Global skew The difference in the arrival of clock signal at the clock pin of non related flops. Skew can be positive or negative.

 When data and clock are routed in same direction then it is Positive skew. When data and clock are routed in opposite then it is negative skew. Recovery Time Recovery specifies the minimum time that an asynchronous control input pin must be held stable after being de-asserted and before the next clock (active-edge) transition. Recovery time specifies the time the inactive edge of the asynchronous signal has to arrive before the closing edge of the clock. Recovery time is the minimum length of time an asynchronous control signal (eg.preset) must be stable before the next active clock edge. The recovery slack time calculation is similar to the clock setup slack time calculation, but it applies asynchronous control signals. Equation 1: Recovery Slack Time = Data Required Time Data Arrival Time Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tclkq+ Register to Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register =Tsetup If the asynchronous control is not registered, equations shown in Equation 2 is used to calculate the recovery slack time. Equation 2: Recovery Slack Time = Data Required Time Data Arrival Time Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register Delay+Tsetup If the asynchronous reset signal is from a port (device I/O), you must make an Input Maximum Delay assignment to the asynchronous reset pin to perform recovery analysis on that path. Removal Time Removal specifies the minimum time that an asynchronous control input pin must be held stable before being de-asserted and after the previous clock (active-edge) transition. Removal time specifies the length of time the active phase of the asynchronous signal has to be held after the closing edge of clock. Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. Calculation is similar to the clock hold slack calculation, but it applies asynchronous control signals. If the asynchronous control is registered, equations shown in Equation 3 is used to calculate the removal slack time. If the recovery or removal minimum time requirement is violated, the output of the sequential cell becomes uncertain. The uncertainty can be caused by the value set by the resetbar signal or the value clocked into the sequential cell from the data input. Equation 3 Removal Slack Time = Data Arrival Time Data Required Time Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tclkq of Source Register + Register to Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register + Thold If the asynchronous control is not registered, equations shown in Equation 4 is used to calculate the removal slack time. Equation 4 Removal Slack Time = Data Arrival Time Data Required Time Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register +Thold

 If the asynchronous reset signal is from a device pin, you must specify the Input Minimum Delay constraint to the asynchronous reset pin to perform a removal analysis on this path. What is the difference between soft macro and hard macro? What is the difference between hard macro, firm macro and soft macro? or What are IPs? Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design flow, not in FPGA flow. Before bying any IP it is very important to evaluate its advantages and disadvantages over each other, hardware compatibility such as I/O standards with your design blocks, reusability for other designs. Soft macros Soft macros are in synthesizable RTL. Soft macros are more flexible than firm or hard macros. Soft macros are not specific to any manufacturing process. Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area, or power. Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data. From the physical design perspective, soft macro is any cell that has been placed and routed in a placement and routing tool such as Astro. (This is the definition given in Astro Rail user manual !) Soft macros are editable and can contain standard cells, hard macros, or other soft macros. Firm macros Firm macros are in netlist format. Firm macros are optimized for performance/area/power using a specific fabrication technology. Firm macros are more flexible and portable than hard macros. Firm macros are predictive of performance and area than soft macros. Hard macro Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPs !). Hard macos are targeted for specific IC manufacturing technology. Hard macros are block level designs which are silicon tested and proved. Hard macros have been optimized for power or area or timing. In physical design you can only access pins of hard macros unlike soft macros which allows us to manipulate in different way. You have freedom to move, rotate, flip but you can't touch anything inside hard macros. Very common example of hard macro is memory. It can be any design which carries dedicated single functionality (in general).. for example it can be a MP4 decoder. Be aware of features and characteristics of hard macro before you use it in your design... other than power, timing and area you also should know pin properties like sync pin, I/O standards etc LEF, GDS2 file format allows easy usage of macros in different tools. From the physical design (backend) perspective: Hard macro is a block that is generated in a methodology other than place and route (i.e. using full custom design methodology) and is brought into the physical design database (eg. Milkyway in Synopsys; Volcano

in Magma) as a GDS2 file. What is the difference between FPGA and CPLD? FPGA-Field Programmable Gate Array and CPLD-Complex Programmable Logic Device-- both are programmable logic devices made by the same companies with different characteristics. "A Complex Programmable Logic Device (CPLD) is a Programmable Logic Device with complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations". Architecture Granularity is the biggest difference between CPLD and FPGA. FPGA are "fine-grain" devices. That means that they contain hundreds of (up to 100000) of tiny blocks (called as LUT or CLBs etc) of logic with flip-flops, combinational logic and memories.FPGAs offer much higher complexity, up to 150,000 flip-flops and large number of gates available. CPLDs typically have the equivalent of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million. CPLD are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops and combinational logic. CPLDs based on AND-OR structure. CPLD's have a register with associated logic (AND/OR matrix). CPLD's are mostly implemented in control applications and FPGA's in datapath applications. Because of this course grained architecture, the timing is very fixed in CPLDs. FPGA are RAM based. They need to be "downloaded" (configured) at each power-up. CPLD are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once. FPGA needs boot ROM but CPLD does not. In some systems you might not have enough time to boot up FPGA then you need CPLD+FPGA. Generally, the CPLD devices are not volatile, because they contain flash or erasable ROM memory in all the cases. The FPGA are volatile in many cases and hence they need a configuration memory for working. There are some FPGAs now which are nonvolatile. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory. The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-to-output timings than FPGA. Features FPGA have special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this. FPGA can contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500> Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment). Security: In CPLD once programmed, the design can be locked and thus made secure. Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue. Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated equipment. FPGA idle power consumption is reasonably low, although it is sharply increasing in the newest families. Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even on-chip microprocessors and Multi-Gigabit Transceivers.These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage. Use FPGAs for larger and more complex designs.

 FPGA is suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will find out that each timing report is different. But it is different in CPLD synthesis, you can get the same result. As CPLDs and FPGAs become more advanced the differences between the two device types will continue to blur. While this trend may appear to make the two types more difficult to keep apart, the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macro cells with predictable timing characteristics will likely be sufficient to maintain a product differentiation for the foreseeable future. What is the difference between FPGA and ASIC? This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer. FPGA vs. ASIC Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs. FPGA Field Programable Gate Arrays FPGA Design Advantages Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !! No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!! Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis. More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device. Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features. Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically. FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC. Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design. Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ?

 FPGA sythesis is much more easier than ASIC. In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it. FPGA Design Disadvantages Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race ! You have to use the resources available in the FPGA. Thus FPGA limits the design size. Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation. ASIC Application Specific Intergrated Circiut ASIC Design Advantages Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA. Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations. Low power....Low power....Low power: ASIC can be optimized for required low power. There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !! In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA. In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) . ASIC Design Diadvantages Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC. Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!) Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE. Structured ASICS Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer. Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity. Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O. FPGA vs. ASIC Design Flow Comparison

ASIC Design Check List Silicon Process and Library Characteristics What exact process are you using? How many layers can be used for this design? Are the Cross talk Noise constraints, Xtalk Analysis configuration, Cell EM & Wire EM available? Design Characteristics What is the design application? Number of cells (placeable objects)? Is the design Verilog or VHDL? Is the netlist flat or hierarchical? Is there RTL available? Is there any datapath logic using special datapath tools? Is the DFT to be considered? Can scan chains be reordered? Is memory BIST, boundary scan used on this design? Are static timing analysis constraints available in SDC format?

Clock Characteristics How many clock domains are in the design? What are the clock frequencies? Is there a target clock skew, latency or other clock requirements? Does the design have a PLL? If so, is it used to remove clock latency? Is there any I/O cell in the feedback path? Is the PLL used for frequency multipliers? Are there derived clocks or complex clock generation circuitry? Are there any gated clocks? If yes, do they use simple gating elements? Is the gate clock used for timing or power? For gated clocks, can the gating elements be sized for timing? Are you muxing in a test clock or using a JTAG clock? Available cells for clock tree?

Are there any special clock repeaters in the library? Are there any EM, slew or capacitance limits on these repeaters? How many drive strengths are available in the standard buffers and inverters? Do any of the buffers have balanced rise and fall delays? Any there special requirements for clock distribution? Will the clock tree be shielded? If so, what are the shielding requirements?

Floorplan and Package Characteristics Target die area? Does the area estimate include power/signal routing? What gates/mm2 has been assumed? Number of routing layers? Any special power routing requirements? Number of digital I/O pins/pads? Number of analog signal pins/pads? Number of power/ground pins/pads? Total number of pins/pads and Location? Will this chip use a wire bond package? Will this chip use a flip-chip package? If Yes, is it I/O bump pitch? Rows of bumps? Bump allocation?Bump pad layout guide? Have you already done floorplanning for this design? If yes, is conformance to the existing floorplan required? What is the target die size? What is the expected utilization? Please draw the overall floorplan ? Is there an existing floorplan available in DEF? What are the number and type of macros (memory, PLL, etc.)? Are there any analog blocks in the design? What kind of packaging is used? Flipchip? Are the I/Os periphery I/O or area I/O? How many I/Os? Is the design pad limited? Power planning and Power analysis for this design? Are layout databases available for hard macros ? Timing analysis and correlatio? Physical verification ?

Data Input Library information for new library .lib for timing information GDSII or LEF for library cells including any RAMs RTL in Verilog/VHDL format Number of logical blocks in the RTL Constraints for the block in SDC Floorplan information in DEF I/O pin location Macro locations

ASIC General General ASIC questions are posted here. More questions related to different catagories of ASICs can be found at respective sections. What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs? In system with insufficient hold time, will slowing down the clock help? In system with insufficient setup time, will slowing down the clock help? Why would a testbench not have pins (port) on it? When declaring a flip flop, why would not you declare its output value in the port statement? Give 2 advantages of using a script to build a chip?

 A tri state bus is directly connected to a set of CMOS input buffers. No other wires or components are attached to the bus wires. Upon observation we can find that under certain conditions, this circuit is consuming considerable power. Why it is so? Is circuit correct? If not, how to correct? Is Verilog (or that matter any HDL) is a concurrent or sequential language? What is the function of sensitivity list? A mealy type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly? A moore type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the state machine be synthesized correctly? What type of delay is most like a infinite bandwidth transmission line? Define metastability. When does metastability occur? Give one example of a situation where metastability could occur. Give two ways metastability could manifest itself in a state machine. What is MTBF? Does MTBF give the time until the next failure occurs? Give 3 ways in which to reduce the chance of metastable failure. Give 2 advantages of using a synchronous reset methodology. Give 2 disadvantages of using a synchronous reset methodology. Give 2 advantages of using an asynchronous reset methodology. Give 2 disadvantages of using an asynchronous reset methodology. What are the two most fundamental inputs (files) to the synthesis tool? What are two important steps in synthesis? What happens in those steps? What are the two major output (files) from the synthesis process? Name the fundamental 3 operating consitions that determine (globally) the delay characteristics of CMOS gates. For each how they affect gate delay? For a single gate, with global gating conditions held constant , what 3 delay coefficients effect total gate delay? Which is the most sensitive to circuit topology? FPGA. What is the difference between FPGA and CPLD? FPGA-Field Programmable Gate Array and CPLD-Complex Programmable Logic Device-- both are programmable logic devices made by the same companies with different characteristics. "A Complex Programmable Logic Device (CPLD) is a Programmable Logic Device with complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations". This is what Wiki defines.....!! Architecture Granularity is the biggest difference between CPLD and FPGA. FPGA are "fine-grain" devices. That means that they contain hundreds of (up to 100000) of tiny blocks (called as LUT or CLBs etc) of logic with flip-flops, combinational logic and memories.FPGAs offer much higher complexity, up to 150,000 flip-flops and large number of gates available. CPLDs typically have the equivalent of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million. CPLD are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops and combinational logic. CPLDs based on AND-OR structure. CPLD's have a register with associated logic (AND/OR matrix). CPLD's are mostly implemented in control applications and FPGA's in datapath applications. Because of this course grained architecture, the timing is very

fixed in CPLDs. FPGA are RAM based. They need to be "downloaded" (configured) at each power-up. CPLD are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once. FPGA needs boot ROM but CPLD does not. In some systems you might not have enough time to boot up FPGA then you need CPLD+FPGA. Generally, the CPLD devices are not volatile, because they contain flash or erasable ROM memory in all the cases. The FPGA are volatile in many cases and hence they need a configuration memory for working. There are some FPGAs now which are nonvolatile. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory. The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-to-output timings than FPGA. Features FPGA have special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this. FPGA can contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500> Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where "instant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery-operated equipment). Security: In CPLD once programmed, the design can be locked and thus made secure. Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue. Power: The high static (idle) power consumption prohibits use of CPLD in battery-operated equipment. FPGA idle power consumption is reasonably low, although it is sharply increasing in the newest families. Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even on-chip microprocessors and Multi-Gigabit Transceivers.These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage. Use FPGAs for larger and more complex designs. FPGA is suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will find out that each timing report is different. But it is different in CPLD synthesis, you can get the same result. As CPLDs and FPGAs become more advanced the differences between the two device types will continue to blur. While this trend may appear to make the two types more difficult to keep apart, the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macro cells with predictable timing characteristics will likely be sufficient to maintain a product differentiation for the foreseeable future. What is the difference between FPGA and ASIC? This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer. FPGA vs. ASIC Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and cons but it is designers responsibility to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs. FPGA - Field Programable Gate Arrays

FPGA Design Advantages Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA ! Done !! No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap. (sometimes its free ! You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. I would say "very expensive"...Its in crores....!! Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less.The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis. More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device. Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundreds or more depending on the hardware features. Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again.Modern FPGAs are reconfigurable both partially and dynamically. FPGAs are good for prototyping and limited production.If you are going to make 100-200 boards it isn't worth to make an ASIC. Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design. Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU etc inbuilt, which can be used to get better performace. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ? FPGA sythesis is much more easier than ASIC. In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it. FPGA Design Disadvantages Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race ! You have to use the resources available in the FPGA. Thus FPGA limits the design size. Good for low quantity production. As quantity increases cost per product increases compared to the ASIC implementation. ASIC Application Specific Intergrated Circiut ASIC Design Advantages Cost....cost....cost....Lower unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA. Speed...speed...speed....ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations. Low power....Low power....Low power: ASIC can be optimized for required low power. There are several

low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call.....never.....low power ASICs helps battery live longer life !! In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA. In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no need of DFT !) . ASIC Design Diadvantages Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC. Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!) Expensive Tools: ASIC design tools are very much expensive. You spend a huge amount of NRE. Structured ASICS Structured ASICs have the bottom metal layers fixed and only the top layers can be designed by the customer. Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity. Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O. FPGA Interview Questions What is minimum and maximum frequency of DCM in spartan-3 series FPGA? List some of constraints you used and their purpose during your design? What is the size of bitmap with changing gate count? What are different types of FPGA programming modes? How to change from one to another? List out some important features of FPGA. List out some of synthesizable and non synthesizable constructs? Draw general structure of FPGA? What is the difference between FPGA and CPLD? What is DCM? Why they are used? Draw FPGA design flow. Explain each step. What is input and output from each step? What is slice, CLB, LUT? Is it possible to configure CLB as RAM? What is purpose of a constraint file? What is its extension? How you will choose an FPGA? How clock is routed through out FPGA? What are difference between PLL and DLL ? What is soft processor? What is hard processor?

Tell me a little bit about semiconductors (what is conductance and valence band? Fermi level? For n type semiconductor, what is the doping? Do you know how to say P and As in English?)

How does a pn junction works? (I know you know it, but could you tell other people clearly? Try it!!!, They ask you this question!). What is the depletion re ion? What is the build!in potential? What is the relation between these para"eters with dopin concentration and te"perature? #e"e"ber the te"po o$ the build!in potential is about ?"%&'. Tell "e how ()*+,T works. (Write it down in your own words and re"e"ber it !!!). Tell "e how -.T works. (*hould I write down and re"e"ber it? *ure! -ut it is less asked). How does %be and Ic chan e with te"perature?

 Threshold /olta e0 I$ the substrate dopin concentration increase, or te"perature increases, how will %t chan e? it increase or decrease? Tell "e what is 1hannel len th "odulation, what is ,arly e$$ects and their physical ori in. Tell "e what is short 1hannel e$$ect. +or a 2.34u" and 2.4u" technolo y ()*+,T, which has a hi her cuto$$ $requency? How does a -and ap %olta e re$erence work? What is the ideal input and output resistance o$ a current source? How about /olta e source? How to i"pro/e these para"eters? (1ascode topolo y, use lon channel transistors) Tell "e the para"eters as "any as possible you know that used to character an a"pli$ier. What are the two types o$ noise o$ ()*+,T, how to eli"inate the"?(Ther"al and +licker) 3.I$ the $ollowin in/erter biased in the "iddle o$ %dd, what is the s"all si nal ain? (5nswer "6ro)

7. 1rossection dia ra" o$ the in/erter (be able to draw the contact o$ power supply and round) 8. +ro" the crossection o$ the dia ra", be able to draw the parasitic -.T leads to latch!up. 9 . How to pre/ent latch!up (do not $or et uard rin , cla"ppin circuits!) :. ;raw the layout o$ an in/erter or <)#&<5<; ate. =. +or the $ollowin source $ollower, what is its !8d- bandwidth? How about it stability?

>. In the $ollowin $i ure, i$ the two resisters are equal, what is its !8d- bandwidth? 1o"pare its stability with that o$ a source $ollower.

4.+or the $ollowin circuit, i$ the input is a rail!to!rail square wa/e, plot the wa/e a$ter the in/erter and /o.

?.+or the $ollowin circuits, What is the ain? @sin what technolo y to i"pro/e the "atchin o$ the input transistors? I$ the bias current increase, what happens to the ain? (Hit0 ;ecrease!!!) What happens to the bandwidth? #eplace the <()* with npn -.T and A()* with pnp -.T, answer the abo/e questions.(<ow ain re"ains constant with increasin biasin current!)

32. +or the $ollowin circuits, answer the questions a ain. What are the ad/anta es and disad/anta es o$ these two a"pli$iers?

33. What are the e$$ecti/e resistance $ro" source to drain o$ the $ollowin two transistors? (The /alue o$ the resistance is #). 5nswer0 both o$ the" are 3& ".

37.What is the low $requency ain o$ the $ollowin circuits? The input is the input current Iin. Where does the do"inant pole locate? How about the pole at node 3?

38.+or the $ollowin circuit, the threshold /olta e o$ the transistor is 2.>%. %b3B3/, %b7B7/, When %in chan e $ro" :% to 2%, draw the current $low throu h the transistors %* %in. (This question was supplied by Wan Ce)

39. +or the $ollowin circuits, %ddB:/, tell "e what are %o3 and %o7 when %in is :%, 8%, 7.:% and 2%.

3:. +or the $ollowin circuit, what is the ain o$ %out&%in? Where is the +eedback and what is the $unction o$ $eedback?

3=. +or the $ollowin circuits, the s"all si nal input is i in, the s"all si nal output is /out, what is the s"all si naloutput? What is the ain?

Newly updated questions

at (arch 7229 5s I said abo/e, I would put "ore questions when I $irst set up this pa e...then I always $eel to busy to do it...and I ot a lot o$ e"ails askin about this...this "ade "e $eel uilty, a little. 5nd +I<5DDE a $ew "ore questions co"e out. These question are "aily on #1 network. they are si"ple, but really are o$ten asked. I was asked al"ost e/ery question one way or the other. 3>. +i ure out the %out wa/e $or" o$ the $ollowin circuits0

+i ure 3

+i ure 7

+i ure 8

+i ure 9 5nswer Hints0 The basic concept to reply these kind o$ #1 (or #D1) network questions is that0 $or 1, it resistance is in$inity when $requencyB2 and 2 when $requency is in$inity. (+or D, its resistnace is 2 when $requencyB2 while its resitance is in$inity when $requency is in$inity. 34. +or the $ollowin circuit, at ti"e 2, the switch switches $ro" 5 to -, $i ure out the /olta e wa/e $or" at -. <ote0 this is a FclassicF question. It was asked 32 years a o and I was asked this question just recently. Eou "i ht be asked this question neGt ti"e... 3?. +o the $ollowin circuit, what is the /olta e /alue at 5 and -? (The %t o$ the transistor is 3%).

72. The capacitor o$ the $ollowin $i ure is connected with two ideal ()* switches. *witches T3 and T7 are alternately turned on with a $requency $$c. What is the a/era e current $lowin $ro" node 3 to node 7? What is the equi/alent i"pedance $ro" node 3 to node 7?

73. Eou are porbin a square wa/e pulse in the lab that has a ris eti"e o$ : ns and $all ti"e o$ 7 ns. What is the "ini"u" bandwidth o$ the oscilloscope to /iew the si nal? 5nswer0 The ti"e thay it takes an #1 circuit to o $ro" 32H to ?2H o$ its $inal /alue is tBln?I#1. The bandwidth o$ the oscilloscope lar er than -WBln?&(7IpiI7ns)B3>9(HJ. 1hoose a 722(HJ or $aster oscilloscope. To reduce error, choose a oscolloscope 8 ti"e $aster than the calculated /alue, or =22(HJ. ). Can you talk about low power techniques? How low power and latest 90nm/65nm technologies are related? #e$er here and browse $or di$$erent low power techniques. o you know about input !ector controlled method o" leakage reduction? Deaka e current o$ a ate is dependant on its inputs also. Hence $ind the set o$ inputs which i/es least leaka e. -y applyi this "ini"u" leaka e /ector to a circuit it is possible to decrease the leaka e current o$ the circuit when it is in the standby "ode. This "ethod is known as input /ector controlled "ethod o$ leaka e reduction. How can you reduce dynamic power? !#educe switchin acti/ity by desi nin ood #TD !1lock atin !5rchitectural i"pro/e"ents !#educe supply /olta e !@se "ultiple /olta e do"ains!(ulti /dd

#hat are the !ectors o" dynamic power? %olta e and 1urrent How will you do power planning? #e$er here $or power plannin .

$" you ha!e both $% drop and congestion how will you "i& it? !*pread "acros !*pread standard cells !Increase strap width !Increase nu"ber o$ straps !@se proper blocka e

$s increasing power line width and pro!iding more number o" straps are the only solution to $% drop? !*pread "acros !*pread standard cells !@se proper blocka e $n a reg to reg path i" you ha!e setup problem where will you insert bu""er'near to launching "lop or capture "lop? #hy? (bu$$ers are inserted $or $iGin $anout /oilations and hence they reduce setup /oilationK otherwise we try to $iG setup /oilation with the siJin o$ cellsK now just assu"e that you "ust insert bu$$er !) <ear to capture path. -ecause there "ay be other paths passin throu h or ori inatin $ro" the $lop nearer to lauch $lop. Hence bu$$er insertion "ay a$$ect other paths also. It "ay i"pro/e all those paths or de arde. I$ all those paths ha/e /oilation then you "ay insert bu$$er nearer to launch $lop pro/ided it i"pro/es slack. How will you decide best "loorplan? #e$er here $or $loor plannin . #hat is the most challenging task you handled? #hat is the most challenging (ob in )*% "low? !It "ay be power plannin ! because you $ound "ore I# drop !It "ay be low power tar et!because you had "ore dyna"ic and leaka e power !It "ay be "acro place"ent!because it had "ore connection with standard cells or "acros !It "ay be 1T*!because you needed to handle "ultiple clocks and clock do"ain crossin s !It "ay be ti"in !because siJin cells in ,1) $low is not "eetin ti"in !It "ay be library preparation!because you $ound so"e inconsistancy in libraries. !It "ay be ;#1!because you $aced thousands o$ /oilations

How will you synthesi+e clock tree? !*in le clock!nor"al synthesis and opti"iJation !(ultiple clocks!*ynthesis each clock seperately !(ultiple clocks with do"ain crossin !*ynthesis each clock seperately and balance the skew How many clocks were there in this pro(ect? !It is speci$ic to your project !(ore the clocks "ore challen in ! How did you handle all those clocks? !(ultiple clocksLMsynthesiJe seperatelyLMbalance the skewLMopti"iJe the clock tree ,re they come "rom seperate e&ternal resources or )--? !I$ it is $ro" seperate clock sources (i.e.asynchronousK $ro" di$$erent pads or pins) then balancin skew between these clock sources beco"es challen in . !I$ it is $ro" ADD (i.e.synchronous) then skew balancin is co"parati/ely easy. #hy bu""ers are used in clock tree? To balance skew (i.e. $lop to $lop delay) #hat is cross talk?

 *witchin o$ the si nal in one net can inter$ere nei bourin net due to cross couplin capacitance.This a$$ect is known as cros talk. 1ross talk "ay lead setup or hold /oilation. How can you a!oid cross talk? !;ouble spacin BM"ore spacin BMless capacitanceBMless cross talk !(ultiple /iasBMless resistanceBMless #1 delay !*hieldin BM constant cross couplin capacitance BMknown /alue o$ crosstalk !-u$$er insertionBMboost the /icti" stren th

How shielding a!oids crosstalk problem? #hat e&actly happens there? !Hi h $requency noise (or litch)is coupled to %** (or %;;) since shilded layers are connected to either %;; or %**. 1ouplin capacitance re"ains constant with %;; or %**. How spacing helps in reducing crosstalk noise? width is "oreBM"ore spacin between two conductorsBMcross couplin capacitance is lessBMless cross talk #hy double spacing and multiple !ias are used related to clock? Why clock?L because it is the one si nal which cha es it state re ularly and "ore co"pared to any other si nal. I$ any other si nal switches $ast then also we can use double space. ;ouble spacin BMwidth is "oreBMcapacitance is lessBMless cross talk (ultiple /iasBMresistance in parellelBMless resistanceBMless #1 delay How bu""er can be used in !ictim to a!oid crosstalk? -u$$er increase /icti"s si nal stren thK bu$$ers break the net len thBM/icti"s are "ore tolerant to coupled si nal $ro" a ressor. 2 co""ents Dinks to this post Dabels0 Ahysical ;esi n, *ynthesis, Ti"in 5nalysis
)hysical esign .uestions and ,nswers

I a" ettin se/eral e"ails requestin answers to the questions posted in this blo . -ut it is /ery di$$icult to pro/ide detailed answer to all questions in "y a/ailable spare ti"e. Hence i decided to i/e Nshort and sweetO one line answers to the questions so that readers can i""ediately bene$ited. ;etailed answers will be posted in later sta e.I ha/e i/en answers to so"e o$ the physical desi n questions here. ,njoy ! #hat parameters /or aspects0 di""erentiate Chip esign and 1lock le!el design? 1hip desi n has I&) padsK block desi n has pins. 1hip desi n uses all "etal layes a/ailableK block desi n "ay not use all "etal layers. 1hip is enerally rectan ular in shapeK blocks can be rectan ular, rectilinear. 1hip desi n requires se/eral packa in K block desi n ends in a "acro. How do you place macros in a "ull chip design? +irst check $lylines i.e. check net connections $ro" "acro to "acro and "acro to standard cells. I$ there is "ore connection $ro" "acro to "acro place those "acros nearer to each other pre$erably nearer to core boundaries. I$ input pin is connected to "acro better to place nearer to that pin or pad. I$ "acro has "ore connection to standard cells spread the "acros inside core. 5/oid criscross place"ent o$ "acros. @se so$t or hard blocka es to uide place"ent en ine. i""erentiate between a Hierarchical esign and "lat design?

 Hierarchial desi n has blocks, subblocks in an hierarchyK +lattened desi n has no subblocks and it has only lea$ cells. Hierarchical desi n takes "ore run ti"eK +lattened desi n takes less run ti"e. #hich is more complicated when u ha!e a 23 4H+ and 500 4H+ clock design? :22 (HJK because it is "ore constrained (i.e.lesser clock period) than 94 (HJ desi n. Name "ew tools which you used "or physical !eri"ication? Herculis $ro" *ynopsys, 1aliber $ro" (entor Craphics. #hat are the input "iles will you gi!e "or primetime correlation? <etlist, Technolo y library, 1onstraints, *A,+ or *;+ $ile. $" the routing congestion e&ists between two macros5 then what will you do? Aro/ide so$t or hard blocka e How will you decide the die si+e? -y checkin the total area o$ the desi n you can decide die siJe. $" lengthy metal layer is connected to di""usion and poly5 then which one will a""ect by antenna problem? Aoly $" the "ull chip design is routed by 6 layer metal5 why macros are designed using 5-4 instead o" using 6-4? -ecause top two "etal layers are required $or lobal routin in chip desi n. I$ top "etal layers are also used in block le/el it will create routin blocka e. $n your pro(ect what is die si+e5 number o" metal layers5 technology5 "oundry5 number o" clocks? ;ie siJe0 tell in "" e . 3"" G 3"" K re"eber 3""B3222"icron which is a bi siJe !! (etal layers0 *ee your tech $ile. enerally $or ?2n" it is > to ?. Technolo y0 5 ain look into tech $iles. +oundry05 ain look into tech $ilesK e . T*(1, I-(, 5#TI*5< etc 1locks0 Dook into your desi n and *;1 $ile ! How many macros in your design? Eou know it well as you ha/e desi ned it ! 5 *o1 (*yste" )n 1hip) desi n "ay ha/e 322 "acros also !!!! #hat is each macro si+e and number o" standard cell count? ;epends on your desi n. #hat are the input needs "or your design? +or synthesis0 #TD, Technolo y library, *tandard cell library, 1onstraints +or Ahysical desi n0 <etlist, Technolo y library, 1onstraints, *tandard cell library #hat is 7 C constraint "ile contains? 1lock de$initions Ti"in eGception!"ulticycle path, $alse path Input and )utput delays How did you do power planning? How to calculate core ring width5 macro ring width and strap or trunk width? How to "ind number o" power pad and $8 power pads? How the width o" metal and number o" straps calculated "or power and ground?

 Cet the total core power consu"ptionK et the "etal layer current density /alue $ro" the tech $ileK ;i/ide total power by nu"ber sides o$ the chipK ;i/ide the obtained /alue $ro" the current density to et core power rin width. Then calculate nu"ber o$ straps usin so"e "ore equations. Will be eGplained in detail later. How to "ind total chip power? Total chip powerBstandard cell power consu"ption,(acro power consu"ption pad power consu"ption. #hat are the problems "aced related to timing? Arelayout0 *etup, (aG transition, "aG capacitance Aost layout0 Hold How did you resol!e the setup and hold problem? *etup0 upsiJe the cells Hold0 insert bu$$ers $n which layer do you pre"er "or clock routing and why? <eGt lower layer to the top two "etal layers( lobal routin layers). -ecause it has less resistance hence less #1 delay. $" in your design has reset pin5 then it9ll a""ect input pin or output pin or both? )utput pin. uring power analysis5 i" you are "acing $% drop problem5 then how did you a!oid? Increase power "etal layer width. Co $or hi her "etal layer. *pread "acros or standard cells. Aro/ide "ore straps. e"ine antenna problem and how did you resol!e these problem? Increased net len th can accu"ulate "ore char es while "anu$acturin o$ the de/ice due to ionisation process. I$ this net is connected to ate o$ the ()*+,T it can da"a e dielectric property o$ the ate and ate "ay conduct causin da"a e to the ()*+,T. This is antenna proble". ;ecrease the len th o$ the net by pro/idin "ore /ias and layer ju"pin . Insert antenna diode. How delays !ary with di""erent ):; conditions? 7how the graph< A increase!Mdealy increase A decrease!Mdelay decrease % increase!Mdelay decrease % decrease!Mdelay increase T increase!Mdelay increase T decrease!Mdelay decrease =&plain the "low o" physical design and inputs and outputs "or each step in "low< 1lick here to see the $low dia ra" #hat is cell delay and net delay? >ate delay Transistors within a ate take a $inite ti"e to switch. This "eans that a chan e on the input o$ a ate takes a $inite ti"e to cause a chan e on the output.P(a "aQ

 Cate delay B$unction o$(i&p transition ti"e, 1netR1pin). 1ell delay is also sa"e as Cate delay. Cell delay +or any ate it is "easured between :2H o$ input transition to the correspondin :2H o$ output transition. Intrinsic delay Intrinsic delay is the delay internal to the ate. Input pin o$ the cell to output pin o$ the cell. It is de$ined as the delay between an input and output pair o$ a cell, when a near Jero slew is applied to the input pin and the output does not see any load condition.It is predo"inantly caused by the internal capacitance associated with its transistor. This delay is lar ely independent o$ the siJe o$ the transistors $or"in the ate because increasin siJe o$ transistors increase internal capacitors. Net elay /or wire delay0 The di$$erence between the ti"e a si nal is $irst applied to the net and the ti"e it reaches other de/ices connected to that net. It is due to the $inite resistance and capacitance o$ the net.It is also known as wire delay. Wire delay B$n(#net , 1netR1pin) #hat are delay models and what is the di""erence between them? Dinear ;elay (odel (D;() <on Dinear ;elay (odel (<D;() #hat is wire load model? Wire load "odel is <D;( which has esti"ated # and 1 o$ the net. #hy higher metal layers are pre"erred "or :dd and :ss? -ecause it has less resistance and hence leads to less I# drop. #hat is logic optimi+ation and gi!e some methods o" logic optimi+ation< @psiJin ;ownsiJin -u$$er insertion -u$$er relocation ;u""y bu$$er place"ent #hat is the signi"icance o" negati!e slack? ne ati/e slackBBM there is setup /oilationBBM deis n can $ail #hat is signal integrity? How it a""ects ;iming? I# drop, ,lectro (i ration (,(), 1rosstalk, Cround bounce are si nal inte rity issues. I$ Idrop is "oreBBMdelay increases. crosstalkBBMthere can be setup as well as hold /oilation. #hat is $% drop? How to a!oid? How it a""ects timing? There is a resistance associated with each "etal layer. This resistance consu"es power causin /olta e drop i.e.I# drop. I$ I# drop is "oreBBMdelay increases. #hat is =4 and it e""ects?

 ;ue to hi h current $low in the "etal ato"s o$ the "etal can displaced $ro" its ori ial place. When it happens in lar er a"ount the "etal can open or bul in o$ "etal layer can happen. This e$$ect is known as ,lectro (i ration. 5$$ects0 ,ither short or open o$ the si nal line or power line. #hat are types o" routing? Clobal #outin Track 5ssi n"ent ;etail #outin #hat is latency? >i!e the types? 7ource -atency It is known as source latency also. It is de$ined as Nthe delay $ro" the clock ori in point to the clock de$inition point in the desi nO. ;elay $ro" clock source to be innin o$ clock tree (i.e. clock de$inition point). The ti"e a clock si nal takes to propa ate $ro" its ideal wa/e$or" ori in point to the clock de$inition point in the desi n. Network latency It is also known as Insertion delay or <etwork latency. It is de$ined as Nthe delay $ro" the clock de$inition point to the clock pin o$ the re isterO. The ti"e clock si nal (rise or $all) takes to propa ate $ro" the clock de$inition point to a re ister clock pin. #hat is track assignment? *econd sta e o$ the routin wherein particular "etal tracks (or layers) are assi ned to the si nal nets. #hat is congestion? I$ the nu"ber o$ routin tracks a/ailable $or routin is less than the required tracks then it is known as con estion. #hether congestion is related to placement or routing? #outin #hat are clock trees? ;istribution o$ clock $ro" the clock source to the sync pin o$ the re isters. #hat are clock tree types? H tree, -alanced tree, 6 tree, 1lusterin tree, +ish bone #hat is cloning and bu""ering? 1lonin is a "ethod o$ opti"iJation that decreases the load o$ a hea/ily loaded cell by replicatin the cell. -u$$erin is a "ethod o$ opti"iJation that is used to insert be$$ers in hi h $anout nets to decrease the dealy.
#hat is the di""erence between a latch and a "lip'"lop?

-oth latches and $lip!$lops are circuit ele"ents whose output depends not only on the present inputs, but also on pre/ious inputs and outputs. They both are hence re$erred as NsequentialO ele"ents. In electronics, a latch, is a kind o$ bistable "ulti /ibrator, an electronic circuit which has two stable states and thereby can store one bit o$ o$ in$or"ation. Today the word is "ainly used $or si"ple transparent stora e ele"ents, while sli htly "ore ad/anced non!transparent (or clocked) de/ices are described as $lip! $lops. In$or"ally, as this distinction is quite new, the two words are so"eti"es used interchan eably. PwikiQ In di ital circuits, a $lip!$lop is a kind o$ bistable "ulti /ibrator, an electronic circuit which has two stable

states and thereby is capable o$ ser/in as one bit o$ "e"ory. Today, the ter" $lip!$lop has co"e to enerally denote non!transparent (clocked or ed e!tri ered) de/ices, while the si"pler transparent ones are o$ten re$erred to as latches.PwikiQ 5 $lip!$lop is controlled by (usually) one or two control si nals and&or a ate or clock si nal. Datches are le/el sensiti/e i.e. the output captures the input when the clock si nal is hi h, so as lon as the clock is lo ic 3, the output can chan e i$ the input also chan es. +lip!+lops are ed e sensiti/e i.e. $lip $lop will store the input only when there is a risin or $allin ed e o$ the clock. 5 positi/e le/el latch is transparent to the positi/e le/el(enable), and it latches the $inal input be$ore it is chan in its le/el(i.e. be$ore enable oes to S2T or be$ore the clock oes to !/e le/el.) 5 positi/e ed e $lop will ha/e its output e$$ecti/e when the clock input chan es $ro" S2T to S3T state (S3T to S2T $or ne ati/e ed e $lop) only. Datches are $aster, $lip $lops are slower. Datch is sensiti/e to litches on enable pin, whereas $lip!$lop is i""une to litches. Datches take less ates (less power) to i"ple"ent than $lip!$lops. ;!++ is built $ro" two latches. They are in "aster sla/e con$i uration. Datch "ay be clocked or clock less. -ut $lip $lop is always clocked. +or a transparent latch enerally ; to U propa ation delay is considered while $or a $lop clock to U and setup and hold ti"e are /ery i"portant. 7ynthesis perspecti!e? )ros and Cons o" -atches and @lip @lops In synthesis o$ H;D codes inappropriate codin can in$er latches instead o$ $lip $lops. , .0Oi$O and NcaseO state"ents. This should be a/oided sa latches are "ore prone to litches. Datch takes less area, +lip!$lop takes "ore area ( as $lip $lop is "ade up o$ latches) . Datch $acilitate ti"e borrowin or cycle stealin whereas $lip $lops allow synchronous lo ic. Datches are not $riendly with ;+T tools. (ini"iJe in$errin o$ latches i$ your desi n has to be "ade testable. *ince enable si nal to latch is not a re ular clock that is $ed to the rest o$ the lo ic. To ensure testability, you need to use )# ate usin NenableOV and NscanWenableO si nals as input and $eed the output to the enable port o$ the latch. Pre$Q (ost ,;5 so$tware tools ha/e di$$iculty with latches. *tatic ti"in analyJers typically "ake assu"ptions about latch transparency. I$ one assu"es the latch is transparent (i.e.tri ered by the acti/e ti"e o$ clock,not tri ered by just clock ed e), then the tool "ay $ind a $alse ti"in path throu h the input data pin. I$ one assu"es the latch is not transparent, then the tool "ay "iss a critical path. I$ tar et technolo y supports a latch cell then race condition proble"s are "ini"iJed. I$ tar et technolo y does not support a latch then synthesis tool will in$er it by basic ates which is prone to race condition. Then you need to add redundant lo ic to o/erco"e this proble". -ut while opti"iJation redundant lo ic can be re"o/ed by the synthesis tool ! This will create endless proble"s $or the desi n tea". ;ue to the transparency issue, latches are di$$icult to test. +or scan testin , they are o$ten replaced by a latch!$lip!$lop co"patible with the scan!test shi$t!re ister. @nder these conditions, a $lip!$lop would actually be less eGpensi/e than a latch. #ead a ood article on proble"s o$ latch published in eeti"es lon back !! +lip $lops are $riendly with ;+T tools. *can insertion $or synchronous lo ic is hassle $ree. 7 co""ents Dinks to this post Dabels0 ;i ital desi n
#hat are the di""erent types o" delays in ,7$C or :-7$ design?

i""erent ;ypes o" elays in ,7$C or :-7$ design

 7ource elay/-atency Network elay/-atency $nsertion elay ;ransition elay/7lew? %ise time5 "all time )ath elay Net delay5 wire delay5 interconnect delay )ropagation elay )hase elay Cell elay $ntrinsic elay =&trinsic elay $nput elay 8utput elay =&it elay -atency /)re/post C;70 Ancertainty /)re/)ost C;70 Anateness? )ositi!e unateness5 negati!e unateness Bitter? )-- (itter5 clock (itter >ate delay Transistors within a ate take a $inite ti"e to switch. This "eans that a chan e on the input o$ a ate takes a $inite ti"e to cause a chan e on the output.P(a "aQ Cate delay B$unction o$(i&p transition ti"e, 1netR1pin). 1ell delay is also sa"e as Cate delay. 7ource elay /or 7ource -atency0 It is known as source latency also. It is de$ined as Nthe delay $ro" the clock ori in point to the clock de$inition point in the desi nO. ;elay $ro" clock source to be innin o$ clock tree (i.e. clock de$inition point). The ti"e a clock si nal takes to propa ate $ro" its ideal wa/e$or" ori in point to the clock de$inition point in the desi n. Network elay/latency0 It is also known as Insertion delay or <etwork latency. It is de$ined as Nthe delay $ro" the clock de$inition point to the clock pin o$ the re isterO. The ti"e clock si nal (rise or $all) takes to propa ate $ro" the clock de$inition point to a re ister clock pin. $nsertion delay The delay $ro" the clock de$inition point to the clock pin o$ the re ister. ;ransition delay It is also known as N*lewO. It is de$ined as the ti"e taken to chan e the state o$ the si nal. Ti"e taken $or the transition $ro" lo ic 2 to lo ic 3 and /ice /ersa . or Ti"e taken by the input si nal to rise $ro" 32H(72H) to the ?2H(42H) and /ice /ersa. Transition is the ti"e it takes $or the pin to chan e state.

7lew #ate o$ chan e o$ lo ic.*ee Transition delay. *lew rate is the speed o$ transition "easured in /olt & ns. %ise ;ime #ise ti"e is the di$$erence between the ti"e when the si nal crosses a low threshold to the ti"e when the si nal crosses the hi h threshold. It can be absolute or percent. Dow and hi h thresholds are $iGed /olta e le/els around the "id /olta e le/el or it can be either 32H and ?2H respecti/ely or 72H and 42H respecti/ely. The percent le/els are con/erted to absolute /olta e le/els at the ti"e o$ "easure"ent by calculatin percenta es $ro" the di$$erence between the startin /olta e le/el and the $inal settled /olta e le/el. @all ;ime +all ti"e is the di$$erence between the ti"e when the si nal crosses a hi h threshold to the ti"e when the si nal crosses the low threshold. The low and hi h thresholds are $iGed /olta e le/els around the "id /olta e le/el or it can be either 32H and ?2H respecti/ely or 72H and 42H respecti/ely. The percent le/els are con/erted to absolute /olta e le/els at the ti"e o$ "easure"ent by calculatin percenta es $ro" the di$$erence between the startin /olta e le/el and the $inal settled /olta e le/el. +or an ideal square wa/e with :2H duty cycle, the rise ti"e will be 2.+or a sy""etric trian ular wa/e, this is reduced to just :2H. 1lick here to see wa/e$or". 1lick here to see "ore in$o. The rise&$all de$inition is set on the "eter to 32H and ?2H based on the linear power in Watts. These points translate into the !32 d- and !2.: d- points in lo "ode (32 lo 2.3) and (32 lo 2.?). The rise&$all ti"e /alues o$ 32H and ?2H are calculated based on an al orith", which looks at the "ean power abo/e and below the :2H points o$ the rise&$all ti"es. 1lick here to see "ore. )ath delay Aath delay is also known as pin to pin delay. It is the delay $ro" the input pin o$ the cell to the output pin o$ the cell. Net elay /or wire delay0 The di$$erence between the ti"e a si nal is $irst applied to the net and the ti"e it reaches other de/ices connected to that net. It is due to the $inite resistance and capacitance o$ the net.It is also known as wire delay. Wire delay B$n(#net , 1netR1pin) )ropagation delay +or any ate it is "easured between :2H o$ input transition to the correspondin :2H o$ output transition. This is the ti"e required $or a si nal to propa ate throu h a ate or net. +or ates it is the ti"e it takes $or a e/ent at the ate input to a$$ect the ate output. +or net it is the delay between the ti"e a si nal is $irst applied to the net and the ti"e it reaches other de/ices connected to that net. It is taken as the a/era e o$ rise ti"e and $all ti"e i.e. TpdB (TphlRTplh)&7. )hase delay *a"e as insertion delay Cell delay +or any ate it is "easured between :2H o$ input transition to the correspondin :2H o$ output transition.

$ntrinsic delay Intrinsic delay is the delay internal to the ate. Input pin o$ the cell to output pin o$ the cell. It is de$ined as the delay between an input and output pair o$ a cell, when a near Jero slew is applied to the input pin and the output does not see any load condition.It is predo"inantly caused by the internal capacitance associated with its transistor. This delay is lar ely independent o$ the siJe o$ the transistors $or"in the ate because increasin siJe o$ transistors increase internal capacitors. =&trinsic delay *a"e as wire delay, net delay, interconnect delay, $li ht ti"e. ,Gtrinsic delay is the delay e$$ect that associated to with interconnect. output pin o$ the cell to the input pin o$ the neGt cell. $nput delay Input delay is the ti"e at which the data arri/es at the input pin o$ the block $ro" eGternal circuit with respect to re$erence clock. 8utput delay )utput delay is ti"e required by the eGternal circuit be$ore which the data has to arri/e at the output pin o$ the block with respect to re$erence clock. =&it delay It is de$ined as the delay in the lon est path (critical path) between clock pad input and an output. It deter"ines the "aGi"u" operatin $requency o$ the desi n. -atency /pre/post cts0 Datency is the su""ation o$ the *ource latency and the <etwork latency. Are 1T* esti"ated latency will be considered durin the synthesis and a$ter 1T* propa ated latency is considered. Ancertainty /pre/post cts0 @ncertainty is the a"ount o$ skew and the /ariation in the arri/al clock ed e. Are 1T* uncertainty is clock skew and clock .itter. 5$ter 1T* we can ha/e so"e "ar in o$ skew R .itter. Anateness 5 $unction is said to be unate i$ the rise transition on the positi/e unate input /ariable causes the ouput to rise or no chan e and /ice /ersa. <e ati/e unateness "eans cell output lo ic is in/erted /ersion o$ input lo ic. e . In in/erter ha/in input 5 and output E, E is !/e unate w.r.to 5. Aositi/e unate "eans cell output lo ic is sa"e as that o$ input. These R/e ad !/e unateness are constraints de$ined in library $ile and are de$ined $or output pin w.r.to so"e input pin. 5 clock si nal is positi/e unate i$ a risin ed e at the clock source can only cause a risin ed e at the re ister clock pin, and a $allin ed e at the clock source can only cause a $allin ed e at the re ister clock pin. 5 clock si nal is ne ati/e unateV i$ a risin ed e at the clock source can only cause a $allin ed e at the re ister clock pin, and a $allin ed e at the clock source can only cause a risin ed e at the re ister clock pin. In other words, the clock si nal is in/erted. 5 clock si nal is not unate i$ the clock sense is a"bi uous as a result o$ non!unate ti"in arcs in the clock path. +or eGa"ple, a clock that passes throu h an 6)# ate is not unate because there are nonunate arcs in the ate. The clock sense could be either positi/e or ne ati/e, dependin on the state o$ the other input to the 6)# ate. Bitter The short!ter" /ariations o$ a si nal with respect to its ideal position in ti"e.

 .itter is the /ariation o$ the clock period $ro" ed e to ed e. It can /arry R&! jitter /alue. +ro" cycle to cycle the period and duty cycle can chan e sli htly due to the clock eneration circuitry. This can be "odeled by addin uncertainty re ions around the risin and $allin ed es o$ the clock wa/e$or". 7ources o" Bitter 1o""on sources o$ jitter include0 Internal circuitry o$ the phase!locked loop (ADD) #ando" ther"al noise $ro" a crystal )ther resonatin de/ices #ando" "echanical noise $ro" crystal /ibration *i nal trans"itters Traces and cables 1onnectors #ecei/ers 1lick here to read "ore about jitter $ro" 5ltera. 1lick here to read what wiki says about jitter. 7kew The di$$erence in the arri/al o$ clock si nal at the clock pin o$ di$$erent $lops. Two types o$ skews are de$ined0 Docal skew and Clobal skew. -ocal skew The di$$erence in the arri/al o$ clock si nal at the clock pin o$ related $lops. >lobal skew The di$$erence in the arri/al o$ clock si nal at the clock pin o$ non related $lops. *kew can be positi/e or ne ati/e. When data and clock are routed in sa"e direction then it is )ositi!e skew< When data and clock are routed in opposite then it is negati!e skew< %eco!ery ;ime #eco/ery speci$ies the "ini"u" ti"e that an asynchronous control input pin "ust be held stable a$ter bein de!asserted and be$ore the neGt clock (acti/e!ed e) transition. #eco/ery ti"e speci$ies the ti"e the inacti/e ed e o$ the asynchronous si nal has to arri/e be$ore the closin ed e o$ the clock. #eco/ery ti"e is the "ini"u" len th o$ ti"e an asynchronous control si nal (e .preset) "ust be stable be$ore the neGt acti/e clock ed e. The reco/ery slack ti"e calculation is si"ilar to the clock setup slack ti"e calculation, but it applies asynchronous control si nals. ,quation 30 #eco/ery *lack Ti"e B ;ata #equired Ti"e XYN ;ata 5rri/al Ti"e ;ata 5rri/al Ti"e B Daunch ,d e R 1lock <etwork ;elay to *ource #e ister R TclkqR #e ister to #e ister ;elay ;ata #equired Ti"e B Datch ,d e R 1lock <etwork ;elay to ;estination #e ister BTsetup I$ the asynchronous control is not re istered, equations shown in ,quation 7 is used to calculate the reco/ery slack ti"e. ,quation 70 #eco/ery *lack Ti"e B ;ata #equired Ti"e XYN ;ata 5rri/al Ti"e

 ;ata 5rri/al Ti"e B Daunch ,d e R (aGi"u" Input ;elay R Aort to #e ister ;elay ;ata #equired Ti"e B Datch ,d e R 1lock <etwork ;elay to ;estination #e ister ;elayRTsetup I$ the asynchronous reset si nal is $ro" a port (de/ice I&)), you "ust "ake an Input (aGi"u" ;elay assi n"ent to the asynchronous reset pin to per$or" reco/ery analysis on that path. %emo!al ;ime #e"o/al speci$ies the "ini"u" ti"e that an asynchronous control input pin "ust be held stable be$ore bein de!asserted and a$ter the pre/ious clock (acti/e!ed e) transition. #e"o/al ti"e speci$ies the len th o$ ti"e the acti/e phase o$ the asynchronous si nal has to be held a$ter the closin ed e o$ clock. #e"o/al ti"e is the "ini"u" len th o$ ti"e an asynchronous control si nal "ust be stable a$ter the acti/e clock ed e. 1alculation is si"ilar to the clock hold slack calculation, but it applies asynchronous control si nals. I$ the asynchronous control is re istered, equations shown in ,quation 8 is used to calculate the re"o/al slack ti"e. I$ the reco/ery or re"o/al "ini"u" ti"e require"ent is /iolated, the output o$ the sequential cell beco"es uncertain. The uncertainty can be caused by the /alue set by the resetbar si nal or the /alue clocked into the sequential cell $ro" the data input. ,quation 8 #e"o/al *lack Ti"e B ;ata 5rri/al Ti"e XYN ;ata #equired Ti"e ;ata 5rri/al Ti"e B Daunch ,d e R 1lock <etwork ;elay to *ource #e ister R Tclkq o$ *ource #e ister R #e ister to #e ister ;elay ;ata #equired Ti"e B Datch ,d e R 1lock <etwork ;elay to ;estination #e ister R Thold I$ the asynchronous control is not re istered, equations shown in ,quation 9 is used to calculate the re"o/al slack ti"e. ,quation 9 #e"o/al *lack Ti"e B ;ata 5rri/al Ti"e XYN ;ata #equired Ti"e ;ata 5rri/al Ti"e B Daunch ,d e R Input (ini"u" ;elay o$ Ain R (ini"u" Ain to #e ister ;elay ;ata #equired Ti"e B Datch ,d e R 1lock <etwork ;elay to ;estination #e ister RThold I$ the asynchronous reset si nal is $ro" a de/ice pin, you "ust speci$y the Input (ini"u" ;elay constraint to the asynchronous reset pin to per$or" a re"o/al analysis on this path.
#hat is the di""erence between so"t macro and hard macro?

#hat is the di""erence between hard macro5 "irm macro and so"t macro? or #hat are $)s? Hard "acro, $ir" "acro and so$t "acro are all known as IA (Intellectual property). They are opti"iJed $or power, area and per$or"ance. They can be purchased and used in your 5*I1 or +AC5 desi n i"ple"entation $low. *o$t "acro is $leGible $or all type o$ 5*I1 i"ple"entation. Hard "acro can be used in pure 5*I1 desi n $low, not in +AC5 $low. -e$ore byin any IA it is /ery i"portant to e/aluate its ad/anta es and disad/anta es o/er each other, hardware co"patibility such as I&) standards with your desi n blocks, reusability $or other desi ns. 7o"t macros *o$t "acros are in synthesiJable #TD. *o$t "acros are "ore $leGible than $ir" or hard "acros. *o$t "acros are not speci$ic to any "anu$acturin process. *o$t "acros ha/e the disad/anta e o$ bein so"ewhat unpredictable in ter"s o$ per$or"ance, ti"in , area,

or power. *o$t "acros carry reater IA protection risks because #TD source code is "ore portable and there$ore, less easily protected than either a netlist or physical layout data. +ro" the physical desi n perspecti/e, so$t "acro is any cell that has been placed and routed in a place"ent and routin tool such as 5stro. (This is the de$inition i/en in 5stro #ail user "anual !) *o$t "acros are editable and can contain standard cells, hard "acros, or other so$t "acros. @irm macros +ir" "acros are in netlist $or"at. +ir" "acros are opti"iJed $or per$or"ance&area&power usin a speci$ic $abrication technolo y. +ir" "acros are "ore $leGible and portable than hard "acros. +ir" "acros are predicti/e o$ per$or"ance and area than so$t "acros. Hard macro Hard "acros are enerally in the $or" o$ hardware IAs (or we ter"ed it as hardwre IAs !). Hard "acos are tar eted $or speci$ic I1 "anu$acturin technolo y. Hard "acros are block le/el desi ns which are silicon tested and pro/ed. Hard "acros ha/e been opti"iJed $or power or area or ti"in . In physical desi n you can only access pins o$ hard "acros unlike so$t "acros which allows us to "anipulate in di$$erent way. Eou ha/e $reedo" to "o/e, rotate, $lip but you canSt touch anythin inside hard "acros. %ery co""on eGa"ple o$ hard "acro is "e"ory. It can be any desi n which carries dedicated sin le $unctionality (in eneral).. $or eGa"ple it can be a (A9 decoder. -e aware o$ $eatures and characteristics o$ hard "acro be$ore you use it in your desi nZ other than power, ti"in and area you also should know pin properties like sync pin, I&) standards etc D,+, C;*7 $ile $or"at allows easy usa e o$ "acros in di$$erent tools. +ro" the physical desi n (backend) perspecti/e0 Hard "acro is a block that is enerated in a "ethodolo y other than place and route (i.e. usin $ull custo" desi n "ethodolo y) and is brou ht into the physical desi n database (e . (ilkyway in *ynopsysK %olcano in (a "a) as a C;*7 $ile. Here is one article published in e"bedded "a aJine about IAs. 1lick here to read. *ynthesis and place"ent o$ "acros in "odern *o1 desi ns are challen in . ,;5 tools e"ploy di$$erent al orith"s acco"plish this task alon with the tar et o$ power and area. There are se/eral research papers a/ailable on these subjects. *o"e o$ the" can be downloaded $ro" the i/en link below. NHard (acro Alace"ent in 1o"pleG *o1 ;esi nO L /iew and read article $ro" soccentral NHard (acro Alace"ent in 1o"pleG *o1 ;esi nO L download white paper $===/Ani!erity research papers NDocal *earch $or +inal Alace"ent in %D*I ;esi nO !download N1onsistent Alace"ent o$ (acro!-locks @sin +loorplannin and standard cell place"entO L download N5 Ti"in !;ri/en *o$t!(acro Alace"ent 5nd #esynthesis (ethod In Interaction with 1hip +loorplannin O L download 2 co""ents Dinks to this post Dabels0 5*I1, Ahysical ;esi n, %D*I
#hat is the di""erence between @)>, and C)- ?

+AC5!+ield Aro ra""able Cate 5rray and 1AD;!1o"pleG Aro ra""able Do ic ;e/iceL both are pro ra""able lo ic de/ices "ade by the sa"e co"panies with di$$erent characteristics. N5 1o"pleG Aro ra""able Do ic ;e/ice (1AD;) is a Aro ra""able Do ic ;e/ice with co"pleGity between that o$ A5Ds (Aro ra""able 5rray Do ic) and +AC5s, and architectural $eatures o$ both. The buildin block o$ a 1AD; is the "acro cell, which contains lo ic i"ple"entin disjuncti/e nor"al $or" eGpressions and "ore specialiJed lo ic operationsO. This is what Wiki de$inesZ..!! 1lick here to see what else wiki has to say about it ! ,rchitecture Cranularity is the bi est di$$erence between 1AD; and +AC5. +AC5 are N$ine! rainO de/ices. That "eans that they contain hundreds o$ (up to 322222) o$ tiny blocks (called as D@T or 1D-s etc) o$ lo ic with $lip!$lops, co"binational lo ic and "e"ories.+AC5s o$$er "uch hi her co"pleGity, up to 3:2,222 $lip!$lops and lar e nu"ber o$ ates a/ailable. 1AD;s typically ha/e the equi/alent o$ thousands o$ lo ic ates, allowin i"ple"entation o$ "oderately co"plicated data processin de/ices. A5Ds typically ha/e a $ew hundred ate equi/alents at "ost, while +AC5s typically ran e $ro" tens o$ thousands to se/eral "illion. 1AD; are Ncoarse! rainO de/ices. They contain relati/ely $ew (a $ew 322Ts "aG) lar e blocks o$ lo ic with $lip!$lops and co"binational lo ic. 1AD;s based on 5<;!)# structure. 1AD;Ss ha/e a re ister with associated lo ic (5<;&)# "atriG). 1AD;Ss are "ostly i"ple"ented in control applications and +AC5Ss in datapath applications. -ecause o$ this course rained architecture, the ti"in is /ery $iGed in 1AD;s. +AC5 are #5( based. They need to be NdownloadedO (con$i ured) at each power!up. 1AD; are ,,A#)( based. They are acti/e at power!up i.e. as lon as theyS/e been pro ra""ed at least once. +AC5 needs boot #)( but 1AD; does not. In so"e syste"s you "i ht not ha/e enou h ti"e to boot up +AC5 then you need 1AD;R+AC5. Cenerally, the 1AD; de/ices are not /olatile, because they contain $lash or erasable #)( "e"ory in all the cases. The +AC5 are /olatile in "any cases and hence they need a con$i uration "e"ory $or workin . There are so"e +AC5s now which are non/olatile. This distinction is rapidly beco"in less rele/ant, as se/eral o$ the latest +AC5 products also o$$er "odels with e"bedded con$i uration "e"ory. The characteristic o$ non!/olatility "akes the 1AD; the de/ice o$ choice in "odern di ital desi ns to per$or" [boot loaderS $unctions be$ore handin o/er control to other de/ices not ha/in this capability. 5 ood eGa"ple is where a 1AD; is used to load con$i uration data $or an +AC5 $ro" non!/olatile "e"ory. -ecause o$ coarse! rain architecture, one block o$ lo ic can hold a bi equation and hence 1AD; ha/e a $aster input!to!output ti"in s than +AC5. 1lick here to read one ood article. @eatures +AC5 ha/e special routin resources to i"ple"ent binary counters,arith"etic $unctions like adders, co"parators and #5(. 1AD; donSt ha/e special $eatures like this. +AC5 can contain /ery lar e di ital desi ns, while 1AD; can contain s"all desi ns only.The li"ited co"pleGity (\:22M Speed0 1AD;s o$$er a sin le!chip solution with $ast pin!to!pin delays, e/en $or wide input $unctions. @se 1AD;s $or s"all desi ns, where Ninstant!onO, $ast and wide decodin , ultra!low idle power consu"ption, and desi n security are i"portant (e. ., in battery!operated equip"ent). Security0 In 1AD; once pro ra""ed, the desi n can be locked and thus "ade secure. *ince the con$i uration bitstrea" "ust be reloaded e/ery ti"e power is re!applied, desi n security in +AC5 is an issue.

 Power0 The hi h static (idle) power consu"ption prohibits use o$ 1AD; in battery!operated equip"ent. +AC5 idle power consu"ption is reasonably low, althou h it is sharply increasin in the newest $a"ilies. Design flexibility0 +AC5s o$$er "ore lo ic $leGibility and "ore sophisticated syste" $eatures than 1AD;s0 clock "ana e"ent, on!chip #5(, ;*A $unctions, ("ultipliers), and e/en on!chip "icroprocessors and (ulti!Ci abit Transcei/ers.These bene$its and opportunities o$ dyna"ic recon$i uration, e/en in the end! user syste", are an i"portant ad/anta e. @se +AC5s $or lar er and "ore co"pleG desi ns. 1lick here to read what 6ilinG has to say about it. +AC5 is suited $or ti"in circuit becauce they ha/e "ore re isters , but 1AD; is suited $or control circuit because they ha/e "ore co"binational circuit. 5t the sa"e ti"e, I$ you synthesis the sa"e code $or +AC5 $or "any ti"es, you will $ind out that each ti"in report is di$$erent. -ut it is di$$erent in 1AD; synthesis, you can et the sa"e result. 5s 1AD;s and +AC5s beco"e "ore ad/anced the di$$erences between the two de/ice types will continue to blur. While this trend "ay appear to "ake the two types "ore di$$icult to keep apart, the architectural ad/anta e o$ 1AD;s co"binin low cost, non!/olatile con$i uration, and "acro cells with predictable ti"in characteristics will likely be su$$icient to "aintain a product di$$erentiation $or the $oreseeable $uture.
#hat is the di""erence between @)>, and ,7$C?

This question is /ery popular in %D*I $resher inter/iews. It looks si"ple but a deeper insi ht into the subject re/eals the $act that there are lot o$ thinks to be understood !! *o here is the answer. @)>, !s< ,7$C ;i$$erence between 5*I1s and +AC5s "ainly depends on costs, tool a/ailability, per$or"ance and desi n $leGibility. They ha/e their own pros and cons but it is desi ners responsibility to $ind the ad/anta es o$ the each and use either +AC5 or 5*I1 $or the product. Howe/er, recent de/elop"ents in the +AC5 do"ain are narrowin down the bene$its o$ the 5*I1s. @)>, @ield )rogramable >ate ,rrays @)>, esign ,d!antages Faster time-to-market: <o layout, "asks or other "anu$acturin steps are needed $or +AC5 desi n. #eady"ade +AC5 is a/ailable and burn your H;D code to +AC5 ! ;one !! No N%= /Non %ecurring =&penses0? This cost is typically associated with an 5*I1 desi n. +or +AC5 this is not there. +AC5 tools are cheap. (so"eti"es its $ree ! Eou need to buy +AC5Z. thats all !). 5*I1 youpay hu e <#, and tools are eGpensi/e. I would say N/ery eGpensi/eOZIts in croresZ.!! Simpler design cycle: This is due to so$tware that handles "uch o$ the routin , place"ent, and ti"in . (anual inter/ention is less.The +AC5 desi n $low eli"inates the co"pleG and ti"e!consu"in $loorplannin , place and route, ti"in analysis. More predictable project cycle: The +AC5 desi n $low eli"inates potential re!spins, wa$er capacities, etc o$ the project since the desi n lo ic is already synthesiJed and /eri$ied in +AC5 de/ice. Field Reprogramability: 5 new bitstrea" ( i.e. your pro ra") can be uploaded re"otely, instantly. +AC5 can be repro ra""ed in a snap while an 5*I1 can take ]:2,222 and "ore than 9!= weeks to "ake the sa"e chan es. +AC5 costs start $ro" a couple o$ dollars to se/eral hundreds or "ore dependin on the hardware $eatures. Reusability: #eusability o$ +AC5 is the "ain ad/anta e. Arototype o$ the desi n can be i"ple"ented on +AC5 which could be /eri$ied $or al"ost accurate results so that it can be i"ple"ented on an 5*I1. I$desi n has $aults chan e the H;D code, enerate bit strea", pro ra" to +AC5 and test a ain.(odern +AC5s are recon$i urable both partially and dyna"ically. +AC5s are ood $or prototypin and li"ited production.I$ you are oin to "ake 322!722 boards it isnSt worth to "ake an 5*I1. Cenerally +AC5s are used $or lower speed, lower co"pleGity and lower /olu"e desi ns.-ut todaySs

+AC5s e/en run at :22 (HJ with superior per$or"ance. With unprecedented lo ic density increases and a host o$ other $eatures, such as e"bedded processors, ;*A blocks, clockin , and hi h!speed serial at e/er lower price, +AC5s are suitable $or al"ost any type o$ desi n. @nlike 5*I1s, +AC5Ss ha/e special hardwares such as -lock!#5(, ;1( "odules, (51s, "e"ories and hi hspeed I&), e"bedded 1A@ etc inbuilt, which can be used to et better per$or"ace. (odern +AC5s are packed with $eatures. 5d/anced +AC5s usually co"e with phase!locked loops, low!/olta e di$$erential si nal, clock data reco/ery, "ore internal routin , hi h speed, hardware "ultipliers $or ;*As, "e"ory,pro ra""able I&), IA cores and "icroprocessor cores. #e"e"ber Aower A1 (hardcore) and (icroblaJe (so$tcore) in 6ilinG and 5#( (hardcore) and <ios(so$tcore) in 5ltera. There are +AC5s a/ailable now with built in 5;1 ! @sin all these $eatures desi ners can build a syste" on a chip. <ow, dou yo really need an 5*I1 ? +AC5 sythesis is "uch "ore easier than 5*I1. In +AC5 you need not do $loor!plannin , tool can do it e$$iciently. In 5*I1 you ha/e do it. @)>, esign isad!antages Aowe consu"ption in +AC5 is "ore. Eou donSt ha/e any control o/er the power opti"iJation. This is where 5*I1 wins the race ! Eou ha/e to use the resources a/ailable in the +AC5. Thus +AC5 li"its the desi n siJe. Cood $or low quantity production. 5s quantity increases cost per product increases co"pared to the 5*I1 i"ple"entation. ,7$C ,pplication 7peci"ic $ntergrated Circiut ,7$C esign ,d!antages ost!"cost!"cost!"#ower unit costs: +or /ery hi h /olu"e desi ns costs co"es out to be /ery less. Dar er /olu"es o$ 5*I1 desi n pro/es to be cheaper than i"ple"entin desi n usin +AC5. i/es desi n $leGibility. This i/es

Speed!speed!speed!"$S% s are faster t&an FP'$: 5*I1 enoro"ous opportunity $or speed opti"iJations.

#ow power!"#ow power!"#ow power: 5*I1 can be opti"iJed $or required low power. There are se/eral low power techniques such as power atin , clock atin , "ulti /t cell libraries, pipelinin etc are a/ailable to achie/e the power tar et. This is where +AC5 $ails badly !!! 1an you think o$ a cell phone which has to be char ed $or e/ery callZ..ne/erZ..low power 5*I1s helps battery li/e lon er li$e !! In 5*I1 you can i"ple"ent analo circuit, "iGed si nal desi ns. This is enerally not possible in +AC5. In 5*I1 ;+T (;esi n +or Test) is inserted. In +AC5 ;+T is not carried out (rather $or +AC5 no need o$ ;+T !) . ,7$C esign iad!antages (ime-to-market: *o"e lar e 5*I1s can take a year or "ore to desi n. 5 ood way to shorten de/elop"ent ti"e is to "ake prototypes usin +AC5s and then switch to an 5*I1. Design %ssues: In 5*I1 you should take care o$ ;+( issues, *i nal Inte rity isuues and "any "ore. In +AC5 you donSt ha/e all these because 5*I1 desi ner takes care o$ all these. ( ;onSt $or et +AC5 isan I1 and desi ned by 5*I1 desi n en inner !!) )xpensi*e (ools: 5*I1 desi n tools are /ery "uch eGpensi/e. Eou spend a hu e a"ount o$ <#,. 7tructured ,7$C7 *tructured 5*I1s ha/e the botto" "etal layers $iGed and only the top layers can be desi ned by the custo"er. *tructured 5*I1s are custo" de/ices that approach the per$or"ance o$ todaySs *tandard 1ell 5*I1 while dra"atically si"pli$yin the desi n co"pleGity. *tructured 5*I1s o$$er desi ners a set o$ de/ices with speci$ic, custo"iJable "etal layers alon with

prede$ined "etal layers, which can contain the underlyin pattern o$ lo ic cells, "e"ory, and I&). @)>, !s< ,7$C esign @low Comparison http0&&www.GilinG.co"&co"pany& ettin started&$p a/sasic.ht" 8ther links http0&&www.controlen .co"&article&15=2>779.ht"l http0&&www.soccentral.co"&results.asp?1ate oryI;B944^,ntryI;B3:44> http0&&www.us.desi n!reuse.co"&articles&article?232.ht"l 3 co""ents Dinks to this post Dabels0 5*I1, +AC5
$n scan chains i" some "lip "lops are C!e edge triggered and remaining "lip "lops are '!e edge triggered how it beha!es?

5nswer0 +or desi ns with both positi/e and ne ati/e clocked $lops, the scan insertion tool will always route the scan chain so that the ne ati/e clocked $lops co"e be$ore the positi/e ed e $lops in the chain. This a/oids the need o$ lockup latch. +or the sa"e clock do"ain the ne ed e $lops will always capture the data just captured into the posed e $lops on the posed e o$ the clock. +or the "ultiple clock do"ains, it all depends upon how the clock trees are balanced. I$ the clock do"ains are co"pletely asynchronous, 5TAC has to "ask the recei/in $lops.
#hat is di""erence between normal bu""er and clock bu""er?

5nswer0 1lock net is one o$ the Hi h +anout <et(H+<)s. The clock bu$$ers are desi ned with so"e special property like hi h dri/e stren th and less delay. 1lock bu$$ers ha/e equal rise and $all ti"e. This pre/ents duty cycle o$ clock si nal $ro" chan in when it passes throu h a chain o$ clock bu$$ers. <or"al bu$$ers are desi ned with W&D ratio such that su" o$ rise ti"e and $all ti"e is "ini"u". They too are desi ned $or hi her dri/e stren th.
#hat is di""erence between H@N synthesis and C;7?

,nswer? H@Ns are synthesiJed in $ront end alsoZ. but at that "o"ent no place"ent in$or"ation o$ standard cells are a/ailableZ hence backend tool collapses synthesiJed H+<s. It resenthesiJes H+<s based on place"ent in$or"ation and appropriately inserts bu$$er. Tar et o$ this synthesis is to "eet delay require"ents i.e. setup and hold. +or clock no synthesis is carried out in $ront end (whyZ..????..because no place"ent in$or"ation o$ $lip!$lops ! *o synthesis wonSt "eet true skew tar ets !!) Z in backend clock tree synthesis tries to "eet NskewO tar etsZIt inserts clock bu$$ers (which ha/e equal rise and $all ti"e, unlike nor"al bu$$ers !)Z There is no skew in$or"ation $or any H+<s.
$s it possible to ha!e a +ero skew in the design?

,nswer? Theoretically it is possibleZ.! Aractically it is i"possibleZ.!! Aractically we cant reduce any delay to JeroZ. delay will eGistZ hence we try to "ake skew NequalO (or sa"e) rather than NJeroOZZnow with this opti"iJation all $lops et the clock ed e with sa"e delay relati/e to each otherZ. so /irtually we can say they are ha/in NJero skew O or skew is NbalancedO.
#hat you mean by scan chain reordering?

,nswerD? -ased on ti"in and con estion the tool opti"ally places standard cells. While doin so, i$ scan chains are detached, it can break the chain orderin (which is done by a scan insertion tool like ;+T co"piler $ro" *ynopsys) and can reorder to opti"iJe itZ. it "aintains the nu"ber o$ $lops in a chain.

,nswerE? ;urin place"ent, the opti"iJation "ay "ake the scan chain di$$icult to route due to con estion. Hence the tool will re!order the chain to reduce con estion. This so"eti"es increases hold ti"e proble"s in the chain. To o/erco"e these bu$$ers "ay ha/e to be inserted into the scan path. It "ay not be able to "aintain the scan chain len th eGactly. It cannot swap cell $ro" di$$erent clock do"ains. -ecause o$ scan chain reorderin patterns enerated earlier is o$ no use. -ut this is not a proble" as 5TAC can be redone by readin the new netlist.
8n what basis we decide the clock "requency in any design?

,nswer? There are se/eral $actors. I"portant o$ the" are0 3) $nput and output data rate 0 +or eGa"ple i$ you are desi nin any encryptor or decryptor you need "ini"u" 322 (HJ 7) )ower0 Hi her the $requency "ore the power consu"ption 8),ccuracy o" the results required0 I$ hi her accuracy is not needed #1 oscillator can be used which sa/es areaZ and e/erythin we want in co"pact siJeZ.. but #1 cant produce hi her $requency ! 9) ;echnology0 Dower the node "ore speed (also "ore powerZ.a ain trade o$$ !!)Z. how "uch $ast we want ? :) ;arget plat"orm0 Is it +AC5 or custo" 5*I1Z. naturally 5*I1 can i/e hi her clok $requencyZ but +AC5 $requency o$ operation is li"ited by se/eral other $actors
#hat is B;,>?

,nswerD? .T5C is acrony" $or N.oint Test 5ction CroupO.This is also called as I,,, 339?.3 standard $or *tandard Test 5ccess Aort and -oundary!*can 5rchitecture. This is used as one o$ the ;+T techniques. ,nswerE? .T5C (.oint Test 5ction Croup) boundary scan is a "ethod o$ testin I1s and their interconnections. This used a shi$t re ister built into the chip so that inputs could be shi$ted in and the resultin outputs could be shi$ted out. .T5C requires $our I&) pins called clock, input data, output data, and state "achine "ode control. The uses o$ .T5C eGpanded to debu in so$tware $or e"bedded "icrocontrollers. This eli"jinates the need $or in!circuit e"ulators which is "ore costly. 5lso .T5C is used in downloadin con$i uration bitstrea"s to +AC5s. .T5C cells are also known as boundary scan cells, are s"all circuits placed just inside the I&) cells. The purpose is to enable data to&$ro" the I&) throu h the boundary scan chain. The inter$ace to these scan chains are called the T5A (Test 5ccess Aort), and the operation o$ the chains and the T5A are controlled by a .T5C controller inside the chip that i"ple"ents .T5C.
,7$C esign Check -ist

7ilicon )rocess and -ibrary Characteristics What eGact process are you usin ? How "any layers can be used $or this desi n? 5re the 1ross talk <oise constraints, 6talk 5nalysis con$i uration, 1ell ,( ^ Wire ,( a/ailable? esign Characteristics What is the desi n application? <u"ber o$ cells (placeable objects)? Is the desi n %erilo or %H;D? Is the netlist $lat or hierarchical? Is there #TD a/ailable? Is there any datapath lo ic usin special datapath tools? Is the ;+T to be considered? 1an scan chains be reordered? Is "e"ory -I*T, boundary scan used on this desi n?

 5re static ti"in analysis constraints a/ailable in *;1 $or"at? Clock Characteristics How "any clock do"ains are in the desi n? What are the clock $requencies? Is there a tar et clock skew, latency or other clock require"ents? ;oes the desi n ha/e a ADD? I$ so, is it used to re"o/e clock latency? Is there any I&) cell in the $eedback path? Is the ADD used $or $requency "ultipliers? 5re there deri/ed clocks or co"pleG clock eneration circuitry? 5re there any ated clocks? I$ yes, do they use si"ple atin ele"ents? Is the ate clock used $or ti"in or power? +or ated clocks, can the atin ele"ents be siJed $or ti"in ? 5re you "uGin in a test clock or usin a .T5C clock? 5/ailable cells $or clock tree? 5re there any special clock repeaters in the library? 5re there any ,(, slew or capacitance li"its on these repeaters? How "any dri/e stren ths are a/ailable in the standard bu$$ers and in/erters? ;o any o$ the bu$$ers ha/e balanced rise and $all delays? 5ny there special require"ents $or clock distribution? Will the clock tree be shielded? I$ so, what are the shieldin require"ents? Tar et die area? ;oes the area esti"ate include power&si nal routin ? What ates&""7 has been assu"ed? <u"ber o$ routin layers? 5ny special power routin require"ents? <u"ber o$ di ital I&) pins&pads? <u"ber o$ analo si nal pins&pads? <u"ber o$ power& round pins&pads? Total nu"ber o$ pins&pads and Docation? Will this chip use a wire bond packa e? Will this chip use a $lip!chip packa e? I$ Ees, is it I&) bu"p pitch? #ows o$ bu"ps? -u"p allocation?-u"p pad layout uide? Ha/e you already done $loorplannin $or this desi n? I$ yes, is con$or"ance to the eGistin $loorplan required? What is the tar et die siJe? What is the eGpected utiliJation? Alease draw the o/erall $loorplan ? Is there an eGistin $loorplan a/ailable in ;,+? What are the nu"ber and type o$ "acros ("e"ory, ADD, etc.)? 5re there any analo blocks in the desi n? What kind o$ packa in is used? +lipchip? 5re the I&)s periphery I&) or area I&)? How "any I&)s? Is the desi n pad li"ited? Aower plannin and Aower analysis $or this desi n? 5re layout databases a/ailable $or hard "acros ? Ti"in analysis and correlatio? Ahysical /eri$ication ?

@loorplan and )ackage Characteristics

ata $nput Dibrary in$or"ation $or new library .lib $or ti"in in$or"ation C;*II or D,+ $or library cells includin any #5(s #TD in %erilo &%H;D $or"at <u"ber o$ lo ical blocks in the #TD 1onstraints $or the block in *;1 +loorplan in$or"ation in ;,+ I&) pin location (acro locations

)ower >ating

Aower Catin is e$$ecti/e $or reducin leaka e power P8Q. Aower atin is the technique wherein circuit blocks that are not in use are te"porarily turned o$$ to reduce the o/erall leaka e power o$ the chip. This te"porary shutdown ti"e can also call as Nlow power "odeO or Ninacti/e "odeO. When circuit blocks are required $or operation once a ain they are acti/ated to Nacti/e "odeO. These two "odes are switched at the appropriate ti"e and in the suitable "anner to "aGi"iJe power per$or"ance while "ini"iJin i"pact to per$or"ance. Thus oal o$ power atin is to "ini"iJe leaka e power by te"porarily cuttin power o$$ to selecti/e blocks that are not required in that "ode. Aower atin a$$ects desi n architecture "ore co"pared to the clock atin . It increases ti"e delays as power ated "odes ha/e to be sa$ely entered and eGited. The possible a"ount o$ leaka e power sa/in in such low power "ode and the ener y dissipation to enter and eGit such "ode introduces so"e architectural trade!o$$s. *huttin down the blocks can be acco"plished either by so$tware or hardware. ;ri/er so$tware can schedule the power down operations. Hardware ti"ers can be utiliJed. 5 dedicated power "ana e"ent controller is the other option. 5n eGternally switched power supply is /ery basic $or" o$ power atin to achie/e lon ter" leaka e power reduction. To shuto$$ the block $or s"all inter/al o$ ti"e internal power atin is suitable. 1()* switches that pro/ide power to the circuitry are controlled by power atin controllers. )utput o$ the power ated block dischar e slowly. Hence output /olta e le/els spend "ore ti"e in threshold /olta e le/el. This can lead to lar er short circuit current. Aower atin uses low!leaka e A()* transistors as header switches to shut o$$ power supplies to parts o$ a desi n in standby or sleep "ode. <()* $ooter switches can also be used as sleep transistors. Insertin the sleep transistors splits the chipSs power network into a per"anent power network connected to the power supply and a /irtual power network that dri/es the cells and can be turned o$$. The quality o$ this co"pleG power network is critical to the success o$ a power! atin desi n. Two o$ the "ost critical para"eters are the I#!drop and the penalties in silicon area and routin resources. Aower atin can be i"ple"ented usin cell! or cluster!based (or $ine rain) approaches or a distributed coarse! rained approach. )ower'gating parameters Aower atin i"ple"entation has additional considerations than the nor"al ti"in closure i"ple"entation. The $ollowin para"eters need to be considered and their /alues care$ully chosen $or a success$ul i"ple"entation o$ this "ethodolo y P3Q P7Q. )ower gate si+e? The power ate siJe "ust be selected to handle the a"ount o$ switchin current at any i/en ti"e. The ate "ust be bi er such that there is no "easurable /olta e (I#) drop due to the ate. Cenerally we use 86 the switchin capacitance $or the ate siJe as a rule o$ thu"b. ;esi ners can also choose between header (A!()*) or $ooter (<!()*) ate. @sually $ooter ates tend to be s"aller in area $or the sa"e switchin current. ;yna"ic power analysis tools can accurately "easure the switchin current and also predict the siJe $or the power ate. >ate control slew rate? In power atin , this is an i"portant para"eter that deter"ines the power atin e$$iciency. When the slew rate is lar e, it takes "ore ti"e to switch o$$ and switch!on the circuit and hence can a$$ect the power atin e$$iciency. *lew rate is controlled throu h bu$$erin the ate control si nal. 7imultaneous switching capacitance? This i"portant constraint re$ers to the a"ount o$ circuit that can be switched si"ultaneously without a$$ectin the power network inte rity. I$ a lar e a"ount o$ the circuit is switched si"ultaneously, the resultin Nrush currentO can co"pro"ise the power network inte rity. The circuit needs to be switched in sta es in order to pre/ent this.

 )ower gate leakage? *ince power ates are "ade o$ acti/e transistors, leaka e is an i"portant consideration to "aGi"iJe power sa/in s. @ine'grain power gating 5ddin a sleep transistor to e/ery cell that is to be turned o$$ i"poses a lar e area penalty, and indi/idually atin the power o$ e/ery cluster o$ cells creates ti"in issues introduced by inter!cluster /olta e /ariation that are di$$icult to resol/e. +ine! rain power atin encapsulates the switchin transistor as a part o$ the standard cell lo ic. *witchin transistors are desi ned by either library IA /endor or standard cell desi ner. @sually these cell desi ns con$or" to the nor"al standard cell rules and can easily be handled by ,;5 tools $or i"ple"entation. The siJe o$ the ate control is desi ned with the worst case consideration that this circuit will switch durin e/ery clock cycle resultin in a hu e area i"pact. *o"e o$ the recent desi ns i"ple"ent the $ine! rain power atin selecti/ely, but only $or the low %t cells. I$ the technolo y allows "ultiple %t libraries, the use o$ low %t de/ices is "ini"u" in the desi n (72H), so that the area i"pact can be reduced. When usin power ates on the low %t cells the output "ust be isolated i$ the neGt sta e is a hi h %t cell. )therwise it can cause the nei hborin hi h %t cell to ha/e leaka e when output oes to an unknown state due to power atin . Cate control slew rate constraint is achie/ed by ha/in a bu$$er distribution tree $or the control si nals. The bu$$ers "ust be chosen $ro" a set o$ always on bu$$ers (bu$$ers without the ate control si nal) desi ned with hi h %t cells. The inherent di$$erence between when a cell switches o$$ with respect to another, "ini"iJes the rush current durin switch!on and switch!o$$. @sually the atin transistor is desi ned as a hi h /t de/ice. 1oarse! rain power atin o$$ers $urther $leGibility by opti"iJin the power atin cells where there is low switchin acti/ity. Deaka e opti"iJation has to be done at the coarse rain le/el, swappin the low leaka e cell $or the hi h leaka e one. +ine! rain power atin is an ele ant "ethodolo y resultin in up to 326 leaka e reduction. This type o$ power reduction "akes it an appealin technique i$ the power reduction require"ent is not satis$ied by "ultiple %t opti"iJation alone. Coarse'grain power gating The coarse! rained approach i"ple"ents the rid style sleep transistors which dri/es cells locally throu h shared /irtual power networks. This approach is less sensiti/e to A%T /ariation, introduces less I#!drop /ariation, and i"poses a s"aller area o/erhead than the cell! or cluster!based i"ple"entations. In coarse! rain power atin , the power! atin transistor is a part o$ the power distribution network rather than the standard cell. There are two ways o$ i"ple"entin a coarse! rain structure0 3) #in !based 7) colu"n!based %ing'based methodology0 The power ates are placed around the peri"eter o$ the "odule that is bein switched!o$$ as a rin . *pecial corner cells are used to turn the power si nals around the corners. Column'based methodology0 The power ates are inserted within the "odule with the cells abutted to each other in the $or" o$ colu"ns. The lobal power is the hi her layers o$ "etal, while the switched power is in the lower layers. Cate siJin depends on the o/erall switchin current o$ the "odule at any i/en ti"e. *ince only a $raction o$ circuits switch at any point o$ ti"e, power ate siJes are s"aller as co"pared to the $ine! rain switches. ;yna"ic power si"ulation usin worst case /ectors can deter"ine the worst case switchin $or the "odule and hence the siJe. I# drop can also be $actored into the analysis. *i"ultaneous switchin capacitance is a "ajor consideration in coarse! rain power atin i"ple"entation. In order to li"it si"ultaneous switchin daisy chainin the ate control bu$$ers, special counters are used to selecti/ely turn on blocks o$ switches. $solation Cells Isolation cells are used to pre/ent short circuit current. 5s the na"e indicates these cells isolate power ated block $ro" the nor"ally on block. Isolation cells are specially desi ned $or low short circuit current when input is at threshold /olta e le/el. Isolation control si nals are pro/ided by power atin controller. Isolation o$ the si nals o$ a switchable "odule is essential to preser/e desi n inte rity. @sually a si"ple )# or 5<; lo ic can $unction as an output isolation de/ice. (ultiple state retention sche"es are a/ailable in practice to preser/e the state be$ore a "odule shuts down. The si"plest technique is to scan out the re ister /alues into a "e"ory be$ore shuttin down a "odule. When the "odule wakes up, the /alues are scanned back $ro" the "e"ory.

%etention %egisters When power atin is used, the syste" needs so"e $or" o$ state retention, such as scannin out data to a #5(, then scannin it back in when the syste" is reawakened. +or critical applications, the "e"ory states "ust be "aintained within the cell, a condition that requires a retention $lop to store bits in a table. That "akes it possible to restore the bits /ery quickly durin wakeup. #etention re isters are special low leaka e $lip!$lops used to hold the data o$ "ain re ister o$ the power ated block. Thus internal state o$ the block durin power down "ode can be retained and loaded back to it when the block is reacti/ated. #etention re isters are always powered up. The retention strate y is desi n dependent. ;urin the power atin data can be retained and trans$erred back to block when power atin is withdrawn. Aower atin controller controls the retention "echanis" such as when to sa/e the current contents o$ the power atin block and when to restore it back.
4ultiple ;hreshold C487 /4;C4870 Circuits

.a"es T. 'ao et al. P7Q showed (T1()* lo ic is e$$ecti/e standby leaka e control technique, but di$$icult to i"ple"ent since sleep transistor siJin is hi hly dependent on dischar e pattern within the circuit block. They showed dual %t do"ino lo ic a/oids the siJin di$$iculties and inherent per$or"ance associated with (T1()*. Hi h %t cells are used where leaka e has to be pre/ented whereas low %t cells are e"ployed where speed is o$ concern. -oth cells are e$$ecti/ely used in (T1()* technique. 4;C487 technique FDG In acti/e "ode o$ operation the hi h %t transistors are turned o$$ and the lo ic ates consistin o$ low %t transistors can operate with low switchin power dissipation and s"aller propa ation delay. In standby "ode the hi h %t transistors are turned o$$ thereby cuttin o$$ the internal low %t circuitry.
:ariable ;hreshold C487 /:;C4870

)ne o$ the e$$icient "ethods to reduce power consu"ption is to use low supply /olta e and low threshold /olta e without loosin speed per$or"ance. -ut increase in the lower threshold /olta e de/ices leads to increased sub threshold leaka e and hence "ore standby power consu"ption. %ariable Threshold 1()* (%T1()*) de/ices are one solution to this proble". In %T1()* technique threshold /olta e o$ the low threshold de/ices are /aried by applyin /ariable substrate bias /olta e $ro" a control circuitry. %T1()* technique is /ery e$$ecti/e technique to reduce the power consu"ption with so"e drawbacks with respect to "anu$acturin o$ these de/ices. %T1()* requires either twin well or triple well technolo y to achie/e di$$erent substrate bias /olta e le/els at di$$erent parts o$ the I1. The area o/erhead o$ the substrate bias control circuitry is ne li ible. P3Q
:oltage 7caling

#educin the power supply /olta e is the e$$ecti/e technique to reduce dyna"ic power with the speed penalty. 'eepin all others $actors constant i$ power scalin is scaled down propa ation delay will increase. This can be co"pensated by scalin down the threshold /olta e to the sa"e eGtent as the supply /olta e. This allows the circuit to produce the sa"e speed per$or"ance at a lower %dd. 5t the sa"e ti"e s"aller threshold /olta es lead to s"aller noise "ar in and increased leaka e current.
ynamic :oltage and @requency 7caling / :@70

We know that supply /olta e can be reduced i$ $requency o$ operation is reduced. I$ reduction in supply /olta e is quadratic then approGi"ately cubic reduction o$ power consu"ption can be achie/ed. Howe/er, it should be noted that $requency reduction slows the operation. The abo/e "entioned relation between ener y and /olta e is not always true. The authors in P3Q showed that quadratic relationship between ener y and %dd de/iates as %dd is scaled down into the sub threshold /olta e le/el. *ub threshold leaka e current increases eGponentially with the supply /olta e. *ince in sub threshold operation the on current takes the $or" o$ sub threshold current delay increases eGponentially with /olta e scalin . 5t /ery low /olta es dyna"ic power reduces quadratically. -ut the leaka e ener y increases with supply /olta e reduction since leaka e ener y is linear with the circuit delay. Hence dyna"ic and leaka e power beco"es co"parable in sub threshold /olta e re ion. 5ccordin to -o _hai et al. P3Q dyna"ic /olta e and $requency scalin is /ery popular low power technique. -ut lar er /olta e ran es does not i"pro/e power e$$iciency. They showed that $or sub threshold supply /olta es, leaka e ener y beco"es do"inant, "akin Njust in ti"e co"pletionO ener y ine$$icient. They also showed that eGtendin /olta e ran e below hal$ %dd will i"pro/e the ener y e$$iciency $or "ost processor desi ns while eGtendin this ran e to sub threshold operations is bene$icial only $or speci$ic applications. )ne o$ the i"portant points to be noted $ro" their study is ;%+* in sub threshold /olta e ran e is ne/er ener y e$$icient.

4ulti ;hreshold /4:;0 :oltage ;echnique

(ultiple threshold /olta e techniques use both Dow %t and Hi h %t cells. @se lower threshold ates on critical path while hi her threshold ates o$$ the critical path. This "ethodolo y i"pro/es per$or"ance without an increase in power. +lip side o$ this technique is that (ulti %t cells increase $abrication co"pleGity. It also len thens the desi n ti"e. I"proper opti"iJation o$ the desi n "ay utiliJe "ore Dow %t cells and hence could end up with increased power! #uchir Auri et al. P7Q ha/e discussed the desi n issues related with "ultiple supply /olta es and "ultiple threshold /olta es in the opti"iJation o$ dyna"ic and static power. They noted se/eral ad/anta es o$ (ulti %t opti"iJation. (ulti %t opti"iJation is place"ent non disturbin trans$or"ation. +ootprint and area o$ low %t and hi h %t cells are sa"e as that o$ no"inal %t cells. This enables ti"e critical paths to be swapped by low %t cells easily. +rank *ill et al. P8Q ha/e proposed a new "ethod $or assi n"ent o$ de/ices with di$$erent %th in a double %th process. They de/eloped "iGed %th ates. They showed leaka e reduction o$ 7:H. They created a library o$ D%T, "iGed %t, H%T and (ulti %t. They co"pared si"ulation results with a D%T /ersion o$ each desi n. Deaka e power dissipation decreased by a/era e =:H with "iGed %th technique co"pared to the D%T i"ple"entation. (eeta *ri/atsa/ et al. P9Q ha/e eGplored /arious ways o$ reducin leaka e power and reco""ended (ulti %t approach. They ha/e carried out analysis usin 382 n" and ?2 n" technolo y. They synthesiJed desi n with di$$erent co"bination o$ tar et library. The co"binations were Dow %t cells only, Hi h %t cells only, Hi h %t cells with incre"ental co"pile usin Dow %t library, no"inal (or re ular) %t cell and (ulti %t tar etin H/t and D/t in one o. With only Dow %t hi hest leaka e power o$ 9=? `w was obtained. With only Hi h %t cells leaka e power consu"ption was "ini"u" but ti"in was not "et (!3.38 o$ slack). With no"inal %t "oderate leaka e power /alue o$ 7=8 `w was obtained. -est results (:9 `w with ti"in "et) obtained $or synthesis tar etin H/t library and incre"ental co"pile usin D/t library. ;i$$erent low leaka e synthesis $lows are carried out by 6iaodon _han P3Q usin *ynopsys ,;5 tools are listed below0 -ow':t HI 4ulti':t "low0 This produces least cell count and least dyna"ic power. -ut produce hi hest leaka e power. It takes /ery low runti"e. Cood $or a desi n with /ery ti ht ti"in constraints 4ulti':t one pass "low0 It takes lon est runti"e and can be used in "ost o$ desi ns. High':t HI 4ulti':t "low0 Aroduce least leaka e power consu"ption but has hi h cell count and dyna"ic power. This "ethodolo y is ood $or leaka e power critical desi n. High':t HI 4ulti':t with di""erent timing constraints "low 0 This is a well balanced $low and produces second least leaka e power. This has s"aller cell count, area and dyna"ic power and shorter runti"e. This desi n is also ood $or "ost o$ desi ns. 8ptimi+ation 7trategies The tradeo$$s between the di$$erent %t cells to achie/e opti"al per$or"ance are especially bene$icial durin synthesis technolo y ate "appin and place"ent opti"iJation. The lo ic synthesis, or ate "appin phase o$ the opti"iJation process is i"ple"ented by synthesis tool, and place"ent opti"iJation is handled physical i"ple"entation tool. 7ynthesis ;urin lo ic synthesis, the desi n is "apped to technolo y ates. 5t this point in the process opti"al lo ic architectures are selected, "apped to technolo y cells, and opti"iJed $or speci$ic desi n oals. *ince a ran e o$ %t libraries are now a/ailable and choices ha/e to be "ade across architectures with di$$erent %t cells, lo ic synthesis is the ideal place to start deployin a "iG o$ di$$erent %t cells into the desi n. 7ingle')ass !s< ;wo')ass 7ynthesis Hwith multiple threshold libraries (ultiple libraries are currently a/ailable with di$$erent per$or"ance, area and power utiliJation characteristics, and synthesis opti"iJation can be achie/ed usin either one or "ore libraries concurrently. In a sin le!pass $low, "ultiple libraries can be loaded into synthesis tool prior to synthesis opti"iJation. In a two!pass $low, the desi n is initially opti"iJed usin one library, and then an incre"ental opti"iJation is carried out usin additional libraries. 5bout "ulti /t opti"iJation in his paper #uchir AuriP7Q says0 NThe "ulti!threshold opti"iJation al orith" i"ple"ented in physical synthesis is capable o$ opti"iJin se/eral %t le/els at the sa"e ti"e. Initially, the desi n is opti"iJed usin the hi her threshold /olta e library only. Then, the (ulti!%t opti"iJation co"putes the power!

per$or"ance tradeo$$ cur/e up to the "aGi"u" allowable leaka e power li"it $or the neGt lower threshold /olta e library. *ubsequently, the opti"iJation starts $ro" the "ost critical slack end o$ this power!per$or"ance cur/e and switches the "ost critical ate to neGt equi/alent lower!%t /ersion. This will increase the leaka e in the desi n beyond the "aGi"u" per"issible leaka e power. To co"pensate $or this, the al orith" picks the least critical ate $ro" the other end o$ the power!per$or"ance cur/e and substitutes it back with its hi her!%t /ersion. I$ this does not brin the leaka e power below the allowed li"it, it tra/erses $urther $ro" the cur/e ($ro" least critical towards "ore critical) substitutin ates with hi her!%t ates, until the leaka e li"it is satis$ied. Then we ju"p back to the second "ost critical cell and switch it to the lower!%t /ersion. This iteration continues until we can no lon er switch any ate with the lower /t /ersion without /iolatin the leaka e power li"it.O -ut 5"it 5 arwal et al. P:Q ha/e warned about the yield loss possibilities due to dual %t $lows. They showed that in nano!scale re i"e, con/entional dual %t desi n su$$ers $ro" yield loss due to process /ariation and /astly o/eresti"ates leaka e sa/in s since it does not consider junction -T-T (-and To -and Tunnelin ) leaka e into account. Their analysis showed the i"portance o$ considerin de/ice based analysis while desi nin low power sche"es like dual %t. Their research also showed that in scaled technolo y, statistical in$or"ation o$ both leaka e and delay helps in "ini"iJin total leaka e while ensurin yield with respect to tar et delay in dual %t desi ns. Howe/er, nonscalability o$ the present way o$ realiJin hi h %t, requires the use o$ di$$erent process options such as "etal ate work $unction en ineerin in $uture technolo ies.
4ulti :dd /:oltage0

;yna"ic power is directly proportional to power supply. Hence naturally reducin power si ni$icantly i"pro/es the power per$or"ance. 5t the sa"e ti"e ate delay increases due to the decreased threshold /olta e. Hi h /olta e can be applied to the ti"in critical path and rest o$ the chip runs in lower /olta e. )/erall syste" per$or"ance is "aintained. ;i$$erent blocks ha/in di$$erent /olta e supplies can be inte rated in *o1. This increases power plannin co"pleGity in ter"s o$ layin down the power rails and power rid structure. De/el shi$ters are necessary to inter$ace between di$$erent blocks.
4ultiple :oltage ,7$C/7oC esign? Classi"ication

(ulti /olta e desi n strate ies can be broadly classi$ied as $ollows P3Q0 7tatic :oltage 7caling /7:70? ;i$$erent but $iGed /olta e is applied to di$$erent blocks or subsyste"s o$ the *o1 desi n. 4ulti'le!el :oltage 7caling /4:70? The block or subsyste" o$ the 5*I1 or *o1 desi n is switched between two or "ore /olta e le/els. -ut $or di$$erent operatin "odes li"ited nu"bers o$ discrete /olta e le/els are supported. ynamic :oltage and @requency 7caling / :@70? %olta e as well as $requency is dyna"ically /aried as per the di$$erent workin "odes o$ the desi n so as to achie/e power e$$iciency. When hi h speed o$ operation is required /olta e is lowered to attain hi her speed o$ operation with the penalty o$ increased power consu"ption.

,dapti!e !oltage 7caling /,:70? Here /olta e is controlled usin a control loop. This is an eGtension o$ ;%+*. 4ulti :oltage esign Challenges -e!el 7hi"ters *i nals crossin $ro" one /olta e do"ain to another /olta e do"ain ha/e to be inter$aced throu h the le/el shi$ter bu$$ers which appropriately shi$t the si nal le/els. ;esi n o$ suitable le/el shi$ter is a challen in job. ;iming ,nalysis Ti"in analysis o$ the i/en desi n beco"es si"pler with the sin le /olta e as it can be per$or"ed $or sin le per$or"ance point based on the characteriJed libraries. Tools can opti"iJe the desi n $or worst case A%T (Arocess, %olta e, te"perature) conditions. This is not the case with "ulti /olta e desi ns. Dibraries should be characteriJed $or di$$erent /olta e le/els that are used in the desi n. ,;5 tool has to opti"iJe indi/idual blocks or subsyste"s and also "ultiple /olta e do"ains. This analysis beco"es co"pleG $or lar er 5*I1&*o1. @loor planning and )ower )lanning (ultiple power do"ain de"ands "ultiple power rid structure and a suitable power distribution a"on the". +or a lar er 5*I1&*o1 "ore care$ul $loor plannin and power plannin is essential. The speed in which di$$erent

power do"ains switch on or o$$ is also i"portant. 5 low /olta e power do"ain "ay acti/ate early co"pared to the hi h /olta e do"ain. (ulti /olta e desi ns pose additional board le/el co"pleGities. *eparate power supply "ay necessary to pro/ide di$$erent power le/els. 4ulti :oltage esigns? ;iming $ssues Clock 1lock Tree *ynthesis (1T*) tools should be aware o$ di$$erent power do"ains and understand the le/el shi$ters to insert the" in appropriate places. 1lock tree is routed throu h le/el shi$ters to reach di$$erent power do"ains. *i"ultaneous ti"in analysis and opti"iJation is necessary $or "ultiple /olta e do"ains. Thus 1T* beco"es "ore co"pleG in "ulti /olta e desi ns. ;iming $ssues with multi !oltage design 7tatic ;iming ,nalysis /7;,0 Ti"in analysis $or sin le /olta e desi n is easy. When it co"es to static /olta e scalin it beco"es little tou her job as analysis has to be carried out $or di$$erent /olta es. This "ethodolo y requires libraries which are characteriJed $or di$$erent /olta es used. (ulti le/el and dyna"ic /olta e scalin pose a reater challen e. +or each supply /olta e le/el or operatin point constraints are speci$ied. There can be di$$erent operatin "odes $or di$$erent /olta es. 1onstraints need not be sa"e $or all "odes and /olta es. The per$or"ance tar et $or each "ode can /ary. ,;5 tool should be capable o$ handlin all these situations si"ultaneously to carry out ti"in analysis. ;i$$erent constraints at di$$erent "odes and /olta es ha/e to be satis$ied. 4ulti :oltage esigns? )ower )lanning $ssues ,$$icient power plannin is one o$ the key concerns o$ "odern *o1 desi ns. In "ulti /olta e desi ns pro/idin power to the di$$erent power do"ains is challen in . ,/ery power do"ain requires independent local power supply and rid structure and so"e desi ns "ay e/en ha/e a separate power pad. *eparate power pad is possible in $lip!chip desi ns and power pad can be taken out near $ro" the power do"ain. )ther chips ha/e to take out the power pads $ro" the periphery which can put li"it to the nu"ber o$ power do"ains. Docal on chip /olta e re ulation is ood idea to pro/ide "ultiple /olta es to di$$erent circuits. @n$ortunately "ost o$ the di ital 1()* technolo ies are not suitable $or the i"ple"entation o$ either switched "ode o$ operation or linear /olta e re ulations. *eparate power rail structure is required $or each power do"ain. These additional power rails introduce di$$erent le/els o$ I# drop puttin li"it to the achie/able power e$$iciency.
-ow )ower esign ;echniques

(ichael 'eatin et al. P3Q lists se/eral low power techniques to tackle the dyna"ic and static power consu"ption in "odern *o1 desi ns. ;yna"ic power control techniques include clock atin , "ulti /olta e, /ariable $requency, and e$$icient circuits. Deaka e power control techniques include power atin , "ulti %t cells. 1o""on "ethods supported by ,;5 tools include clock atin , ate siJin , low power place"ent, re ister clusterin , low power 1T*, "ulti %t opti"iJation. *o"e o$ the low power techniques in use today are listed in below table. i""erent -ow )ower ;echniques FJG ;rade'o""s associated with the !arious power management techniques FEG 5bo/e table su""ariJes trade!o$$s associated with di$$erent power "ana e"ent techniques. Aower atin and ;%+* de"and lar e "ethodolo y chan e whereas "ulti /t and clock atin a$$ect least. @nless lar e leaka e opti"iJation is not necessary it is always bene$icial to o with either "ulti /t or clock atin techniques. -ased on the desi n co"pleGity and require"ents co"bination o$ any low power techniques can be adopted. (ulti /t opti"iJation alon with the power atin is $ound to be e$$icient in so"e o$ the co"pleG desi ns. 5d/anced i"pro/e"ents in the i"ple"entation (i.e. $abrication) technolo y has allowed substrate biasin techniques to be used hea/ily as it does not pose any architectural and desi n /eri$ication challen es and also pro/ides hi h leaka e reduction. 5<5D)C ,D,1T#)<I1* !!A5#T I BBBBBBBBBBBBBBBBBBBBBBBBBBB 3) How does a (os+et works. 7) What are di$$erent types o$ -.T con$i urations and when do we use the". 8) What is the di$$erence between TTD and 1()* ? 9) What is noise "ar in?

:) Which is the "ost i"portant pin the "icro!controller? =) ,Gplain about Cround -ounce and %cc *a . >) What is ,(I and what are di$$erent types o$ it. 4) )ne question on any kind o$ sensors you are aware o$ ,G0 hall sensor etc. ?) What is D%;T. 32) How do we select the correct /alue o$ decouplin capacitor (or) what is the purpose o$ usin a decouplin capacitor 33) What is parasitic capacitance ^ what are the e$$ects o$ it. 37) What is the di$$erence between "icroprocessor and "icro controller. 38) What are di$$erent types o$ "icro processor architectures 39) What is the di$$erence between by pass capacitor and decouplin capacitor 3:) How do you select an op a"p ( this can apply to other co"ponents also) 3=) *in le ended and ;i$$erential si nals. 3>) How do you decide the layer stack up on A1-. 34) Uuestions $ro"+ilter ;esi n0 5nalo and ;i ital +ilters, di$$erent types o$ $ilters. 3?) What is si nal inte rity? 72) What is "eta stability? 73) ;i$$erence between 1AD; and +AC5 77) ;i$$erence between ;;# and ;;#7 #5(. 78) What is ter"ination? What are the di$$erent types o$ ter"inations? 79) When do you need to use an heat sink and how do you decide on that? 7:) What is the di$$erence between clock bu$$er and clock dri/er? 7=) What is .itter? 7>) What is ain bandwidth product? 74) ;e$ine settlin ti"e o$ op a"p? 7?) What is slew rate o$ op a"p, de$ine co""on "ode rejection ratio and input o$$set /olta e? 82) What is the di$$erence between static response and dyna"ic response? 83) What is an inte rator and di$$erentiator? 87) ;e$ine the para"eters o$ an 5;1 or types o$ 5;1 etc? 88) What is sa"ple and hold circuit? 89) What is a co"parator?( so"e questions related to sch"itt tri er or positi/e $eed back o$ op a"p) 8:) What is +an )ut? 8=) ;i$$erent types o$ %olta e re ulators. ( Dinear, *witchin etc..) 8>) How do you create a basic delay circuit? 84) What is characteristic i"pedance? 8?) What is rin in , undershoot and o/ershoot o$ a si nal why do they occur and how to reduce the"? 92)What are the para"eters to be taken into consideration while selectin a "os$et? R