FLIP FLOP JK

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity FFJK is PORT (J,K,clk: in std_logic; Q,Qn : inout std_logic); end FFJK;

architecture Funcion of FFJK is begin process (J,K,clk) begin if(clk 'event and clk='1') then

if (J='0' and K='1') then Q <= '0'; Qn <= '1';

elsif (J='1' and K='0') then Q <= '1'; Qn <= '0';

elsif (J='0' and K='0') then Q <= Q; Qn <= Qn;

else

Q <= NOT Q;

Qn <= NOT Qn;

end if; end if; end process; end Funcion;

FLIP FLOP SR
library ieee; use ieee.std_logic_1164.all;

entity FFSR is PORT (S,R,clk: in std_logic; Q,Qn: inout std_logic); end FFSR;

architecture Funcion of FFSR is begin process (clk,R,S) begin if(clk 'event and clk='1') then if (S='0' and R='1') then Q <= '0'; Qn <= '1';

elsif(S='1' and R='0') then Q <= '1'; Qn <= '0';

elsif (S='0' and R='0') then Q <= Q; Qn <= Qn;

else Q <= '-'; Qn <= '-';

end if; end if; end process; end Funcion;

FLIP FLOP D
library ieee; use ieee.std_logic_1164.all;

entity FlipFlop is PORT (D,clk: in std_logic; Q : out std_logic); end FlipFlop;

architecture Funcionamiento of FlipFlop is begin process(clk) begin if (clk 'event and clk='1') then activo por flanco de subida Q <= D; end if; end process; end Funcionamiento; --condicn de reloj

REGISTRO DE 8 BITS
library ieee; use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity Reg8bitsD is PORT (D: in std_logic_vector (7 downto 0); clk: in std_logic; Q: out std_logic_vector (7 downto 0)); end Reg8bitsD;

architecture Funcion of Reg8bitsD is begin process (clk) begin if (clk 'event and clk='1') then Q <= D; end if; end process; end Funcion;

REGISTRO DE 4 BITS
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity Reg4bits is PORT (D: in std_logic_vector (3 downto 0); clk, clr: in std_logic; Q,nQ: inout std_logic_vector (3 downto 0)); end Reg4bits;

architecture Funcion of Reg4bits is

begin process (clk,clr) begin if (clk 'event and clk='1') then if (clr='0') then Q <="0000"; nQ <= "1111";

else

Q <= D; nQ <= NOT Q; end if; end if; end process; end Funcion;

CONTADOR DE 4 BITS
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity Contador4b is PORT (clk: in std_logic; Q: inout std_logic_vector (3 downto 0)); end Contador4b;

architecture Cuenta of Contador4b is begin process (clk) begin

if(clk 'event and clk='1') then Q <= Q+1; end if; end process; end Cuenta;

CONTADOR DE 4 BITS UP/DOWN

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity ContUD is PORT (clk,UD: in std_logic; Qn: inout std_logic_vector (3 downto 0)); end ContUD;

architecture Cuenta of ContUD is begin process (clk,UD) begin if(clk 'event and clk='1') then if (UD='0') then Qn <= Qn+1;

else Qn <= Qn-1; end if; end if; end process; end Cuenta;

CONTADOR CON RESET Y CARGA PARALELA

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity Cont is PORT (EN,CLK,CLR,LOAD: IN STD_LOGIC; P : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Q : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END Cont;

ARCHITECTURE Cuenta OF Cont IS BEGIN PROCESS(EN,CLK,CLR,LOAD) BEGIN IF(CLK 'EVENT AND CLK='1') THEN IF(CLR='1') THEN Q <= "0000";

ELSIF (EN='0' AND LOAD='0') THEN Q <= P;

ELSIF (EN='0' AND LOAD='1') THEN Q <= Q;

ELSIF (EN='1' AND LOAD='0') THEN Q <= P;

ELSE Q <= Q+1;

END IF; END IF; END PROCESS; END Cuenta;