LETTERS International Journal of Recent Trends in Engineering, Vol 2, No.

6, November 2009

Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder
Raminder Preet Pal Singh1, Parveen Kumar2, Balwinder Singh3
1

Dept ECE, Sri Sai College of Engg & Tech, Badhani, India, Email: raminder_212003@rediffmail.com 2 Dept ECE, BCET Gurdaspur (Punjab), India, Email: parveen.klair@gmail.com 3 VLSI-ES Division, Centre for development & Advanced Computing (CDAC), Mohali, India Email: balwinder_cdacmohali@yahoo.com

Abstract In this paper, design of two different array multipliers are presented, one by using carry-look-ahead (CLA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare its performance with the multiplier designed by using CLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%). Index Terms Multiplier, Carry Save Adder, Look Ahead Carry Adder, VHDL Simulation

I.

INTRODUCTION

Multipliers are most commonly used in various electronic applications e.g. Digital signal processing in which multipliers are used to perform various algorithms like FIR, IIR etc. Earlier, the major challenge for VLSI designer was to reduce area of chip by using efficient optimization techniques to satisfy MOORES law. Then the next phase is to increase the speed of operation to achieve fast calculations like, in todays microprocessors millions of instructions are performed per second. Speed of operation is one of the major constraints in designing DSP processors and todays general-purpose processors. However area and speed are two conflicting constraints. So improving speed results always in larger areas. Now, as most of todays commercial electronic products are portable like Mobile, Laptops etc. that require more battery back up. Therefore, lot of research is going on to reduce power consumption. So, in this paper it is tried to find out the best solution to achieve low power consumption, less area required and high speed for multiplier operation.

number of successive addition operation is required. Therefore one of the major components required to design a multiplier is Adder. Adders can be Ripple Carry, Carry Look Ahead, Carry Select, Carry Skip and Carry Save [1,2,3]. A lot of research work has been done to analyze performance of different fast adders. In 1996, Area-time-power tradeoffs were performed on different parallel adders [8]. Sertbas, A. and R.S. zbey in 2004, a performance analysis was carried out for classified binary adder architectures on the basis of VHDL simulations [9]. Performance analysis of multipliers is also carried out by number of researchers. Basic architecture of multiplier uses Ripple Carry Adder in the partial product lines. In 2005, Fonseca, M.; da Costa, E. et al presented a design of a Radix 2m hybrid Array multiplier to handle operands in 2s-complement form by using Carry Save Adder in each partial product lines. The results showed that the multiplier architecture with CSA gives better performance in terms of area, speed and power consumption as compared to the architecture with RCA [10]. Further in 2008, Hasan Krad and Aws Yousif AlTaie worked on performance analysis of a 32-Bit unsigned data multiplier with CLA logic and a 32-bit multiplier with a RCA using VHDL. The analysis was done on the basis of speed performance only and showed that multiplier architecture using CLA gives better result than RCA [5]. In this work, performance analysis of multiplier by using CLA logic and CSA logic is presented. The multipliers presented in this paper are all modeled by using VHDL for 32-bit unsigned data. XILINX ISE v 9.1i is used as synthesis tool and FPGA-Spartan III (XC3S250E) device is selected to get area and power reports. Modelsim XE III 6.2g is used to get timing simulation. III. CARRY LOOKAHEAD ADDER (CLA) Lookahead carry algorithm speed up the operation to perform addition, because in this algorithm carry for the next stages is calculated in advance based on input signals. In CLA, the carry propagation time is reduced to O(log2(Wd)) by using a tree like circuit to compute the carry rapidly. The CLA exploits the fact that the carry generated by a bit-position depends on the three inputs to that position. If X and Yare two inputs then if X=Y= 1, a carry is generated independently of the carry from the previous bit position and if X=Y= 0, no carry is generated. Similarly if X Y, a carry is generated if and 83

II.

PRIOR WORK

The basic principle used for multiplication is to evaluate partial products and accumulation of shifted partial products. In order to perform this operation
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LETTERS International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009
only if the previous bit-position generates a carry. C is initial carry, S and Cout are output sum and carry respectively, then Boolean expression for calculating next carry and addition is: Pi = Xi xor Yi -- Carry Propagation (1) Gi = Xi and Yi -- Carry Generation (2) Ci+1 = Gi or (Pi and Ci) -- Next Carry (3) Si = Xi xor Yi xor Ci -- Sum Generation (4) Thus, for 4-bit adder, we can extend the carry, as shown below: C1 = G0 + P0 C0 (5) C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 (6) C3 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 (7) C4 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 (8)

Figure 1: Computation flow of Carry Save Adder

V. ALGORITHM FOR ARRAY MULTIPLIER In Array multiplier, almost identical calls array is used for generation of the bit-products and accumulation. All bit-products are generated in parallel and collected through an array of full adders or any other type of adders and final adder. Array multiplier has a regular structure that simplifies the wiring and the layout. Therefore, among other multiplier structures, array multiplier takes up the least amount of area but it is also the slowest with the latency proportional to O (Wd) where Wd is the word length of the operand. Table II gives an algorithm steps and shows complete multiplication process with the help of an example. In this algorithm, S (i) represents sum of each product term, B(i)A represents each product term and P(i) represents individual bit-term of final product
TABLE II. ALGORITHM STEPS FOR MULTIPLIER OPERATION

IV. CARRY SAVE ADDER (CSA) Basically, carry save adder is used to compute sum of three or more n-bit binary numbers. Carry save adder is same as a full adder. As shown in the Figure.1, here we are computing sum of two 32-bit binary numbers, so we take 32 full adders at first stage. Carry save unit consists of 32 full adders, each of which computes single sum and carry bit based only on the corresponding bits of the two input numbers. Let X and Y are two 32-bit numbers and produces partial sum and carry as S and C as shown in the Table1: Si = Xi xor Yi (9) Ci = Xi and Yi (10) The final addition is then computed as: 1. 2. 3. Shifting the carry sequence C left by one place. Placing a 0 to the front (MSB) of the partial sum sequence S. Finally, a ripple carry adder is used to add these two together and computing the resulting sum.

TABLE I.

CARRY SAVE ADDER COMPUTATION

X: Y: Z: + S: C: + Sum:

10011 11001 01011 00001 11011 110111

ARRAY MULTIPLIER USING CLA and CSA Instead of using Ripple carry adder (RCA), here we use Carry lookahead logic and Carry save adder for adding each group of partial product terms because RCA is slowest adder among all other fast adders available. Figure 2 & 3 shows architecture of 32-bit Array multiplier using CLA and CSA respectively to add each group of partial products in parallel. The basic algorithm for multiplication process remains same as shown in table II. Only difference between them is in the way of performing addition of partial products and final addition. In case of multiplier with CSA, partial product addition is

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LETTERS International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009
carried out in Carry save form and RCA is used only in final addition. Whereas, in case of multiplier with CLA, all partial product additions as well as final addition is carried out by using carry lookahead logic.

Figure 4: Simulation Waveform for 32-Bit multiplier using Carry Lookahead Adder

Figure 2: 32-Bit Array Multiplier Using Carry Lookahead Logic

Figure 5: Simulation Waveform for 32-Bit multiplier using Carry Save Adder

VI.

RESULTS AND DISCUSSION

Figure 3: 32-Bit Array Multiplier Using Carry save Adder

I.

VI

SIMULATION RESULTS

The VHDL simulation of the two multiplier is presented in this section. For simulation Modelsim XE III 6.2g tool is used. The multipliers use 32-bit values as shown in simulation waveforms.

In this section, the results obtained from Synthesis and Simulation reports are presented. The aim of this experiment is to evaluate the performance of two Array multipliers (one by using CLA and second by using CSA) on the basis of Area required, Speed of operation and power consumption. As shown in table III, figure 6(a) and 6(b), multiplier with CSA has shown better results than with CLA. Area results are presented in terms of number of CLBs and gate count required for implementing design on FPGA. Multiplier with CSA requires less CLBs because it requires less number of full adders than multiplier with CLA. Further, simulation result shows that multiplier with CSA takes less time to generate final product than with CLA because addition is performed in parallel without waiting for the previous result in case of CSA. Similarly, result shows slight improvement in power consumption in case of multiplier using CSA. Power consumption depends on the switching activities. Therefore power consumption is directly proportional to area covered by the design on chip. Here we take dynamic power consumption for performance analysis.

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LETTERS International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009
TABLE III. SYNTHESIS AND SIMULATION RESULTS FOR AREA, DELAY AND POWER CONSUMPTION Area 32-Bit Multiplier using CLA CSA Difference %age CSA Vs CLA No. Of CLBs 1068 1023 -4.20% Gate Count 12801 12084 -5.9 % Delay (ns) 96.5 54.1 -78.30% Dynamic Power (mW) 22.1 21.8 -1.40%

CONCLUSION AND FUTURE WORK

This paper presents two different multipliers that are modeled using VHDL. According to the results obtained, implementation of CSA logic in each partial product lines improves overall performance of multiplier unit (Speed improved by 78.3%, Area reduced by 4.2% and power consumption decreased by 1.4%) as compare to CLA logic. This work is performed on 32-bit unsigned data. Therefore, it can be extended for signed multiplication.
REFERENCES

15000 10000 5000 0

12801

12084

1068 CLA

1023 CSA

CLB's

Gate Count

Figure 6(a): Hardware utilization comparison of CSA and CLA

120 100 80 60 40 20 0

96.5 54.1 22.1 21.8

CLA

CSA

Delay (ns)

Dynamic Power (mW)

Figure 6 (b): Power and delay comparison of CSA and CLA

[1] B. Parhami, Computer Arithmetic, Algorithm and Hardware Design, Oxford University Press, New York, pp. 91-119, 2000. [2] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design.2nd Edn. McGraw-Hill Higher Education, USA.ISBN: 0072499389, 2005. [3] Wakerly, J.F., 2006. Digital Design-Principles and Practices. 4th Edn. Pearson Prentice Hall, USA.ISBN: 0131733494. [4] Pong P. Chu RTL Hardware Design Using VHDL: coding for Efficiency, Portability and Scalability Wiley-IEEE Press, New Jercy, 2006 [5] Hasan Krad and Aws Yousif Al-Taie, Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL, Journal of Computer Science 4 (4): 305-308, 2008 [6] Asadi, P. and K. Navi A novel high-speed 54-54-bit multiplier, Am. J. Applied Sci., 4 (9): 666-672, 2007 [7] Z. Abid, H. El-Razouk and D.A. El-Dib, Low power multipliers based on new hybrid full adders, Microelectronics Journal, Volume 39, Issue 12, Pages 1509-1515, 2008 [8] Nagendra, C.; Irwin, M.J.; Owens, R.M.,Area-time-power tradeoffs in parallel adders, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 43, Issue 10, Page(s): 689 702, 1996 [9] Sertbas, A. and R.S. zbey, 2004. A performance analysis of classified binary adder architectures and the VHDL simulations. J. Elect. Electron. Eng., Istanbul, Turkey, 4: 1025-1030. [10] Fonseca, M.; da Costa, E. et al, Design of a Radix-2m Hybrid Array Multiplier Using Carry Save Adder integrated Circuits and System Design, 18th Symposium on Volume, Issue, 4-7 Sept. 2005 Page(s): 172-177.

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