Cadence Analog/Mixed-Signal Verification Solution Overview

Zhong Fan Engineering Director, Cadence Technology on Tour, Singapore July 25, 2013

MS Verification Challenge
Main Design Challenges Biggest Challenge in MS Verification

Cause of Silicon Re-spins

Preventable by better Verification Methodology

! Verification is biggest overall challenge in mixed-signal design ! Many of silicon re-spins could be prevented by better verification

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Key Elements of MS Verification Solution

New, Digital-like Methodology applied on analog and mixed-signal

Integrated Environment

Assertion, Coverage and Metric-Driven Methodology

Simulation
Continuous advancements in performance and features

Behavioral Modeling
Methodology, library and tools abstracting analog and mixed-signal functionality to higher level

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Virtuoso AMS Designer

Integration of Virtuoso MMSIM and IUS Simulators

VIRTUOSO MMSIM & IUS INSIDE Hierarchy Editor, Text File Configuration, Virtuoso ADE Integration

Virtuoso AMS Designer

Virtuoso UltraSim Incisive Or Virtuoso Spectre/APS

Enabling Mixed Signal Technology

Analog Solver Spectre, SPICE Verilog-A Parasitics

Shared Memory Space Verilog-AMS VHDL-AMS

Digital Solver Verilog, VHDL, SDF SystemC, e SystemVerilog

SPICE Verilog-A

Verilog(Wreal) VHDL

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Integration of Analog & Digital Verification Flows

Analog Domain
Transistor level Schematic

Mixed Signal Verification

Digital Domain

Schematic Model Generation Create Behavioral Model (RNM)

R D D

D D

D D

D A D

Validate Models to Circuit (amsDMV)

Testbench

! Behavioral models used for functional verification

! Real number models offer analog functionality at digital speeds ! Models are easily used in the Virtuoso and Incisive environments

! Pin/Bus communication abstracted to the transaction-level

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Assertion-Based Verification Introduction

!! Improved documentation !! Improved observability
!! Identifies errors where they take place instead of at the outputs !! Monitors behavior for all vectors

A A A A AA A A A A A A A A A A A A AA

AAA A A AA A A A A A A A A A A A

A A A

Spec
A A A A A A A A A AA

Top-level Integrated Design

A A A A A A A A A A

Integrated blocks

!! Improved controllability !! Improved coverage !! Verification starts sooner

AAA A A A AA

Module/block
6

ABV enables a comprehensive verification approach

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Assertions in Digital, Analog, and Mixed Signal

Why Assertions?
Assume Assert Cover

Language Support
SVA PSL OVM, IAL, e

Not New for Analog

Device checks Spectre MDL $cds_get_analog_value

Assertion Browser vs. Waveforms

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Metric Driven Verification (MDV)

Traditional, Direct Verification Methodology
Test Direct, User defined DUT (Device Under Test)

SPEC

Automatic Checking

Pass/Fail report

Verifies that circuit works for specific tests

Metric Driven Verification Methodology

Random Test Within specified constraints DUT (Device Under Test)

SPEC
Coverage and Pass/Fail Reports

Verifies that circuit works in specified constrain space Drives Verification process to achieve desired goal /coverage Reduces risk of silicon re-spin or costly product recall

Automatic Checking and Coverage Analysis

Verification Plan

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Low-power Verification for Mixed-signal Designs

! Virtuoso AMS Simulation ! Special attention needed to connecting modules in analog-digital co-simulation
! Converting corrupted digital values into electrical or real number values Vdd2
Vdd1

A D A D
iso

D
iso

iso

A
iso

! Virtuoso Power Intent Export Architect ! CPF macro model and CPF design generation from schematic & inherited connection ! Structural netlist generation for use by CLP

Virtuoso Schematic Editor

OA Verilog
Std cell Library

CPF Macro & Design

! Conformal Low Power ! LP structural and functional static checks ! Test bench independent ! Fast and comprehensive
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Conformal Low Power

Cadence low-power and mixed-signal solution

Comprehensive, interoperable, and proven flow
Incisive
Unified analog/MS simulation environment MS behavioral model generation and validation Metric-driven MS verification
(RNM, assertions, UVM-MS)

Virtuoso

CPF-aware AMS simulation Constraint-driven mixed-signal design Unified mixed-signal implementation (OA-based flows)

Encounter

VSE CPF generation, static LP verification by CLP

10

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