Synthesis DFT Physical Design Interview question Which of the following is not present in SDC ___? a.

max trans b. max cap c. max fanout d. max current density Order in Sequence a. translate b. optimi e c. mapping d. incremental synthesis When stated as !."#$m C%OS technology& what does !."# represent? a. gate length b. gate width c. technology node d. C%OS si e What 'inds of timing (iolations are in a typical timing analysis report? a. setup& hold (iolations b. slac' c. none of the abo(e d. all of the abo(e )ard macros are in the form of *. ? a. +etlist b. ,DS c. -./ d. D01 23- stands for ? a. 2egister 3ransfer -e(el b. 2egister 3ransfer -ogic c. 2andom 3echnique -ogic d. 2equired 3iming -ogic Worst case corner means? a. slow process& highest (oltage and highest temperature b. fast process& lowest (oltage and lowest temperature c. nominal process& lowest (oltage and highest temperature d. slow process& lowest (oltage and highest temperature /est case corner means? a. fast process& highest (oltage and highest temperature b. fast process& highest (oltage and lowest temperature c. slow process& highest (oltage and lowest temperature d. fast process& lowest (oltage and lowest temperature W-% is based on the statistical estimates of 2 and C based on ? a. +et 1an4out b. 2 per unit length c. C per unit length d. Statistical estimation Choose not part of the group? a. top b. segmented c. enclosed d. ports During elaboration which of the below tas's are performed? a. /uilds data structures b. .nfers registers in the design c. 5erforms higher4le(el )D- optimi ation& such as dead code remo(al d. 6ll of the abo(e Synthesis means a. Con(ersion of 23- to +etlist b. Con(ersion of +etlist to 23c. Con(ersion of 23- to ,DS d. Con(ersion of 23- to D01 What are the ad(antages of cloc' gating? a. .ncrease cloc' frequency b. sa(e cloc' power c. sa(e lea'age power d. sa(e area Which one of the below is not a semiconductor process node? a. 7! b. 89 c. 99 d. :9 .5 core types doesn;t include< a. Soft core b. )ard core c. 1irm core d. Chip core )ard cores are in the form of

a. 23- b. +etlist c. ,DS d. D01 6S.Cs ha(e less unit cost& higher speed& low power. 3rue or 1lase? a. 3rue b. 1alse c. Can;t say d. 5artially true Which is non4synthesi able here? a. 0(ent b. 0(ent trigger c. posedge d. negedge %utiple if statements with multiple branches ewsult in a. 5riority encoder b. priority decoder c. multiplexer d. 2egister 6 proper conditional assignment will infer.. a. mux b. flip flop c. xor d. encoder always =>posedge cl'? begin reg" @A in!B regC @A reg"B reg# @A regCB end What hardware is infered with abo(e code? a. " flop b. C flop c. # flop d. : flop always =>posedge cl'? begin reg" A in!B regC A reg"B reg# A regCB end What hardware is infered with abo(e code? a. " flop b. C flop c. # flop d. : flop

Which one of the below inefficient 23- coding causes latches< a. .ncomplete if4else statement b. .ncomplete case statement c. missing default in case statement d. all of the abo(e 3echnology libraries are pro(ided by a. 0D6 (endor b. 1ab house c. 1reely a(aialble d. We create libraries .lib file doesn;t consists of a. -ogic cells of (aried dri(e strength& inpus b. Cells such as 6O.& O6.& flip4flops c. ,eometrical information of metal layers d. 6ll of the abo(e synthesis strategies include a. 3op down b. /ottom up c. heirarchical d. 6ll the abo(e What are the constraints you used for the synthesis? a. 3iming b. 6rea& 5ower c. -ogical D2C d. 6ll of the abo(e What will happen to a design that is synthesi ed without any constraints? a. Wont synthesi e b. 3iming won;t meet c. Will synthesi e properly d. Won;t optmi e 3ranslate4Optimi e4%ap is nothing but ..? a. D13 b. 5hysical Design c. Synthesis d. 23- Design -ogic library has a. 3iming& 6rea& 5ower b. Operating Conditions

c. Wire -oad %odels d. 6ll the abo(e units used for time& capacitance& power& (oltage& current etc are specified in a. .lib b. spef c. .tf d. .def 5rocess (ariation accounts for a. De(iation in semiconductor fabrication process b. De(iation in synthesis c. De(iation in D13 d. De(iation in 5hysical Design 3he (oltage drop is due to **.. resistance in the supply wires a. non ero b. ero c. .nfinite d. +one of the abo(e 3he propagation delay **** with increased temperature a. .ncreases b. Decreases c. 2emains same d. Danishes )ow to impro(e synthesis optimi ation results? a. Create path groups b. 1ix hea(ily loaded nets c. Engroup hierarchies on the critical path d. 6ll of the abo(e Disad(antage of bottom4up synthesis aproach is a. %ultiple iterations required until the interfaces are stable b. Synthesi es large designs by using the di(ide4and4conquer approach c. 2equires less memory than top4down synthesis d. 6llows time budgeting .n top4down synthesis approach a. Only top le(el design is synthesi ed b. Subdesigns are synthesi ed seperately c. top le(el and subdesigns are synthesi ed seperately d. top4le(el design and all its subdesigns are synthesi ed together Constraints are generally written in **.. format a. 3C- b. 502c. SDC d. 30F3 -in'ing is the process of a. 2esol(ing references b. Enresol(ing references c. %apping to technology library d. Synthesi ing the design G6naly e; chec's for a. Semantics b. 23c. +etlist d. .5 by default& the tool assumes that the external load on the ports is a. 1inite b. .nfinite c. Hero d. +one /y default& tool assumes ***.. dri(e strength on input ports. a. 1inite b. .nfinite c. Hero d. +one W-% is based on a. +et length and 2 and C b. Designers requirements of design c. Some estimation of 2 and C gi(en by fab house d. statistical estimates of 2 and C based on I+et 1an4outJ. 0nclosed wire load model a. Eses the wire load model specified for the top le(el of the design hierarchy for all nets in a design and its sub designs. b. Eses wire load model of the smallest design that fully encloses the net is applied. c. 1or each net segment crossing heirarchy& the wire load model of the design containing the segment is used d. none Setup (iolations can be fixed by a. slowing down the cloc' b. increasing dri(e strength c. adding buffers d. 6ll of the abo(e )old (iolations can be fixed by a. increasing the delay of the data path b. decreasing the cloc' uncertainty>s'ew c. 6dding buffers d. 6ll of the abo(e D2C constraints exists in a. SDC b. -ibrary

c. Design d. +one external dri(e strength of input port can be specified using SDC a. set_dri(ing_cell b. set_dri(e c. set_load d. set_max_fanout 0stimated cloc' insertion delay is modeled using this constraint a. set_cloc'_latency b. set_cloc'_uncertainty c. set_cloc'_transition d. set_cloc'_gating_chec' Which is ha(ing highest precedence? a. 3iming constraints b. area constraints c. power constraints d. all are of highest precedence Synthesis tool performs area optimi ation only on those paths that ha(e*****. a. positi(e slac' b. negati(e slac' c. worst negati(e slac' d. total negati(e slac' ,rouping of timing paths allows a. Control the optimi ation of design b. Optimi e near4critical paths c. Optimi e all paths d. all of the abo(e 1ollowing methods can be employed to impro(e the timing of the design a. Create path groups b. 1ix hea(ily loaded nets c. Engroup hierarchies on the critical path d. all of the abo(e Disad(antage of bottom4up synthesis strategy is a. Synthesi es large designs by using the di(ide4and4conquer approach b. 2equires less memory than top4down synthesis c. 6llows time budgeting d. %ultiple iterations required until the interfaces are stable .n bottom4up strategy indi(idual subdesigns are synthesi ed *** a. seperately b. together c. one by one d. regularly .n top down synthesis strategy the top4le(el design and all its subdesigns are synthesi ed *.. a. seperately b. together c. one by one d. regularly 6rchitectural optimi ations are carried out o(er a. mapped dedign b. unmapped design c. maped netlist d. unmapped netlist 3he elaborate command automatically elaborates the top4le(el design and all of its *. a. references b. subdesigns c. instances d. all of the abo(e 6t the end of elaboration& 23- Compiler displays any ** references a. resol(ed b. connected c. unresol(ed d. unconnected .n test mode& all 11s are configured as a444444444? a. Serial shift register b. 5arellel shift register c. Serial Counter d. 2ing counter 1ault co(erage is defined as ? a. 3he ratio of +o. of detected faults to total no. of faults b. 3he ratio of +o. of faults to total no. of detected faults c. 3he ratio of +o. of detected faults to >total no. of faults Kno. of undetectable faults? d. 3he ratio of no. of undetectable faults to >total no. of faults K +o. of detected faults? Stuc' at ! modeling represents? a. Signal is permanently low b. Signal is permanently high

c. Signal is either high or low d. Signal is neither high or low .n D13 which one of the below Controllability and which one is obser(ability? a. you can dri(e it to a specified logic (alue by setting the primary inputs to specific (alues b. you can predict the response on it and propagate the fault effect to the primary outputs& where you can measure the response. c. Lou can scan the (alues from primary input to primary output d. S36 Chec's **.. delay requirements of the circuit without any input or output (ectors. a. library b. dynamic c. timing d. static Circle the incorrect one a. Dynamic 3iming 6nalysis >D36? and Static 3iming 6nalysis >S36? are not alternati(es to each other b. Can;t run on asynchronous deigns and hence Dynamic 3iming 6nalysis >D36? is the best way to analy e asynchronous designs c. 2uns faster and hence lesser analysis time d. (erifies functionality of the design by applying input (ectors and chec'ing for correct output (ectors Circle the incorrect one a. 3a'es lot of time simulate and (erify b. best suitable for designs ha(ing cloc's crossing multiple domains c. can be used for synchronous as well as asynchronous designs d. Chec's static delay requirements of the circuit without any input or output (ectors. ****. can be used for synchronous as well as asynchronous designs a. static timing analysis b. dynamic timing analysis c. spice timing analysis d. simulation timing analysis De(ice le(el timing analysis is carried out using **.. simulation a. Derilog b. S5.C0 c. Dynamic d. 3iming 6ll paths in the design may not run always in worst case delay. )ence the analysis is **.. a. pessimistic b. optimistic c. complete d. incomplete S36 ****. for logical correctness of the design a. does chec' b. does not chec' c. partially chec' d. +one of the abo(e S36 is not suitable for ****.circuits a. synchronous b. pseudo4synchonous c. asynchronous d. digital ,ate delay Afunction of ******* a. >input load & output transition?. b. >input transition time& input load?. c. >input transition time& output transition? d. >input transition time& Cload?. Cell or gate delay is calculated using **** a. -./ b. -01 c. +-D% d. D01 +-D% is highly accurate as it is deri(ed from ****. characteri ations a. S5.C0 b. CCS c. C%OS d. -./ Wire delay A function of *****. a. >2net& CnetMCpin? b. >Cnet& 2netMCpin? c. >2net& CnetM2pin? d. >2net& CloadMCpin? 6s per 0lmore delay model& doubling the length of the wire **** its delay a. Doubles b. quadruples c. )al(es d. multiples