Documente Academic
Documente Profesional
Documente Cultură
MSSP
Interrupts
Program
Data
Memory 10-bit CCP Timers
Device SRAM I/O I2C™ AUSART 8/16-bit
(# Single-Word A/D (ch) (PWM) SPI
(Bytes) (Master)
Instructions)
MCLR/VPP/RE3 1 28 RB7/PGD
RA0/AN0 2 27 RB6/PGC
RA1/AN1 3 26 RB5/AN13/CCP3
4 25 RB4/AN11
PIC16F737/767
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+ 5 24 RB3/CCP2(1)/AN9
RA4/T0CKI/C1OUT 6 23 RB2/AN8
RA5/AN4/LVDIN/SS/C2OUT 7 22 RB1/AN10
VSS 8 21 RB0/INT/AN12
OSC1/CLKI/RA7 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2(1) 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
RB5/AN13/CCP3
MCLR/VPP/RE3
RB4/AN11
RB7/PGD
RB6/PGC
RA1/AN1
RA0/AN0
QFN (28-pin)
28 27 26 25 24 23 22
RA2/AN2/VREF-/CVREF 1 21 RB3/CCP2(1)/AN9
RA3/AN3/VREF+ 2 20 RB2/AN8
RA4/T0CKI/C1OUT 3 PIC16F737 19 RB1/AN10
RA5/AN4/LVDIN/SS/C2OUT 4 18 RB0/INT/AN12
VSS 5 PIC16F767 17 VDD
OSC1/CLKI/RA7 6 16 VSS
OSC2/CLKO/RA6 7 15 RC7/RX/DT
8 9 10 11 12 13 14
RC1/T1OSI/CCP2(1)
QFN (44-pin)(1)
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC5/SDO
RC0/T1OSO/T1CKI
RC4/SDI/SDA
RC6/TX/CK
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 OSC2/CLKO/RA6
RD4/PSP4 2 32 OSC1/CLKI/RA7
RD5/PSP5 3 31 VSS
RD6/PSP6 4 30 VSS
RD7/PSP7 5
PIC16F747 29 NC
VSS 6 28 VDD
VDD 7 PIC16F777 27 RE2/CS/AN7
VDD 8 26 RE1/WR/AN6
RB0/INT/AN12 9 25 RE0/RD/AN5
RB1/AN10 10 24 RA5/AN4/LVDIN/SS/C2OUT
RB2/AN8 11 23 RA4/T0CKI/C1OUT
20
21
22
13
14
15
16
17
18
19
12 RB3/CCP2(2)/AN9
RB4/AN11
RB5/AN13/CCP3
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
NC
RB6/PGC
RB7/PGD
RA3/AN3/VREF+
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
2: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
PDIP (40-pin)
MCLR/VPP/RE3 1 40 RB7/PGD
RA0/AN0 2 39 RB6/PGC
RA1/AN1 3 38 RB5/AN13/CCP3
RA2/AN2/VREF-/CVREF 4 37 RB4/AN11
RA3/AN3/VREF+ 5 36 RB3/CCP2(1)/AN9
RA4/T0CKI/C1OUT 6 35 RB2/AN8
RA5/AN4/LVDIN/SS/C2OUT 7 34 RB1/AN10
PIC16F747/777
RE0/RD/AN5 8 33 RB0/INT/AN12
RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6
OSC1/CLKI/RA7 13 28 RD5/PSP5
OSC2/CLKO/RA6 14 27 RD4/PSP4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2(1) 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0/PSP0 19 22 RD3/PSP3
RD1/PSP1 20 21 RD2/PSP2
RC1/T1OSI/CCP2(1)
TQFP (44-pin)
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
NC
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKO/RA6
RD6/PSP6 4 30 OSC1/CLKI/RA7
RD7/PSP7 5 PIC16F747 29 VSS
VSS 6 28 VDD
VDD 7 PIC16F777 27 RE2/CS/AN7
RB0/INT/AN12 8 26 RE1/WR/AN6
RB1/AN10 9 25 RE0/RD/AN5
RB2/AN8 10 24 RA5/AN4/LVDIN/SS/C2OUT
RB3/CCP2(1)/AN9 11 23 RA4/T0CKI/C1OUT
12
13
14
15
16
17
18
19
20
21
22
RB4/AN11
MCLR/VPP/RE3
RB5/AN13/CCP3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
NC
NC
RB6/PGC
RB7/PGD
RA3/AN3/VREF+
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PORTA
13 8 RA0/AN0
Data Bus
Program Counter RA1/AN1
Standard RA2/AN2/VREF-/CVREF
Flash RA3/AN3/VREF+
Program RA4/T0CKI/C1OUT
Memory RAM
8-Level Stack File
RA5/AN4/LVDIN/
4K/8K x 14 (13-bit) SS/C2OUT
Registers
OSC2/CLKO/RA6
368 x 8
Program OSC1/CLKI/RA7
14
Bus RAM Addr(1) 9 PORTB
Addr MUX RB0/INT/AN12
Instruction Register RB1/AN10
Direct Addr 7 Indirect RB2/AN8
8 Addr RB3/CCP2(1)/AN9
RB4/AN11
FSR reg RB5/AN13/CCP3
RB7/PGD:RB6/PGC
Status reg
8 PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
3 MUX
Power-up RC2/CCP1
Timer RC3/SCK/SCL
Instruction RC4/SDI/SDA
Oscillator
Decode & Start-up Timer RC5/SDO
ALU
Control RC6/TX/CK
Power-on
Reset 8 RC7/RX/DT
Timing Watchdog
Generation Timer WREG
OSC1/CLKI Brown-out
OSC2/CLKO Reset
PORTE
VDD, VSS
MCLR/VPP/RE3
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
PORTA
13 8 RA0/AN0
Data Bus
Program Counter RA1/AN1
Standard
RA2/AN2/VREF-/CVREF
Flash
Program RA3/AN3/VREF+
Memory RAM RA4/T0CKI/C1OUT
4K/8K x 14 8-Level Stack RA5/AN4/LVDIN/
File
(13-bit) Registers SS/C2OUT
OSC2/CLKO/RA6
368 x 8 OSC1/CLKI/RA7
Program
14
Bus RAM Addr(1) 9 PORTB
Addr MUX RB0/INT/AN12
Instruction Register RB1/AN10
7 Indirect RB2/AN8
Direct Addr
8 Addr RB3/CCP2(1)/AN9
RB4/AN11
FSR reg RB5/AN13/CCP3
RB7/PGD:RB6/PGC
Status reg
8 PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
3 RC2/CCP1
Power-up MUX
RC3/SCK/SCL
Timer
RC4/SDI/SDA
Instruction Oscillator RC5/SDO
Decode & Start-up Timer RC6/TX/CK
ALU
Control RC7/RX/DT
Power-on
Reset 8 PORTD
Timing Watchdog
Generation Timer WREG
OSC1/CLKI Brown-out
OSC2/CLKO Reset RD7/PSP7:RD0/PSP0
RE1/WR/AN6
Timer0 Timer1 Timer2 10-bit A/D RE2/CS/AN7
MCLR/VPP/RE3
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
FIGURE 2-1: PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X7 DEVICES
PC<12:0>
CALL, RETURN 13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h 107h 187h
08h 88h 108h 188h
PORTE 09h TRISE 89h LVDCON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch PMDATA 10Ch PMCON1 18Ch
PIR2 0Dh PIE2 8Dh PMADR 10Dh 18Dh
TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh PMADRH 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h SSPCON2 91h
T2CON 12h PR2 92h
SSPBUF 13h SSPADD 93h
SSPCON 14h SSPSTAT 94h
CCPR1L 15h CCPR3L 95h
CCPR1H 16h CCPR3H 96h
General General
CCP1CON 17h CCP3CON 97h Purpose Purpose
RCSTA 18h TXSTA 98h Register Register
TXREG 19h SPBRG 99h 16 Bytes 16 Bytes
RCREG 1Ah 9Ah
CCPR2L 1Bh ADCON2 9Bh
CCPR2H 1Ch CMCON 9Ch
CCP2CON 1Dh CVRCON 9Dh
ADRESH 1Eh ADRESL 9Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General General General
Purpose Purpose Purpose
General Register Register Register
Purpose 80 Bytes 80 Bytes 80 Bytes
Register EFh 16Fh 1EFh
F0h 170h 1F0h
96 Bytes
Accesses Accesses Accesses
70h-7Fh 70h-7Fh 70h-7Fh
REGISTER 2-1: STATUS: ARITHMETIC STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the
two’s complement of the second operand. For rotate (RRF, RLF) instructions, this
bit is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
OSFIF CMIF LVDIF — BCLIF — CCP3IF CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Data
Memory(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REXT
OSC1 Internal
Clock
CEXT
VSS PIC16F7X7
RA6 I/O (OSC2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CONFIG1 (FOSC2:FOSC0)
Primary Oscillator
SCS<1:0> (T1OSC)
OSC2
Sleep
LP, XT, HS, RC, EC
OSC1
Secondary Oscillator Peripherals
T1OSC
MUX
T1OSO
T1OSCEN To Timer1
Enable
T1OSI Oscillator OSCCON<6:4> Internal Oscillator
8 MHz CPU
111
4 MHz
Internal 110
Oscillator 2 MHz
101
Block
Postscaler
1 MHz
MUX
100
500 kHz
8 MHz 011
31.25 kHz (INTOSC) 250 kHz
Source 010
125 kHz
001
31.25 kHz
31.25 kHz 000
WDT, FSCM
(INTRC)
4.6.4 MODIFYING THE IRCF BITS If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
The IRCF bits can be modified at any time regardless of
(31.25 kHz, IRCF<2:0> 000), there is no need for a
which clock source is currently being used as the
4 ms (approx.) clock switch delay. The new INTOSC
system clock. The internal oscillator allows users to
frequency will be stable immediately after the eight
change the frequency during run time. This is achieved
falling edges. The IOFS bit will remain set after clock
by modifying the IRCF bits in the OSCCON register.
switching occurs.
The sequence of events that occur after the IRCF bits
are modified is dependent upon the initial value of the Note: Caution must be taken when modifying the
IRCF bits before they are modified. If the INTRC IRCF bits using BCF or BSF instructions. It
(31.25 kHz, IRCF<2:0> = 000) is running and the IRCF is possible to modify the IRCF bits to a
bits are modified to any other value than ‘000’, a 4 ms frequency that may be out of the VDD
(approx.) clock switch delay is turned on. Code execu- specification range; for example:
tion continues at a higher than expected frequency VDD = 2.0V and IRCF = 111 (8 MHz).
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. This bit can be
monitored to ensure that the frequency is stable before
using the system clock in time critical applications.
FIGURE 4-7: TIMING DIAGRAM FOR XT, HS, LP, EC, EXTRC TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
TINP(1)
INTOSC
TSCS(3)
OSC1
TOSC(2)
System
Clock
TDLY(4)
SCS<1:0>
Program
Counter PC PC + 1 PC + 2 PC + 3
Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
TT1P(1)
T1OSI
TSCS(3)
OSC1
TOSC(2)
System
Clock
TDLY(4)
SCS<1:0>
Program
Counter PC PC + 1 PC + 2 PC + 3
Secondary
Oscillator
OSC1
TOST(6)
OSC2
TSCS(4)
TOSC(3)
Primary Clock
System Clock
SCS<1:0> TDLY(5)
OSTS
Program
Counter PC PC + 1 PC + 2 PC + 3
FIGURE 4-10: TIMING LP CLOCK TO PRIMARY SYSTEM CLOCK AFTER RESET (HS, XT, LP)
TT1P(1)
Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST(4)
OSC2
TEPU(3)
TOSC(2)
CPU Start-up
System Clock
Peripheral
Clock
Reset
Sleep
OSTS
Program
Counter PC 0000h 0001h 0003h 0004h 0005h
Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
OSC2 TCPU(2)
CPU Start-up
System Clock
MCLR
OSTS
Program
Counter PC 0000h 0001h 0002h 0003h 0004h
Data
Data Bus
Bus D Q
D Q VDD
VDD WR
WR PORTA
PORTA CK Q
CK Q P
P Data Latch
Data Latch
D Q
D Q I/O pin
I/O pin WR N
WR N TRISA
TRISA CK Q
CK Q
TRIS Latch VSS
TRIS Latch VSS Analog
Analog Input Mode
Input Mode
TTL
TTL Input Buffer
Input Buffer RD TRISA
RD TRISA
Q D
Q D
EN
EN
RD PORTA
RD PORTA
To Comparator
To Comparator
To A/D Module Channel Input
To A/D Module Channel Input
To A/D Module VREF+ Input
TTL
RD TRISA Input Buffer
Q D
EN
RD PORTA
To Comparator
To A/D Module VREF-
To A/D Module Channel Input
CVROE
CVREF
D Q
RA4/T0CKI/
WR N
C1OUT pin
TRISA
CK Q
TRIS Latch Analog VSS
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q D
EN
RD PORTA
D Q
RA5/AN4/LVDIN/
WR N
TRISA SS/C2OUT pin
CK Q
TRIS Latch Analog VSS
Input Mode
TTL
Buffer
RD TRISA
Q D
EN
RD PORTA
SS Input
LVDIN
(FOSC = 1x1)
CLKO (FOSC/4) From OSC1 Oscillator
1 Circuit
0
VDD
Data OSC2/CLKO
Bus D Q VDD
WR
PORTA CK Q P
Data Latch
D Q
WR N
TRISA
CK Q
TRIS Latch (FOSC = 1x1)
EMUL VSS
EMUL + FOSC = 00x,010
(FOSC = 1x0,011)
RD TRISA
TTL
Q D EMUL Buffer
EN 1
0
RD PORTA
RA6 pin
(FOSC = 1x0,011)
VDD
N
(FOSC = 1x1)
Oscillator
Circuit
VDD
(FOSC = 011)
Data
Bus OSC1/CLKI
D Q
VDD
WR
PORTA
CK Q P
Data Latch
D Q
WR N
TRISA
CK Q
TRIS Latch (FOSC = 10x) EMUL
VSS
(FOSC = 10x)
RD TRISA
Q D
NEMUL
TTL
1 Buffer
EN
0
RD PORTA
RA7 pin
(FOSC = 10x)
VDD
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG2:PCFG0 = 100, 101, 11x.
Q D
RD PORTB EN
Analog
Input Mode
RD PORTB
To INT
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
VDD
Analog RBPU (1) Weak
Input Mode P Pull-up
Data Latch
Data Bus
D Q
WR PORTB I/O pin
CK
TRIS Latch
D Q
WR TRISB CK Analog
Input Mode
TTL
RD TRISB Input Buffer
Q D
RD PORTB EN
RD PORTB
To A/D Channel Input
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
TTL
Input Buffer
RD TRISB
Q D
RD PORTB EN
RD PORTB
To A/D Channel Input
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
Analog
Input Mode
VDD
RBPU(2)
Weak
P Pull-up
I/O pin
N
VSS
TRIS Latch
D Q
WR TRISB CK Q Analog
Input Mode
TTL
Input Buffer
RD TRISB
Q D
RD PORTB EN
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
3: The SDA Schmitt Trigger conforms to the I2C™ specification.
Analog
Input Mode
RBPU(1) VDD
Weak
P Pull-up
VDD
P
Data Latch
Data Bus
D Q
N I/O pin
WR PORTB CK
TRIS Latch
VSS
D Q
WR TRISB CK
RD TRISB
Analog
Input Mode
TTL
Input Buffer
Latch
Q D
RD PORTB EN Q1
Set RBIF
Analog
Input Mode
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
Analog
Input Mode
CCP3 Output Select
CCP3 Output
1
0
VDD
RBPU(1) Weak
P Pull-up
Data Latch
Data Bus
D Q
I/O pin
WR PORTB CK
TRIS Latch
D Q
WR TRISB CK
Analog
Input Mode
TTL
RD TRISB Input Buffer
Latch
Q D
RD PORTB EN Q1
Set RBIF Analog
Input Mode
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
TTL
RD TRISB Input Buffer
Latch
Q D
RD PORTB EN Q1
Set RBIF Program Mode/ICD
From other Q D
RB7:RB4 pins RD PORTB
EN
Q3
Schmitt Trigger
Buffer
PGC
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
Port/Program Mode/ICD
PGD
1
0 VDD
RBPU(1)
Weak
P Pull-up
Data Latch
Data Bus
D Q
WR PORTB I/O pin
CK
TRIS Latch
D Q 0
WR TRISB
CK 1
TTL
RD TRISB Input Buffer
PGD DRVEN
Latch
Q D
From other Q D
RD PORTB
RB7:RB4 pins
EN
Q3
PGD
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xx00 0000 uu00 0000
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
1
FIGURE 5-16: PORTC BLOCK DIAGRAM CKE
(PERIPHERAL OUTPUT SSPSTAT<6>
OVERRIDE) RC<2:0>,
Note 1: I/O pins have diode protection to VDD and VSS.
RC<7:5> PINS 2: Port/Peripheral Select signal selects between port data
and peripheral output.
Port/Peripheral Select(2) 3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
Peripheral Data Out
0 VDD
Data Bus
D Q
WR P I/O
Port CK Q 1 pin(1)
Data Latch
D Q
WR
TRIS CK Q N
TRIS Latch
VSS
RD
TRIS
Schmitt
Trigger
Peripheral
OE(3) Q D
RD EN
Port
Peripheral Input
RD TRIS
Q D
ENEN
RD Port
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —(1) PORTE Data Direction bits 0000 1111 0000 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
09h PORTE — — — — RE3 RE2 RE1 RE0 ---- x000 ---- x000
89h TRISE IBF OBF IBOV PSPMODE —(1) PORTE Data Direction bits 0000 1111 0000 1111
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
08h PORTD Port Data Latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — RE3 RE2 RE1 RE0 ---- x000 ---- x000
89h TRISE IBF OBF IBOV PSPMODE —(2) PORTE Data Direction bits 0000 1111 0000 1111
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767; always maintain these bits clear.
2: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
Prescaler
0
M 8-bit Prescaler
WDT Timer
U
1 X 8
31.25 kHz 16-bit
Prescaler
8-to-1 MUX PS2:PS0
0 1
MUX PSA
WDT Time-out
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Timer1 can also be used to provide Real-Time Clock When the Timer1 oscillator is enabled (T1OSCEN is
(RTC) functionality to applications with only a minimal set), the RC0/T1OSO/T1CKI and RC1/T1OSI/CCP2
addition of external components and code overhead. pins become inputs. That is, the TRISB<7:6> value is
ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T1CKI
(Default High)
T1CKI
(Default Low)
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
T1OSO OSC2
C2
33 pF
Note: See the Notes with Table 7-1 for additional
information about capacitor selection. RC0
RC1
3: Since each resonator/crystal has its own Note: The special event triggers from the CCP1
characteristics, the user should consult module will not set interrupt flag bit,
the resonator/crystal manufacturer for TMR1IF (PIR1<0>).
appropriate values of external Timer1 must be configured for either Timer or Synchro-
components. nized Counter mode to take advantage of this feature.
4: Capacitor values are for design guidance If Timer1 is running in Asynchronous Counter mode,
only. this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
TOUTPS3:
TOUTPS0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
0Bh,8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TMR2 Timer2 Module Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
0Bh,8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF CMIF LVDIF — BCLIF — CCP3IF CCP2IF 000- 0-00 000- 0-00
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE CMIE LVDIE — BCLIE — CCP3IE CCP2IE 000- 0-00 000- 0-00
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
95h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu
96h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu
97h CCP3CON — — CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F737/767 devices; always maintain these bits clear.
Note 1: The 8-bit timer is concatenated with the 2-bit EQUATION 9-2:
internal Q clock or 2 bits of the prescaler to create
the 10-bit time base. PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The CCPR1L and CCP1CON<5:4> can be written to at any
frequency of the PWM is the inverse of the period time, but the duty cycle value is not latched into
(1/period). CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
FIGURE 9-4: PWM OUTPUT CCPR1H is a read-only register.
TMR2 TMR2
Reset Reset
Period
Duty Cycle
TMR2 = PR2
0Bh,8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF CMIF LVDIF — BCLIF — CCP3IF CCP2IF 000- 0-00 000- 0-00
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE CMIE LVDIE — BCLIE — CCP3IE CCP2IE 000- 0-00 000- 0-00
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 Module Register 0000 0000 0000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
95h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu
96h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu
97h CCP3CON — — CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
Additional details are provided under the individual Data to TX/RX in SSPSR
sections. TRIS bit
REGISTER 10-1: SSPSTAT: MSSP STATUS (SPI MODE) REGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
SDO SDI
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
SSPSR to after Q2
SSPBUF
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit 0
(SMP = 0)
bit 7 bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPSR to after Q2
SSPBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPSR to after Q2
SSPBUF
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA PORTA Data Direction Register 1111 1111 1111 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF and PSPIE bits are reserved on 28-pin devices; always maintain these bits clear.
SSPSR Reg
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
RC4/ MSb LSb
SDI/ receives a complete byte, it is transferred to SSPBUF
SDA and the SSPIF interrupt is set.
Match Detect Addr Match
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
SSPADD Reg
and SSPSR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS30498D-page 108
PIC16F7X7
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Cleared in software Cleared in software
From SSPIF ISR From SSPIF ISR
SSPBUF is written in software SSPBUF is written in software
CKP
DS30498D-page 109
FIGURE 10-10:
DS30498D-page 110
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
PIC16F7X7
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF (PIR1<3>) transfer
BF (SSPSTAT<0>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPADD has update of SSPADD has Clock is held low until
taken place taken place CKP is set to ‘1’
R/W = 0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
DS30498D-page 111
PIC16F7X7
10.4.4 CLOCK STRETCHING 10.4.4.3 Clock Stretching for 7-bit Slave
Both 7-bit and 10-bit Slave modes implement Transmit Mode
automatic clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching
The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the
be enabled during receives. Setting SEN will cause ninth clock, if the BF bit is clear. This occurs
the SCL pin to be held low at the end of each data regardless of the state of the SEN bit.
receive sequence. The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
10.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the
Receive Mode (SEN = 1) contents of the SSPBUF before the master device can
In 7-bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure 10-9).
ninth clock, at the end of the ACK sequence if the BF bit Note 1: If the user loads the contents of SSPBUF,
is set, the CKP bit in the SSPCON register is auto- setting the BF bit before the falling edge of
matically cleared, forcing the SCL output to be held low. the ninth clock, the CKP bit will not be
The CKP being cleared to ‘0’ will assert the SCL line cleared and clock stretching will not occur.
low. The CKP bit must be set in the user’s ISR before
reception is allowed to continue. By holding the SCL 2: The CKP bit can be set in software
line low, the user has time to service the ISR and read regardless of the state of the BF bit.
the contents of the SSPBUF before the master device
10.4.4.4 Clock Stretching for 10-bit Slave
can initiate another receive sequence. This will prevent
buffer overruns from occurring (see Figure 10-13). Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is
Note 1: If the user reads the contents of the
controlled during the first two address sequences by
SSPBUF before the falling edge of the
the state of the UA bit, just as it is in 10-bit Slave
ninth clock, thus clearing the BF bit, the
Receive mode. The first two addresses are followed
CKP bit will not be cleared and clock
by a third address sequence, which contains the high-
stretching will not occur.
order bits of the 10-bit address and the R/W bit set to
2: The CKP bit can be set in software ‘1’. After the third address sequence is performed, the
regardless of the state of the BF bit. The UA bit is not set, the module is now configured in
user should be careful to clear the BF bit Transmit mode and clock stretching is controlled by
in the ISR before the next receive the BF flag as in 7-bit Slave Transmit mode (see
sequence in order to prevent an overflow Figure 10-11).
condition.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX – 1
SCL
Master device
CKP asserts clock
Master device
deasserts clock
Write
SSPCON
DS30498D-page 114
Clock is not held low
PIC16F7X7
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the 9th clock, software
CKP will not be reset BF is set after falling
to ‘0’ and no clock edge of the 9th clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
BF (SSPSTAT<0>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
DS30498D-page 115
PIC16F7X7
10.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is
SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
The addressing procedure for the I2C bus is such that
SSPIF interrupt flag bit is set.
the first byte after the Start condition usually
determines which device will be the slave addressed by When the interrupt is serviced, the source for the inter-
the master. The exception is the general call address rupt can be checked by reading the contents of the
which can address all devices. When this address is SSPBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device specific or a general call address.
Acknowledge. In 10-bit mode, the SSPADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match and the UA
reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is
consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set and while the slave
is configured in 10-bit Address mode, then the second
The general call address is recognized when the
half of the address is not necessary, the UA bit will not
General Call Enable bit (GCEN) is enabled
be set and the slave will begin receiving data after the
(SSPCON2<7> set). Following a Start bit detect, 8 bits
Acknowledge (Figure 10-15).
are shifted into the SSPSR and the address is
compared against the SSPADD. It is also compared to
the general call address and fixed in hardware.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON<6>) ‘0’
Internal SSPM3:SSPM0
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA In Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCL
SSPM3:SSPM0 SSPADD<6:0>
SDA DX DX – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL
TBRG
S
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
occurs here. At completion of Start bit,
SDA = 1, SCL = 1
hardware clears RSEN bit
SCL (no change). and sets SSPIF
1st bit
SDA
Falling edge of ninth clock. Write to SSPBUF occurs here
End of Xmit.
TBRG
SCL TBRG
Sr = Repeated Start
DS30498D-page 124
Write to SSPCON2<0> (SEN = 1), ACKSTAT in
Start condition begins SSPCON2 = 1
From Slave, clear ACKSTAT bit (SSPCON2<6>)
PIC16F7X7
SEN = 0
Transmit Address to Slave R/W = 0 Transmitting Data or Second Half of 10-bit Address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPSTAT<0>)
PEN
R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Write to SSPCON2<4>
to start Acknowledge sequence,
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here. RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
Start XMIT. automatically
Bus master
ACK is not sent terminates
transfer
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive
at end of Acknowledge
SSPIF sequence
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
PIC16F7X7
DS30498D-page 125
PIC16F7X7
10.4.12 ACKNOWLEDGE SEQUENCE 10.4.13 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/
(SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge
pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master
are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is
erate an Acknowledge, then the ACKDT bit should be sampled low, the Baud Rate Generator is reloaded and
cleared. If not, the user should set the ACKDT bit before counts down to ‘0’. When the Baud Rate Generator
starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one
Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the
and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is sam-
SCL pin is sampled high (clock arbitration), the Baud pled high while SCL is high, the P bit (SSPSTAT<4>) is
Rate Generator counts for TBRG. The SCL pin is then set. A TBRG later, the PEN bit is cleared and the SSPIF
pulled low. Following this, the ACKEN bit is automatically bit is set (Figure 10-24).
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 10-23). 10.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
10.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the
If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t
sequence is in progress, then WCOL is set and the occur).
contents of the buffer are unchanged (the write doesn’t
occur).
SCL 8 9
SSPIF
Cleared in
Set SSPIF at the end Cleared in software
of receive software Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock to setup Stop condition
Data changes SDA line pulled low Sample SDA. While SCL is high,
while SCL = 0 by another source data doesn’t match what is driven
by the master. Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module resets into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF
SDA = 0, SCL = 1
TBRG TBRG
SDA
FIGURE 10-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF ‘0’
SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF in software
SDA
SCL
RSEN
BCLIF
Cleared in software
S ‘0’
SSPIF ‘0’
TBRG TBRG
SDA
SCL
S ‘0’
SSPIF
PEN
BCLIF
P ‘0’
SSPIF ‘0’
SDA
PEN
BCLIF
P ‘0’
SSPIF ‘0’
REGISTER 11-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Data Bus
TXIF TXREG Register
TXIE
8
MSb LSb
(8) 0 Pin Buffer
and Control
TSR Register RC6/TX/CK pin
Interrupt
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG AUSART Transmit Data Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
RCIF 8
Interrupt
RCIE Data Bus
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG AUSART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
SPEN
Enable
RX9 Load of
Receive
ADDEN Buffer
RX9
ADDEN
RSR<8> 8
Interrupt RCIF
Data Bus
RCIE
Load RSR
bit 8 = 0, Data Byte bit 8 = 1, Address Byte Word 1
RCREG
Read
RCIF
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
Load RSR
bit 8 = 1, Address Byte bit 8 = 0, Data Byte Word 1
RCREG
Read
RCIF
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG AUSART Receive Register 0000 0000 0000 0000
(1)
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
0Bh, 8Bh, INTCO GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh N
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG AUSART Transmit Register 0000 0000 0000 0000
(1)
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
RC7/RX/DT
bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
pin
Word 1 Word 2
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
Note: Sync Master mode, SPBRG = 0. Continuous transmission of two 8-bit words.
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG AUSART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG AUSART Transmit Data Register 0000 0000 0000 0000
(1)
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG AUSART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000 A A A A A A A A A A A A A A
0001 A A A A A A A A A A A A A A
0010 D A A A A A A A A A A A A A
0011 D D A A A A A A A A A A A A
0100 D D D A A A A A A A A A A A
0101 D D D D A A A A A A A A A A
0110 D D D D D A A A A A A A A A
0111 D D D D D D A A A A A A A A
1000 D D D D D D D A A A A A A A
1001 D D D D D D D D A A A A A A
1010 D D D D D D D D D A A A A A
1011 D D D D D D D D D D A A A A
1100 D D D D D D D D D D D A A A
1101 D D D D D D D D D D D D A A
1110 D D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D D
Legend: A = Analog input, D = Digital I/O
Note: AN5 through AN7 are only available on the 40-pin product variant (PIC16F747 and
PIC16F777).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
The analog reference voltage is software selectable A device Reset forces all registers to their Reset state.
to either the device’s positive and negative supply This forces the A/D module to be turned off and any
voltage (VDD and VSS) or the voltage level on the conversion in progress is aborted.
RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D converter can be
The A/D converter has a unique feature of being able configured as an analog input or as a digital I/O. The
to operate while the device is in Sleep mode. To ADRESH and ADRESL registers contain the result of
operate in Sleep, the A/D conversion clock must be the A/D conversion. When the A/D conversion is com-
derived from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH/ADRESL
The output of the sample and hold is the input into the registers, the GO/DONE bit (ADCON0 register) is
converter which generates the result via successive cleared and A/D Interrupt Flag bit, ADIF, is set. The block
approximation. diagram of the A/D module is shown in Figure 12-1.
1101
AN13
1100
AN12
1011
AN11
S
S
0011
AN3/VREF+
0010
VIN AN2/VREF-
VDD 0000
AN0
A/D
Converter
VREF+
(Reference
Voltage)
VCFG<1:0>
VREF-
(Reference
Voltage)
VSS
VCFG<1:0>
= TAMP + TC + TCOFF
= 2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
TC = CHOLD (RIC + RSS + RS) In(1/2047)
= -120 pF (1 k + 7 k + 10 k) In(0.0004885)
= 16.47 s
TACQ = 2 s + 16.47 s + [(50°C – 25C)(0.05 s/C)
= 19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
CHOLD
VA CPIN ILEAKAGE = DAC Capacitance
5 pF VT = 0.6V = 120 pF
±500 nA
VSS
TABLE 12-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (F))
AD Clock Source (TAD)
Maximum Device Frequency
Operation ADCS2:ADCS1:ADCS0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
FIGURE 12-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts
Time (Holding capacitor is disconnected)
0Bh,8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF CMIF LVDIF — BCLIF — CCP3IF CCP2IF 000- 0-00 000- 0-00
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE CMIE LVDIE — BCLIE — CCP3IE CCP2IE 000- 0-00 000- 0-00
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 000 0000 0000
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
09h PORTE(2) — — — — RE3(3) RE2 RE1 RE0 ---- x000 ---- x000
89h TRISE(2) IBF OBF IBOV PSPMODE —(3) PORTE Data Direction bits 0000 1111 0000 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
2: These registers are reserved on the PIC16F737/767 devices.
3: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RA3/AN3/ A VIN+ C1 Off (Read as ‘0’) RA3/AN3/ D VIN+ C1 Off (Read as ‘0’)
VREF+ VREF+
Two Common Reference Comparators Two Common Reference Comparators with Outputs
CM2:CM0 = 100 CM2:CM0 = 101
RA0/AN0 A VIN- RA0/AN0 A VIN-
One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 001 CM2:CM0 = 110
A VIN- RA0/AN0 A
RA0/AN0 CIS = 0 VIN-
RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A CIS = 1
VREF+ VIN+ C1 C1OUT
VREF+
RA4/T0CKI/C1OUT A
RA1/AN1
CIS = 0 VIN-
RA2/AN2/ A CIS = 1
D VIN- VREF-/CVREF VIN+ C2 C2OUT
RA1/AN1
VIN+ C2 Off (Read as ‘0’)
RA2/AN2/ D CVREF From Comparator
VREF-/CVREF
VREF Module
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
MULTIPLEX
+ -
CxINV
To RA4 or
RA5 pin
Bus Q D
Data
Read CMCON EN
Set
CMIF Q D
bit From
other EN
Comparator
CL Read CMCON
Reset
VT = 0.6V RIC
RS < 10K
AIN
CPIN ILEAKAGE
VA VT = 0.6V ±500 nA
5 pF
VSS
Legend: CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Dh PIR2 OSFIF CMIF LVDIF — BCLIF — CCP3IF CCP2IF 000- 0-00 000- 0-00
8Dh PIE2 OSFIE CMIE LVDIE — BCLIE — CCP3IE CCP2IE 000- 0-00 000- 0-00
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
VDD
16 Stages
CVREN
8R R R R R
8R CVRR
RA2/AN2/VREF-/CVREF
CVROE
CVR3
CVREF CVR2
Input to 16:1 Analog MUX
CVR1
Comparator
CVR0
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
External
Reset
MCLR/VPP/RE3 pin
Sleep
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Detect BOREN
BORSEN S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter R Q
OSC1/
CLKI pin
PWRT
INTRC(1) 11-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: This is the 32 kHz INTRC oscillator. See Section 4.0 “Oscillator Configurations” for more information.
VA
VB
Voltage
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TA TB
Time
VDD LVDIN
LVD Control
Register
16-to-1 MUX
LVDIF
The LVD module has an additional feature that allows pin, LVDIN (Figure 15-5). This gives users flexibility
the user to supply the sense voltage to the module because it allows them to configure the Low-Voltage
from an external source. This mode is enabled when Detect interrupt to occur at any voltage in the valid
bits LVDL3:LVDL0 are set to ‘1111’. In this state, the operating range.
comparator input is multiplexed from the external input
FIGURE 15-5: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD Control
Register
LVDIN
16-to-1 MUX
LVDEN
Externally Generated
Trip Point
LVD
LVDEN
BODEN
EN
BGAP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
VDD
VLVD
LVDIF
Enable LVD
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
VDD
MCLR
Internal POR
TPWRT
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
TPWRT
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
TPWRT
OST Time-out
Internal Reset
5V
VDD 0V 1V
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
PSPIF(1)
PSPIE(1)
OSFIF
OSFIE
BCLIF
BCLIE
ADIF
ADIE Wake-up (If in Sleep mode)
RCIF TMR0IF
RCIE TMR0IE
INT0IF
TXIF
INT0IE
TXIE Interrupt to CPU
RBIF
SSPIF RBIE
SSPIE
PEIE
CCP1IF
CCP1IE
GIE
CCP2IF
CCP2IE
CCP3IF
CCP3IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CMIF
CMIE
The WDT derives its time base from the 31.25 kHz The SWDTEN bit is in the WDTCON register. When the
INTRC; therefore, the accuracy of the 31.25 kHz will be WDTEN bit in the Configuration Word Register 1 is set,
the same accuracy for the WDT time-out period. the SWDTEN bit has no effect. If WDTEN is clear, then
the SWDTEN bit can be used to enable and disable the
The value of WDTCON is ‘---0 1000’ on all Resets. WDT. Setting the bit will enable it and clearing the bit
This gives a nominal time base of 16.38 ms which is will disable it.
compatible with the time base generated with previous
PIC16 microcontroller versions. The PSA and PS<2:0> bits (OPTION_REG) have the
same function as in previous versions of the PIC16
Note: When the OST is invoked, the WDT is held family of microcontrollers.
in Reset because the WDT ripple counter
is used by the OST to perform the oscilla-
tor delay count. When the OST count has
expired, the WDT will begin counting (if
enabled).
Postscaler
1
16-bit Programmable Prescaler WDT
PSA
PS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
2007h Configuration BORV0 BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 1111 1111 1111 1111
bits(1)
105h WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 15-1 for operation of these bits.
CPU Start-up
Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INTRC
OSC1
TOST
OSC2
System Clock
Sleep
OSTS
Program PC 0000h 0001h 0003h 0004h 0005h
Counter
Sample Clock
(488 Hz)
System Oscillator
Clock Failure
Output
CM Output
(Q)
Failure
Detected
OSCFIF
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
INT pin
INTF Flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>) Processor in
Sleep
INSTRUCTION FLOW
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction
Fetched Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Instruction Dummy Cycle Dummy Cycle
Executed Inst(PC – 1) Sleep Inst(PC + 1) Inst(0004h)
Note: Additional information on the mid-range instruction set is available in the “PIC® Mid-Range MCU Family
Reference Manual” (DS33023).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
6.0V
5.5V
5.0V
4.5V
Voltage
4.0V
3.5V
3.0V
2.5V
2.0V
16 MHz 20 MHz
Frequency
6.0V
5.5V
5.0V
4.5V
Voltage
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz 10 MHz
Frequency
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Min Typ Max Units Conditions
No.
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC16LF7X7 -2 ±1 2 % +25°C
-5 — 5 % -10°C to +85°C VDD = 2.7V-3.3V
-10 — 10 % -40°C to +85°C
PIC16F7X7 -2 ±1 2 % +25°C
-5 — 5 % -10°C to +85°C
VDD = 4.5V-5.5V
-10 — 10 % -40°C to +85°C
Extended devices -15 — 15 % -40°C to +125°C
INTRC Accuracy @ Freq = 31 kHz(2)
PIC16LF7X7 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7V-3.3V
PIC16F7X7 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5V-5.5V
Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC is used to calibrate INTOSC.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV
D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio* 55 — — dB
300 TRESP Response Time(1)* — 150 400 ns PIC16F7X7
300A 600 ns PIC16LF7X7
301 TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from
VSS to VDD.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — — 1/4 LSb Low Range (CVRR = 1)
— — 1/2 LSb High Range (CVRR = 0)
D312 VRUR Unit Resistor Value (R)* — 2k —
310 TSET Settling Time(1)* — — 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transition from ‘0000’ to ‘1111’.
VDD
(LVDIF can be
VLVD cleared in software)
(LVDIF set by hardware)
LVDIF
Param
Symbol Characteristic Min Typ† Max Units Conditions
No.
D420 VLVD LVD Voltage on VDD LVDL<3:0> = 0000 N/A N/A N/A V Reserved
Transition High-to-Low LVDL<3:0> = 0001 1.96 2.06 2.16 V T 25C
LVDL<3:0> = 0010 2.16 2.27 2.38 V T 25C
LVDL<3:0> = 0011 2.35 2.47 2.59 V T 25C
LVDL<3:0> = 0100 2.43 2.56 2.69 V
LVDL<3:0> = 0101 2.64 2.78 2.92 V
LVDL<3:0> = 0110 2.75 2.89 3.03 V
LVDL<3:0> = 0111 2.95 3.1 3.26 V
LVDL<3:0> = 1000 3.24 3.41 3.58 V
LVDL<3:0> = 1001 3.43 3.61 3.79 V
LVDL<3:0> = 1010 3.53 3.72 3.91 V
LVDL<3:0> = 1011 3.72 3.92 4.12 V
LVDL<3:0> = 1100 3.92 4.13 4.34 V
LVDL<3:0> = 1101 4.11 4.33 4.55 V
LVDL<3:0> = 1110 4.41 4.64 4.87 V
Legend: Shading of rows is to assist in readability of the table.
† Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
VDD/2
RL
CL pin CL
pin
VSS VSS
RL = 464
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F737/767 devices.
OSC1
1 3 3 4 4
2
CLKO
Q4 Q1 Q2 Q3
OSC1
10 11
CLKO
13 18 12
14 19 16
I/O pin
(Input)
17 15
20, 21
Note: Refer to Figure 18-4 for load conditions.
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
VDD VBOR
35
TABLE 18-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
RA4/T0CKI/C1OUT
40 41
42
RC0/T1OSO/T1CKI
45 46
47 48
TMR0 or TMR1
41* TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — — ns Must also meet
With prescaler 10 — — ns parameter 42
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50 51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53 54
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
65
RD7/PSP7:RD0/PSP0
62
64
63
Note: Refer to Figure 18-4 for load conditions.
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
74
73
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
82
SS
70
SCK
83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb In bit 6 - - - -1 LSb In
74
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
SDA
Out
RC6/TX/CK
pin 121
121
RC7/RX/DT
pin
120
122
RC6/TX/CK
pin 125
RC7/RX/DT
pin
126
ADIF
GO DONE
Sampling Stopped
SAMPLE
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
130 TAD A/D Clock Period PIC16F7X7 1.6 — — s TOSC based, VREF 3.0V
PIC16LF7X7 3.0 — — s TOSC based, VREF 2.0V
PIC16F7X7 2.0 4.0 6.0 s A/D RC mode
PIC16LF7X7 3.0 6.0 9.0 s A/D RC mode
131 TCNV Conversion Time (not including S/H time) — 12 TAD
(Note 1)
132 TACQ Acquisition Time (Note 2) 40 — s
FIGURE 19-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
7
5 5.0V
4.5V
4
IDD (mA)
4.0V
3 3.5V
3.0V
2
2.5V
2.0V
0
4 6 8 10 12 14 16 18 20
FOSC (MHz)
FIGURE 19-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
8
4.5V
5
4.0V
IDD (mA)
4
3.5V
3.0V
3
2.5V
2 2.0V
0
4 6 8 10 12 14 16 18 20
FOSC (MHz)
1.2 4.5V
4.0V
1.0
IDD (mA)
3.5V
0.8 3.0V
2.5V
0.6
2.0V
0.4
0.2
0.0
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
FIGURE 19-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
2.5
5.5V
5.0V
1.5
4.5V
IDD (mA)
4.0V
3.5V
1.0
3.0V
2.5V
2.0V
0.5
0.0
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
50 5.0V
4.5V
40
IDD (A)
4.0V
3.5V
30
3.0V
2.5V
20
2.0V
10
0
20 30 40 50 60 70 80 90 100
FOSC (kHz)
FIGURE 19-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
120
4.5V
80
4.0V
IDD (A)
60 3.5V
3.0V
2.5V
40
2.0V
20
0
20 30 40 50 60 70 80 90 100
FOSC (kHz)
4.5V
1.0
4.0V
IDD (mA)
0.8 3.5V
3.0V
0.6
2.5V
0.4 2.0V
0.2
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
FOSC (MHz)
FIGURE 19-8: MAXIMUM IDD vs. VDD, -40C TO +125C, 1 MHz TO 8 MHz
(RC_RUN MODE, ALL PERIPHERALS DISABLED)
4.5
3.5
5.0V
3.0 4.5V
4.0V
2.5
IDD (mA)
3.5V
2.0
3.0V
1.5
2.5V
1.0 2.0V
0.5
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
FOSC (MHz)
35.0
Max (+70°C)
30.0
25.0
IDD (A)
Typ (+25°C)
20.0
15.0
10.0
5.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 19-10: IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED)
100
Max (125°C)
10
Max (85°C)
1
IPD (A)
0.1
0.01
Typ (25°C) Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.001
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
4.5
5.1 kOhm
3.5
3.0
Freq (MHz)
2.5
10 kOhm
2.0
1.5
1.0
0.5
100 kOhm
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
2.5
2.0
3.3 kOhm
1.5
Freq (MHz)
5.1 kOhm
1.0
10 kOhm
0.5
100 kOhm
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
0.9
0.8
3.3 kOhm
0.7
0.6
5.1 kOhm
Freq (MHz)
0.5
0.4
10 kOhm
0.3
0.2
0.1
100 kOhm
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
5.0
4.5
3.5
3.0
Typ (+25°C)
IPD (A)
2.5
2.0
1.5
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
18
14
12
IWDT (A)
10
Max (-40°C to +125°C)
6
Max (-40°C to +85°C)
2
Typ (25°C)
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 19-16: IPD LVD vs. VDD (SLEEP MODE, LVD = 2.00V-2.12V)
50
45
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
40 Minimum: mean – 3 (-40°C to +125°C)
Max (+125°C)
35
Max (+85°C)
30
IPD (A)
Typ (+25°C)
25
20
15
10
Low-Voltage Detection Range
5
30
25
Typ (+25°C)
IPD (A)
20
15
10
5
Device is Operating
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 19-18: IPD A/D, -40C TO +125C (SLEEP MODE, A/D ENABLED – NOT CONVERTING)
12
Max
(-40°C to +125°C)
8
IPD (A)
Max
(-40°C to +85°C)
2
Typ (+25°C)
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
5.5
5.0
4.5
4.0
Max
3.5
Typ (25°C)
3.0
VOH (V)
2.5
Min
2.0
0.5
0.0
0 5 10 15 20 25
IOH (-mA)
FIGURE 19-20: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
3.5
2.5
Max
2.0
VOH (V)
Typ (25°C)
1.5
Min
1.0
0.5
0.0
0 5 10 15 20 25
IOH (-mA)
1.0
0.9
Max (125°C)
Typical: statistical mean @ 25°C
0.8 Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.7
0.5
Typ (25°C)
0.4
0.3
Min (-40°C)
0.2
0.1
0.0
0 5 10 15 20 25
IOL (-mA)
FIGURE 19-22: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
3.0
Max (125°C)
2.5 Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2.0
VOL (V)
1.5
Max (85°C)
1.0
Typ (25°C)
0.5
Min (-40°C)
0.0
0 5 10 15 20 25
IOL (-mA)
1.5
1.4
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
1.3
VTH Max (-40°C)
1.2
1.1
VTH Typ (25°C)
VIN (V)
1.0
0.8
0.7
0.6
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 19-24: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
4.0
2.5
2.0
1.5
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
3.5
VIH Max
Typical: statistical mean @ 25°C
3.0 Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2.5
2.0
V
VIL Max
ILMax
VIN (V)
VIH Min
1.5
1.0
VIL Min
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 19-26: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C)
3.5
-40°C
-40C
Differential or Integral Nonlinearity (LSB)
+25°C
25C
2.5
+85°C
85C
2
1.5
0.5
+125°C
125C
0
2 2.5 3 3.5 4 4.5 5 5.5
VDD and VREFH (V)
2.5
Differential or Integral Nonlinearilty (LSB)
1.5
Max
Max (-40°C
(-40C toto125C)
+125°C)
Typ
Typ (+25°C)
(25C)
0.5
0
2 2.5 3 3.5 4 4.5 5 5.5
VREFH (V)
PIC16F737-I/SP
0410017 e3
XXXXXXXXXXXXXXXXXXXX PIC16F737-I/SO
XXXXXXXXXXXXXXXXXXXX 0410017 e3
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F737
-I/SS e3
0410017
PIN 1 PIN 1
XXXXXXXX 16F737
-I/ML e3
XXXXXXXX 0410017
YYWWNNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXXXXXXXXXXXXXX PIC16F777-I/P
XXXXXXXXXXXXXXXXXX 0410017 e3
XXXXXXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX PIC16F777
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 0410017
YYWWNNN
PIN 1 PIN 1
XXXXXXXXXXX
XXXXXXXXXXX PIC16F777
-I/ML e3
XXXXXXXXXXX 0410017
YYWWNNN
/HDG6NLQQ\3ODVWLF'XDO,Q/LQH63±PLO%RG\>63',3@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
NOTE 1
E1
1 2 3
A A2
L c
A1 b1
b e eB
8QLWV ,1&+(6
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
7RSWR6HDWLQJ3ODQH $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
%DVHWR6HDWLQJ3ODQH $ ± ±
6KRXOGHUWR6KRXOGHU:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
7LSWR6HDWLQJ3ODQH /
/HDG7KLFNQHVV F
8SSHU/HDG:LGWK E
/RZHU/HDG:LGWK E
2YHUDOO5RZ6SDFLQJ H% ± ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
/HDG3ODVWLF6KULQN6PDOO2XWOLQH66±PP%RG\>6623@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D
N
E
E1
1 2
b
NOTE 1
e
c
A A2
φ
A1
L1 L
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ± ±
2YHUDOO:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
)RRW/HQJWK /
)RRWSULQW / 5()
/HDG7KLFNQHVV F ±
)RRW$QJOH
/HDG:LGWK E ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@
ZLWKPP&RQWDFW/HQJWK
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D D2
EXPOSED
PAD
E
b
E2
2 2
1 1 K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW
A3 A1
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $
6WDQGRII $
&RQWDFW7KLFNQHVV $ 5()
2YHUDOO:LGWK ( %6&
([SRVHG3DG:LGWK (
2YHUDOO/HQJWK ' %6&
([SRVHG3DG/HQJWK '
&RQWDFW:LGWK E
&RQWDFW/HQJWK /
&RQWDFWWR([SRVHG3DG . ± ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
3DFNDJHLVVDZVLQJXODWHG
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@
ZLWKPP&RQWDFW/HQJWK
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
/HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
NOTE 1
E1
1 2 3
A A2
L c
b1
A1
b e eB
8QLWV ,1&+(6
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
7RSWR6HDWLQJ3ODQH $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $ ±
%DVHWR6HDWLQJ3ODQH $ ± ±
6KRXOGHUWR6KRXOGHU:LGWK ( ±
0ROGHG3DFNDJH:LGWK ( ±
2YHUDOO/HQJWK ' ±
7LSWR6HDWLQJ3ODQH / ±
/HDG7KLFNQHVV F ±
8SSHU/HDG:LGWK E ±
/RZHU/HDG:LGWK E ±
2YHUDOO5RZ6SDFLQJ H% ± ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
/HDG3ODVWLF7KLQ4XDG)ODWSDFN37±[[PP%RG\PP>74)3@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D
D1
E
e
E1
N
b
NOTE 1 1 2 3
NOTE 2
A α
c φ
β A1 A2
L L1
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI/HDGV 1
/HDG3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ±
)RRW/HQJWK /
)RRWSULQW / 5()
)RRW$QJOH
2YHUDOO:LGWK ( %6&
2YHUDOO/HQJWK ' %6&
0ROGHG3DFNDJH:LGWK ( %6&
0ROGHG3DFNDJH/HQJWK ' %6&
/HDG7KLFNQHVV F ±
/HDG:LGWK E
0ROG'UDIW$QJOH7RS
0ROG'UDIW$QJOH%RWWRP
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
&KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D D2
EXPOSED
PAD
E2
b
2 2
1 1
N N K
NOTE 1 L
A3 A1
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $
6WDQGRII $
&RQWDFW7KLFNQHVV $ 5()
2YHUDOO:LGWK ( %6&
([SRVHG3DG:LGWK (
2YHUDOO/HQJWK ' %6&
([SRVHG3DG/HQJWK '
&RQWDFW:LGWK E
&RQWDFW/HQJWK /
&RQWDFWWR([SRVHG3DG . ± ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
3DFNDJHLVVDZVLQJXODWHG
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.