JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY::HYDERABAD III YEAR B.Tech. ECE II Semester (EC !!

!"#$ VLSI DESIGN UNIT I INTRODUCTION : Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Oxidation, Lithogra hy, !i""usion, Ion i# lantation, Metallisation, $nca sulation, Pro%e testing, Integrated &esistors and Ca acitors' UNIT II BASIC ELECTRICAL %RO%ERTIES : Basic $lectrical Pro erties o" MOS and BiCMOS Circuits( Ids-)ds relationshi s, MOS transistor threshold )oltage, g#, gds, "igure o" #erit *o+ Pass transistor, NMOS In,erter, )arious ull u s, CMOS In,erter analysis and design, Bi-CMOS In,erters' UNIT III VLSI CIRCUIT DESIGN %ROCESSES : )LSI !esign -lo., MOS Layers, Stic/ !iagra#s, !esign &ules and Layout, 0 1# CMOS !esign rules "or .ires, Contacts and Transistors Layout !iagra#s "or NMOS and CMOS In,erters and 2ates, Scaling o" MOS circuits, Li#itations o" Scaling' UNIT IV GATE LEVEL DESIGN : Logic 2ates and Other co# lex gates, S.itch logic, 3lternate gate circuits, Basic circuit conce ts, Sheet &esistance &S and its conce t to MOS, 3rea Ca acitance 4nits, Calculations - 5 - !elays, !ri,ing large Ca aciti,e Loads, 6iring Ca acitances, -an-in and "an-out, Choice o" layers UNIT V SUBSYSTE& DESIGN : Su%syste# !esign, Shi"ters, 3dders, 3L4s, Multi liers, Parity generators, Co# arators, 7ero8One !etectors, Counters, 9igh !ensity Me#ory $le#ents' UNIT VI SE&ICONDUCTOR INTEGRATED CIRCUIT DESIGN : PL3s, -P23s, CPL!s, Standard Cells, Progra##a%le 3rray Logic, !esign 3 roach' UNIT VII VHDL SYNTHESIS : )9!L Synthesis, Circuit !esign -lo., Circuit Synthesis, Si#ulation, Layout, !esign ca ture tools, !esign )eri"ication Tools, Test Princi les' UNIT VIII C&OS TESTING : CMOS Testing, Need "or testing, Test Princi les, !esign Strategies "or test, Chi le,el Test Techni:ues, Syste#-le,el Test Techni:ues, Layout !esign "or i# ro,ed Testa%ility' TE'TBOO(S ( ;' $ssentials o" )LSI circuits and syste#s <a#ran $shraghian, $shraghian !ougles and 3' Puc/nell, P9I, 0==> $dition' 0' Princi les o" CMOS )LSI !esign - 6este and $shraghian, Pearson $ducation, ;???' RE)ERENCES : ;' Chi !esign "or Su%#icron )LSI( CMOS Layout & Si#ulation, - @ohn P' 4ye#ura, Tho#son Learning' 0' Introduction to )LSI Circuits and Syste#s - @ohn 'P' 4ye#ura, @ohn6iley, 0==A' A' !igital Integrated Circuits - @ohn M' &a%aey, P9I, $$$, ;??B' C' Modern )LSI !esign - 6ayne 6ol", Pearson $ducation, Ard $dition, ;??B'

De*+rtme,t -. ECE Lect/re %0+, III Dear B'Tech II Se#ester (EC !!"#$ VLSI DESIGN UNIT I:INTRODUCTION S.N-. T-*1c c-2ere3 ; Introduction to IC Technology 0 MOS, PMOS, NMOS A CMOS & BiCMOS technologies C Oxidation, Lithogra hy > !i""usion, Ion i# lantation E Metallisation, $nca sulation B Pro%e testing, Integrated &esistors and Ca acitors UNIT II : BASIC ELECTRICAL %RO%ERTIES S.N-. T-*1c c-2ere3 ; Basic $lectrical Pro erties o" MOS and BiCMOS Circuits 0 Ids-)ds relationshi s MOS transistor threshold )oltage A g#, gds, "igure o" #erit *o, Pass transistor ull u to ull do.n ratio "or nMOS in,erter dri,en %y another C nMOS in,erter ull u to ull do.n ratio "or nMOS in,erter !ri,en through one > or #ore ass transistors E NMOS In,erter B 3lternati,e "or#s o" ull u s, F CMOS In,erter analysis and design ? Bi-CMOS In,erters, Latch u UNIT III: VLSI CIRCUIT DESIGN %ROCESSES S.N-. ; 0 A C > E T-*1c c-2ere3 )LSI !esign -lo. MOS Layers, Stic/ !iagra#s La#da %ased !esign &ules and Layout 0 1# CMOS !esign rules , ;'0 u# !ou%le Metal and Poly rules Transistors Layout !iagra#s "or NMOS and CMOS In,erters and 2ates, Sy#%olic !iagra#s-Translation to Mas/ -or# N-. O. C0+sses re4/1re3 =; =0 =; =; =A =; N-. O. C0+sses re4/1re3 =; =0 =0 =0 =0 =0 =0 N-. O. C0+sses re4/1re3 =0 =0 =0 =; =; =; =; =; =; Branch( $C$-;&0

UNIT IV:GATE LEVEL DESIGN S.N-. T-*1c c-2ere3 ; Basic circuit conce ts Introduction 0 Sheet &esistance and its conce t to MOS and in,erter A 3rea Ca acitance 4nits, So#e area ca acitance calculation C Calculations - 5 !elays, In,erter delays > !ri,ing large Ca aciti,e Loads

N-. O. C0+sses re4/1re3 =; =0 =; =0

E B F

6iring Ca acitances, -an-in and "an-out, Choice o" layers &ealiGation o" gates using nMOS and CMOS

=0 =; =; =0 N-. O. C0+sses re4/1re3 =; =A =0 =0 =0 =0 =0 N-. O. C0+sses re4/1re3 =0

UNIT V: Sc+01,5 O. &OS C1rc/1ts S.N-. T-*1c c-2ere3 ; Scaling #odels and scaling "actors 0 Scaling "actors "or de,ice ara#eters, Li#itations o" Scaling A Li#its due to su% threshold currents C Li#its on Logic le,els and su ly ,oltage due to noise > Li#its due to current density, so#e architectural issues E , Introduction to s.itch logic and gate logic B UNIT VI:SE&ICONDUCTOR INTEGRATED CIRCUIT DESIGN S.N-. T-*1c c-2ere3 ; Introduction to PL!s, P3Ls, PL3s 0 I# le#entation a roach in )LSI !esign A -ull Custo# !esign, Standard Cells C Se#i Custo# design > -P23s E CPL!s, UNIT VII: D151t+0 Des15, Us1,5 HDL S.N-. T-*1c c-2ere3 ; !igital syste# !esign Process, )LSI circuit !esign Process 0 9ard.are Si#ulation, 9ard .are synthesis A 9istory o" )9!L, )9!L re:uire#ents, Le,els o" 3%straction C $le#ents o" )9!L, Pac/ages > Li%raries and Binding, O%Hects and Classes E )aria%le assign#ents, Se:uential state#ents B 4sage o" Su% rogra#s, Co# arison o" )9!L and )erilog 9!L UNIT VIII: )9!L MO!$LLIN2 S.N-. T-*1c c-2ere3 ; Si#ulation, Logic Synthesis 0 Inside a logic SynthesiGer, Constraints A Technology Li%raries, )9!L and Logic Synthesis C Place and &oute, Post Layout Ti#ing Si#ulation -unctional 2ate Le,el )eri"ication, Static Ti#ing, MaHor Netlist > -or#ats "or design re resentation E )9!L Synthesis- Progra##ing 3 roach

=0 N-. O. C0+sses re4/1re3 =; =; =; =; =; =;

N-. O. C0+sses re4/1re3 =0 =0 =; =; =0