Lec - 23 Effect of Substrate Bias VB and Channel Bias VC

1
Professor N Cheung, U.C. Berkeley

Lecture 23 EE143 S06
( )
Si ox FB B G
V V V V V + + =
net bias across MOS
M
O
p-Si
V
V
G
C
inversion
electrons
depletion
region
V
B
n+ n+
Effect of Substrate Bias V
B
and Channel Bias V
C
2
( )
( )
s
d
a
OX
d a
FB B G
B C p Si
X qN
C
X qN
V V V
V V V
max
2
max
2
1
2
+ + =
+ =
M O Si
E
i
E
fs
q(V
C
-V
B
)
E
fn
p
q
p
q
s
d
a
Si
X qN
V
max
2
2
1
=
At the onset of strong inversion, where V
G
is defined
as the threshold voltage
3
At threshold: V
G
V
B
= V
FB
+V
ox
+V
Si
But V
Si
= 2|
p
| + (V
C
- V
B
) =>
x
dmax
is different from no-bias case
B
Si Si
d
qN
V
x
2
=
max
V
T
-V
B
= V
FB
+
2
s
qN
B
(2|
F
| + V
C
-V
B
)
C
ox
+ 2|
F
| + V
C
- V
B

V
ox
V
Si
4
Flat Band Voltage with Oxide charges
V
FB
is the Gate voltage required to create no charge in the Si
dx
x
x x
C C
Q
V
ox
x
ox
ox
ox ox
f
S M FB

0
) ( 1
x = 0 x = x
ox
M O
S
ox
(x)
Q
f
ox
(x) due to alkaline
contaminants or trapped charge
Q
f
due to broken bonds at
Si-SiO
2
interface
5
V
T
Tailoring with Ion Implantation
N
sub
Shallow implanted
dopant profile at Si-SiO
2
interface (approximated as
a delta function)
Acceptor implant gives positive shift (+ V
T
)
Donor implant gives negative shift - V
T
Algebraic sign of V
T
shift is independent of n or p substrate !
OX
i
T
C
Q
V =
Q
i
= q implant dose in Si
6
p-Si
implanted acceptors
Na
SiO
2
Doping Profile After Implantation
SiO
2
x
dmax
Q
Q
d
d
Q
n
p-Si
(due to implanted acceptors)
Charge Distribution for V
G
> V
T
* Valid if thickness of implanted dopants << x
dmax
The V
T
shift can be viewed as the extra gate voltage needed to
deplete the implanted dopants ~ Q
i
/C
ox
The delta-function approximation of implanted profile
7
Summary : Parameters Affecting V
T
6
7
n
+
N
a
V
B
5
1
2
4
3
Dopant implant near Si/SiO
2
interface
f OX
Q &
M
x
ox
V
C
Q
n
n
+
8
+ Q
f
or Q
ox
B threshold implant
As or P threshold implant
X
ox
increases
X
ox
increases
M
increases
M
decreases
|V
CB
| increases
|V
CB
| increases
9
Summary of MOS Threshold Voltage (NMOS, p-substrate)
Threshold voltage of MOS capacitor:
Threshold voltage of MOS transistor:
Note 1: At the onset of strong inversion, inversion charge is negligible
and is often ignored in the V
T
expression
Note 2: V
T
of a MOSFET is taken as the V
T
value at source ( i.e., V
C
=V
S
)
Note 3 : Q
i
= (q implant dose ) is the charge due to the ionized donors
or acceptors implanted at the Si surface. Q
i
is negative for acceptors
and is positive for donors
V
T
= V
FB
+
2
s
qN
B
(2|
F
|)
C
ox
+ 2|
F
| -
Q
i
C
ox

V
T
= V
FB
+
2
s
qN
B
(2|
F
| + V
C
-V
B
)
C
ox
+ 2|
F
| + V
C
-
Q
i
C
ox

10
Summary of MOS Threshold Voltage (PMOS, n-substrate)
Threshold voltage of MOS capacitor:
Threshold voltage of MOS transistor:
* Yes, + sign for V
C
term but V
C
(<0) is a negative bias for PMOS because the
inversion holes have to be negatively biased with respect to the n-substrate
to create a reverse biased pn junction.
V
T
= V
FB
-
2
s
qN
B
(2|
F
|)
C
ox
- 2|
F
| -
Q
i
C
ox

V
T
= V
FB
-
2
s
qN
B
(2|
F
| + V
C
-V
B
)
C
ox
- 2|
F
| + V
C
-
Q
i
C
ox

11
Negligible electron concentration
underneath Gate region;
Source-Drain is electrically open
High electron concentration
underneath Gate region;
Source-Drain is electrically connected
V
G
< V
threshold
V
G
> V
threshold
Metal -Oxide-Semiconductor Transistor [ n-channel]
12
MOSFET I-V Analysis
n
+
n
+
V
S
V
G
W
V
B=0
V
D
I
D
L
Q
n
N-MOSFET
In general, inversion charge Qn ( [V
G
-V
T
]) decreases from Source toward
Drain because channel potential V
C
increases.
V
T
increases
13
Let V
T
defined to be threshold voltage at Source
( )
|
.
|
\
|
=
=
+
2
V
V V C
) average ( V V C ) average ( Q
2
V
V ~ ) average ( V
DS
T G OX
T G OX n
DS
T
T
[ This is an approximation ]
I
D
= Wt (-q n v
drift
)
= W Q
n
v
drift
Inversion layer thickness
Inversion layer concentration
Approximate Analysis
Note: I
D
is constant for all positions
along channel
14
L
V
E v With
DS n
n drift

=
DS
DS
T G OX D
V
2
V
V V C
L
W
I
|
.
|
\
|
=
V
DS
I
D
Linear with V
DS
Quadratic with V
DS
15
V
D saturation
n
+
n
+
V
S=0
V
D
Q
n
=0 at the drain
Lateral E-field
Electrons moves
saturation velocity
V
Dsat
is defined to be the value of V
D
with Q
n
=0 at drain.
From Q
n
= C
ox
(V
G
-V
T
-V
D
), we get V
Dsat
=V
G
-V
T
16
17
V
D
I
D
18
DS
DS
T G OX
n
D
V
V
V V C
L
W
I
|
.
|
\
|
=
2
MOSFET I-V Characteristics Summary

For V
D
< V
Dsat
( )
2
2
T G OX
n
Dsat D
V V C
L
W
I I = =

For V
D
> V
Dsat
Note: V
Dsat
= V
G
- V
T
19
E
x
SiO2
inversion
layer
Mobility of inversion charge carriers
*Carrier will experience
additional scattering at the
Si/SiO2 interface
*Channel mobility is lower
than bulk mobility
* (effective) is extracted from MOSFET I-V characteristics
* Typically ~0.5 of (bulk)
20
Parameter Extraction from MOSFET I-V
(A) V
T
V
D
I
D
D
S
( )
.
0
2 2
1
2
'
'
mode saturation in is MOSFET
off pinch at is Drain
V V
V qN
C
V V
drain at V
V V V For
T
G
D p a s
OX
p D FB
T
T G D

<
+ +
+ + =
> =

21
( )
2
T D Dsat D
V V
L
W
k I I = =
V
D
V
T
D
I
L
kW
slope=
V
G
n
C
OX
22
Alternative way to extract V
T
Measure I
D
versus V
G
for a fixed small V
DS
(say <100mV)
The intercept of I
D
versus V
G
plot on V
G
-axis is V
T
.
( )
DS T G OX
n
DS
DS
T G OX
n
D
V V V C
L
W
V
2
V
V V C
L
W
I
|
.
|
\
|

=
V
T
V
G
I
D
23
V
D
I
D
V
B
(varies)
V
D
V
B
=0
V
B1
V
B2
V
T0
V
T1
V
T2
D
I
( ) ( )
OX
a s
p SB p
SB T SB T
C
qN
V
V with V V with V
2
2 2
0 0
=
(
(
+
=
(B) Body Coefficient

24
I
D
V
D
V
G2
V
G1
(C)
V
D
( )
D T G OX n
D
D
D
D
T G OX n D
V small for V V
L
W
C
V
I
V
V
V V C
L
W
I
=
|
.
|
\
|
=
2
I
D
V
G
slope
L
W
C
OX n
25
(D) Transconductance g
m
(a) For V
DS
<V
Dsat
(b) For V
DS
> V
Dsat
D
V fixed
G
D
m
V
I
g
DS OX n
G
D
DS
DS
T G OX
n
D
V
L
W
C
V
I
V
V
V V C
L
W
I
=
|
.
|
\
|
=
2
( )
( )
T G OX
n
G
D
T G OX
n
Dsat D
V V C
L
W
V
I
V V C
L
W
I I
=
= =
2
2
I
D
V
DS
V
G1
+V
G
V
G1
V
Dsat
[g
m
varies with V
DS
]
[g
msat
varies with V
G
]
26
I
D
V
D
V
Dsat
real
ideal
n
+
n
+
Q
n
( ) ( )
1
2
) ( 01 . 0 1 . 0 ~
1
2
+ =
volt to Typically
V V V
k
I
DS T G Dsat
(E) Channel Modulation Parameter

27
Short Channel Effect on V
T
V
T
ideal
analysis
L
depletion
charge
controlled
by gate.
n
+
n
+
V
G
p
depletion layer
L
28
n
+
n
+
V
S
=0 V
D
=0
W
o
x
W
o
X
j
+W
o
X
j
X
j
X
j
L
L
( ) | |
(
(
+ =
+ =
=
1
2
1 2
2
2 '
2 2
j
o
j
j o o j
X
W
X L
X W W X L
x L L
Note: W
o
is x
dmax
Same
electric
potential
because of
heavily
doped n+
29
f
X
W
L
X
Q
Q
W W
L L
N q
j
o
j
ideal
actual
o a
(
(
+ =
=

+
=
1
2
1 1
2
1
Area of gate charge distribution
Yau Model for short-channel effect.
30
Implantation at low energy
Small Dt.
Minimize channeling and
transient enhance diffusion
To make f 1
X
j
W
o
Increase N
a
L large
S/D S/D
L small
S/D
S/D
31
V
T
L
Large V
DS
V
DS
~ 0
Effect of V
DS
on V
T
Lowering
Large V
DS
Larger S/D depletion charge at the drain side
Smaller depletion region charge contributed by gate
V
T
starts to decrease at larger L
n
+
n
+
V
G
depletion layer
Depletion charge
contributed
by gate
32
parasitic
charge
which has to
be created
by gate bias
V
T
is larger than ideal analysis.
Fox Fox
W
Ideal Depletion charge
W
Narrow Width Effect (related to W)
33
V
T
W
V
T
L
Narrow Width Effect
Narrow Channel Effect
34
Small Geometry Effects Summary
W
L
Actual gate
control charge
Ideal
gate control
charge

Lec - 23 Effect of Substrate Bias VB and Channel Bias VC

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1

Professor N Cheung, U.C. Berkeley

MOSFET I-V Characteristics Summary

(B) Body Coefficient

(E) Channel Modulation Parameter

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