Lecture 010 ECE4430 Review I (12/29/01)

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LECTURE 010 ECE 4430 REVIEW I

(READING: GHLM - Chap. 1) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught in ECE 4430 2.) Insure that the students of ECE 6412 are adequately prepared Outline Models for Integrated-Circuit Active Devices Bipolar, MOS, and BiCMOS IC Technology Single-Transistor and Multiple-Transistor Amplifiers Transistor Current Sources and Active Loads

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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MODELS FOR INTEGRATED-CIRCUIT ACTIVE DEVICES PN Junctions - Step Junction Barrier potential NAND NAND kT NAND o = q ln ni2 = Vt ln ni2 = UT ln ni2 Depletion region widthsW1 = W2 = 2si(o-vD)ND qNA(NA+ND) 2si(o-vD)NA qND(NA+ND)

1 N
Cj

Depletion capacitancesiqNAND Cj = A 2(NA+ND)

1 o-vD =

Cj0 vD 1 - o
Fig. 010-01

Cj0 0
0 vD

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-3

PN-Junctions - Graded Junction Graded junction:

ND 0 -NA x
Fig. 010-02

Above expressions become: Depletion region widths 2si(o-vD)ND m W1 = 1 m qND(NA+ND) W 2si(o-vD)NA N m W2 = qND(NA+ND) Depletion capacitance siqNAND 1 Cj0 m Cj = A2(NA+ND) -v m = vD o D m 1 o where 0.33 m 0.5.
ECE 6412 - Analog Integrated Circuits and Systems II

3 2.5 2 Cj 1.5 Cj0 1 m=0.333 0.5 m=0.5 0 -10 -8 -6 -4 vD 0 -2 0 2

Fig. 010-03

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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Large Signal Model for the BJT in the Forward Active Region Large-signal model for a npn transistor:
iB B + FiB E v iB = Is exp BE F Vt Assumes vBE is a constant and iB is determined externally C vBE E + VBE(on) E B C FiB E
Fig.010-04

Large-signal model for a pnp transistor:

iB B + FiB E iB = - Is exp -vBE F Vt Assumes vBE is a constant and iB is determined externally C B FiB E
Fig.010-05

iB C VBE(on) + E

vBE E

Early Voltage: Modified large signal model becomes iC

vBE vCE = IS 1 + VA exp V t

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-5

The Ebers-Moll Equations The reciprocity condition allows us to write, FIEF = RICR = IS Substituting into a previous form of the Ebers-Moll equations gives, IS vBE vBC iC = IS exp Vt + 1 -R exp Vt + 1 and IS vBE vBC iE =-F exp Vt + 1 +IS exp Vt + 1 These equations are valid for all four regions of operation of the BJT. Also: Dependence of F as a function of collector current The temperature coefficient of F is, 1 F TCF = F +7000ppm/C

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-6

Simple Small Signal BJT Model Implementing the above relationships, ic = gmvi + govce, and vi = rib, into a schematic model gives,
C B B + vi E ib
r

ic gmvi
ro

C + vce E B

E Fig. 010-06

Note that the small signal model is the same for either a npn or a pnp BJT. Example: Find the small signal input resistance, Rin, the output resistance, Rout, and the voltage gain of the common emitter BJT if the BJT is unloaded (RL = ), vout/vin, the dc collector current is 1mA, the Early voltage is 100V, and = 100 at room temperature. IC 1mA o 1 gm = Vt = 26mV = 26 mhos or Siemans Rin = r = gm = 10026 = 2.6k VA 100V vout Rout = ro = IC = 1mA = 100k vin = -gm ro = - 26mS100k = -2600V/V
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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Complete Small Signal BJT Model

r B rb C B' r + v1 C gmv1 ro Ccs rc C

rex E E
Fig. 010-07

The capacitance, C, consists of the sum of Cje and Cb. C = Cje +Cb

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-8

Example 1 Derive the complete small signal equivalent circuit for a BJT at IC = 1mA, VCB = 3V, and VCS = 5V. The device parameters are Cje0 = 10fF, ne = 0.5, 0e = 0.9V, C0 = 10fF, nc = 0.3, 0c = 0.5V, Ccs0 = 20fF, ns = 0.3, 0s = 0.65V, o = 100, F = 10ps, VA = 20V, rb = 300, rc = 50, rex = 5, and r = 10oro. Solution Because Cje is difficult to determine and usually an insignificant part of C, let us approximate it as 2Cje0. Cje = 20fF C0 Ccs0 10fF 20fF C = V = and Ccs = V = 0.3 = 5.6fF 0.3 = 10.5fF 3 5 CB CS ne ns 1+ 1+ 1+ 1+ 0.5 0.65 0c 0s IC 1mA gm = Vt = 26mV = 38mA/V Cb = F gm = (10ps)(38mA/V) = 0.38pF C = Cb + Cje = 0.38pF + 0.02pF = 0.4pF o VA 20V r = gm = 10026 = 2.6k, ro = IC = 1mA = 20k and r = 10ro = 20M

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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Transition Frequency, fT fT is the frequency where the magnitude of the short-circuit, common-emitter current =1. Circuit and model:
io rb ii ii C r + v1 C gmv1 ro Ccs rc io

Fig.010-08

Assume that rc 0. As a result, ro and Ccs have no effect. r gm r Io (j ) o V11+r(C+C)s Ii and IogmV1 Ii(j) = (C+C)s = (C+C)s 1+gmr gm 1+ o gm I o ( j ) o Now, ( j ) = I i ( j ) = (C+C)j 1+ o gm At high frequencies, gm gm 1 gm (j) j (C+C) When | (j)| =1 then T = C+C or fT = 2 C+C
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-10

JFET Large Signal Model Large signal model:

G + vGS S
2 IDSS(1 -vGS ) Vp

Fig. 010-09

Incorporating the channel modulation effect: vGS 2 iD = IDSS 1 - Vp vDS vGS-Vp (1+vDS) , Signs for the JFET variables: Type of JFET p-channel n-channel Vp Positive Negative IDSS Negative Positive vGS Normally positive Normally negative
P.E. Allen - 2002

ECE 6412 - Analog Integrated Circuits and Systems II

Lecture 010 ECE4430 Review I (12/29/01)

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Frequency Independent JFET Small Signal Model Schematic:

D G S + vgs gmvgs id + vds G S D

ro

Fig.010-10

Parameters: V GS diD | 2IDSS VGS gm = dvGS Q = - Vp 1- Vp = gm0 1- V p where 2IDSS gm0 = - V p V GS diD | 1 2 ro = dvDS Q = IDSS1- Vp ID Typical values of IDSS and Vp for a p-channel JFET are -1mA and 2V, respectively. With = 0.02V-1 and ID = 1mA we get gm = 1mA/V or 1mS and ro = 50k.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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Frequency Dependent JFET Small Signal Model Complete small signal model:
D G S G Cgss + vgs S

Cgd Cgs gmvgs ro -

id vds

D + G

Fig.010-11

All capacitors are reverse biased depletion capacitors given as, Cgs0 Cgs = V (capacitance from source to top and bottom gates) GS1/3 1+ o Cgd0 Cgd = V (capacitance from drain to top and bottom gates) GD1/3 1+ o Cgss0 Cgss = V (capacitance from the gate (p-base) to substrate) GSS 1/2 1+ o gm 1 fT = 2 Cgs+Cgd+Cgss = 30MHz if gm = 1mA/V and Cgs+Cgd+Cgss = 5pF
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-13

Simple Large Signal MOSFET Model D N-channel reference convention: + Non-saturationiD WoCox vDS2 G B vDS (vGS - VT)vDS (1 + vDS) , 0 < vDS < vGS - VT iD = L + + 2 vGS vBS Saturation- 2 S Fig. 010-12 WoCox vDS(sat) iD = L (v - VT)vDS(sat) 2 (1 + vDS) GS WoCox = 2L (vGS - VT) 2 (1 + vDS), 0 < vGS - VT < vDS where: o = zero field mobility (cm2/voltsec) Cox = gate oxide capacitance per unit area (F/cm2) = channel-length modulation parameter (volts-1) VT = VT0 + 2|f| 2|f| + |vBS| VT0 = zero bias threshold voltage = bulk threshold parameter (volts-0.5) 2|f| = strong inversion surface potential (volts) For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert current.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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MOSFET Small-Signal Model Complete schematic model:

D D

id G B + vgs B + vbs rds

G S

G S

gmvgs

gmbsvbs

+D vds S
Fig. 010-13

where diD | diD | iD gm dvGS Q = (VGS-VT) = 2ID gds dvDS Q = 1 + vDS iD vGS i D vT D i gm D and gmbs = vBS Q = vGS vBS = - vTvBS = = gm Q Q 2 2|F| - VBS Simplified schematic model:
id D G S G S D G + vgs rds

gmvgs

+D vds S Fig. 4.2-2

Extremely important assumption:

ECE 6412 - Analog Integrated Circuits and Systems II

gm 10gmbs 100gds
P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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MOSFET Depletion Capacitors - CBS and CBD Model: Polysilicon gate CJAS CJSWPS H G CBS = MJ + MJSW, vBS FCPB vBS vBS C 1 1 D PB PB Source Drain and F CJAS VBS E CBS = 1+MJ 1 - (1+MJ)FC + MJ PB B A 1- FC SiO2 Bulk CJSWPS VBS Fig. 010-14 + 1+MJSW 1 - (1+MJSW)FC + MJSW PB , Drain bottom = ABCD 1 FC Drain sidewall = ABFE + BCGF + DCGH + ADHE CBS vBS> FCPB where AS = area of the source vBS FCPB PS = perimeter of the source vBS FCPB PB CJSW = zero bias, bulk source sidewall capacitance vBS MJSW = bulk-source sidewall grading coefficient FCPB Fig 010-15 For the bulk-drain depletion capacitance replace "S" by "D" in the above equations.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

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MOSFET Intrinsic Capacitors - CGD, CGS and CGB Cutoff Region: Cutoff CGB=C2+2C5=Cox(Weff)(Leff) +2CGBO(Leff) VB = 0 CGS = C1 Cox(LD)Weff) = CGSO(Weff) CGD = C3 Cox(LD)Weff) = CGDO(Weff) p+ Saturation Region: p- substrate CGB = 2C5 = CGBO(Leff) Saturated VB = 0 CGS = C1+(2/3)C2 = Cox(LD+0.67Leff)(Weff) = CGSO(Weff) + 0.67Cox(Weff)(Leff) p+ CGD = C3 Cox(LD)Weff) = CGDO(Weff) p- substrate Active Region: CGB = 2 C 5 = 2CGBO(Leff) Active VB = 0 CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff) = (CGSO + 0.5CoxLeff)Weff p+ CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff) p- substrate = (CGDO + 0.5CoxLeff)Weff
ECE 6412 - Analog Integrated Circuits and Systems II

CGS

VS = 0

n+

VS = 0 CGS

n+

VS = 0 CGS

n+

;;; ;;; ;;; ;;;

VG < VT
Polysilicon

VD > 0 CGD n+

CGB

VG >VT

Polysilicon

VD >VG -VT CGD n+

Inverted Region

VG >VT

Polysilicon

VD <VG -VT CGD n+

Inverted Region

Fig 010-16

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-17

Small-Signal Frequency Dependent Model The depletion capacitors are found by evaluating the large signal Cgd capacitors at the DC operating point. G + Cgs The charge storage capacitors are vgs gmvgs gmbsvbs constant for a specific region of Cgb S operation. vbs Cbs Gainbandwidth of the MOSFET: + Assume VSB = 0 and the MOSFET B is in saturation, gm 1 1 gm fT = 2 Cgs + Cgd 2 Cgs Recalling that 2 W Cgs 3 CoxWL and gm = oCox L (VGS-VT) gives 3 o fT = 4 L2 (VGS-VT)

id
rds

+ vds S

Cbd

Fig 010-17

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-18

Subthreshold MOSFET Model Weak inversion operation occurs when the applied gate voltage is below VT and pertains to when the surface of the substrate beneath the gate is weakly inverted.

Diffusion Current p-substrate/well

;;; ;;; yyy

VGS
n+
n-channel

n+

Fig. 010-18

Regions of operation according to the surface potential, S. S < F : Substrate not inverted F < S < 2F : Channel is weakly inverted (diffusion current) 2F < S : Strong inversion (drift current) Drift current versus diffusion current in a MOSFET:
log iD Diffusion Current 10-6 Drift Current

10-12

VT

V Fig. 010-19 GS
P.E. Allen - 2002

ECE 6412 - Analog Integrated Circuits and Systems II

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-19

Large-Signal Model for Subthreshold Model: W v /nV iD = Kx L e GS t(1 - e-vDS/Vt)(1 + vDS) where Kx is dependent on process parameters and the bulk-source voltage n 1.5 - 3 and iD kT VGS=VT Vt = q 1A If vDS > 0, then W v /nV VGS<VT iD = Kx L e GS t (1 + vDS) Small-signal model: vDS 0 iD | qID 0 1V gm = vGS Q = nkT Fig 010-20 iD | ID gds = vDS Q VA

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 010 ECE4430 Review I (12/29/01)

Page 010-20

SUMMARY Models - Large-signal - Small-signal Components - pn Junction - BJT - MOSFET Strong inversion Weak inversion - JFET Capacitors - Depletion - Parallel plate

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002