Lecture 180 Power Supply Rejection Ratio (2/12/04)

Page 180-1

LECTURE 180 POWER SUPPLY REJECTION RATIO

(READING: GHLM 434-439, AH 286-293) Objective The objective of this presentation is: 1.) Illustrate the calculation of PSRR 2.) Examine the PSRR of the two-stage, Miller compensated op amp Outline Definition of PSRR Calculation of PSRR for the two-stage op amp Conceptual reason for PSRR Summary

ECE 6412 - Analog Integrated Circuit Design - II Lecture 180 Power Supply Rejection Ratio (2/12/04)

P.E. Allen - 2002 Page 180-2

What is PSRR?
+

Vdd

Av(Vdd=0) PSRR = Add(Vin=0)

V2 Vin V1

VDD Vout Vss VSS

Fig.180-01

How do you calculate PSRR? You could calculate Av and Add and divide, however
Vdd V2 V2 V1
+

VDD Vout Vss VSS V1

Av(V1-V2) Vout AddVdd

Fig. 180-02

Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout Vout(1+Av) = AddVdd Vout Add Add 1 V = = (Good for frequencies up to GB) dd 1+Av Av PSRR+
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 180 Power Supply Rejection Ratio (2/12/04)

Page 180-3

Positive PSRR of the Two-Stage Op Amp

Vdd

M3

M4

Cc

M6
Vout

VDD
Vdd

1 gm3

I3 rds1 gm1V5

gm6(V1-Vdd) rds4 rds2 gm2V5 rds5 + V5 I3 + V1 V5 0

Cc + CI CII

rds6

M1

M2 M5

CI

CII

Vdd - I3 gm1Vout gm3

rds7 Vout -

M7 VSS

VBias

gm6(V1-Vdd) rds4
Vdd

gds1Vdd rds2

gm1Vout + V1 -

Cc CI CII + Vout
-

rds6

rds7

Fig. 180-03

The nodal equations are: (gds1 + gds4)Vdd = (gds2 + gds4 + sCc + sCI)V1 (gm1 + sCc)Vout (gm6 + gds6)Vdd = (gm6 sCc)V1 + (gds6 + gds7 + sCc + sCII)Vout Using the generic notation the nodal equations are: GIVdd = (GI + sCc + sCI)V1 (gmI + sCc)Vout (gmII + gds6)Vdd = (gmII sCc)V1 + (GII + sCc + sCII)Vout whereGI = gds1 + gds4 = gds2 + gds4, GII = gds6 + gds7, gmI = gm1 = gm2 and gmII = gm6
ECE 6412 - Analog Integrated Circuit Design - II Lecture 180 Power Supply Rejection Ratio (2/12/04) P.E. Allen - 2002 Page 180-4

Positive PSRR of the Two-Stage Op Amp - Continued Using Cramers rule to solve for the transfer function, Vout/Vdd, and inverting the transfer function gives the following result. Vdd s2[CcCI+CICII + CIICc]+ s[GI(Cc+CII) + GII(Cc+CI) + Cc(gmII gmI)] + GIGII+gmIgmII Vout = s[Cc(gmII+GI+gds6) + CI(gmII + gds6)] + GIgds6 We may solve for the approximate roots of numerator as sCc s(CcCI+CICII+CcCII) + 1 + 1 g C g g g Vdd mI mII c mI mII + PSRR = Vout GIgds6 sg C mII c + 1 G g I ds 6 where gmII > gmI and that all transconductances are larger than the channel conductances. s s sCc sCII + 1 + 1 + 1 + 1 g |p2| g GIIAvo GB g g Vdd mI mII mI mII + PSRR = V =Gg = gds6 sGIIAvo sgmIICc out I ds6 GIgds6 + 1 + 1 g GB ds6

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 180 Power Supply Rejection Ratio (2/12/04)

Page 180-5

Positive PSRR of the Two-Stage Op Amp - Continued

GIIAv0
gds6

|PSRR+(j)| dB

gds6GB GIIAv0

GB |p2|

Fig. 180-04

At approximately the dominant pole, the PSRR falls off with a -20dB/decade slope and degrades the higher frequency PSRR + of the two-stage op amp. Using the values of Example 6.3-1 we get: PSRR+(0) = 68.8dB, z1 = -5MHz, z2 = -15MHz and p1 = -906Hz

ECE 6412 - Analog Integrated Circuit Design - II Lecture 180 Power Supply Rejection Ratio (2/12/04)

P.E. Allen - 2002 Page 180-6

Concept of the PSRR+ for the Two-Stage Op Amp

Vdd Vout Vdd

M3

M4

Cc

M6
Vout

VDD

Cc
Vdd

Vout

0dB

1 RoutCc

M1

M2 M5

CI

CII

Rout

M7 VSS

Other sources of PSRR+ besides Cc

VBias

Fig. 180-05

1.) The M7 current sink causes VSG6 to act like a battery. 2.) Therefore, Vdd couples from the source to gate of M6. 3.) The path to the output is through any capacitance from gate to drain of M6. Conclusion: The Miller capacitor Cc couples the positive power supply ripple directly to the output. Must reduce or eliminate Cc.
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 180 Power Supply Rejection Ratio (2/12/04)

Page 180-7

Negative PSRR of the Two-Stage Op Amp withVBias Grounded

M3 M4

Cc

M6
Vout

VDD

Cc
M1 M2 M5 VBias VBias grounded

CI

CII gmIVout
RI CI

M7 V ss

gmIIV1

CII

RII

gm7Vss

+ Vout -

VSS
Fig. 180-06

Nodal equations for VBias grounded: 0 = (GI + sCc+sCI)V1 - (gmI+sCc)Vo gm7Vss = (gMII-sCc)V1 + (GII+sCc+sCII)Vo Solving for Vout/Vss and inverting gives Vss s2[CcCI+CICII+CIICc]+s[GI(Cc+CII)+GII(Cc+CI)+Cc(gmII gmI)]+GIGII+gmIgmII Vout = [s(Cc+CI)+GI]gm7

ECE 6412 - Analog Integrated Circuit Design - II Lecture 180 Power Supply Rejection Ratio (2/12/04)

P.E. Allen - 2002 Page 180-8

Negative PSRR of the Two-Stage Op Amp withVBias Grounded - Continued Again using techniques described previously, we may solve for the approximate roots as sCc s(CcCI+CICII+CcCII) + 1 + 1 g C g g g Vss mI mII c mI mII PSRR- = Vout G g s ( C + C ) I m7 c I GI + 1 This equation can be rewritten approximately as sCc sCII s s + 1 +1 + 1 + 1 GB | p | g g G A Vss gmIgmII mI mII 2 II v0 PSRR- = Vout GIgm7 = g g sC s c m 7 mI +1 G + 1 G GB I I Comments: PSRR- zeros = PSRR + zeros DC gain Second-stage gain, PSRR- pole (Second-stage gain) x (PSRR+ pole) Assuming the values of Ex. 6.3-1 gives a gain of 23.7 dB and a pole -147 kHz. The dc value of PSRR- is very poor for this case, however, this case can be avoided by correctly implementing VBias which we consider next.
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 180 Power Supply Rejection Ratio (2/12/04)

Page 180-9

Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS

M3 M4

Cc

M6
Vout

VDD

M1

M2 M5

CI

CII
Vss

Cc rds5 gmIVout
VSS

Cgd7

rds7 + Vout -

VBias VBias connected to VSS

M7 V ss

CI

RI

+ V1 gmIIV1 -

CII

rds6

Fig. 180-07

If the value of VBias is independent of Vss, then the model shown results. The nodal equations for this model are 0 = (GI + sCc + sCI)V1 - (gmI + sCc)Vout and (gds7 + sCgd7)Vss = (gmII - sCc)V1 + (GII + sCc + sCII + sCgd7)Vout Again, solving for Vout/Vss and inverting gives
Vss s2[CcCI+CICII+CIICc+CICgd7+CcCgd7]+s[GI(Cc+CII+Cgd7)+GII(Cc+CI)+Cc(gmIIgmI)]+GIGII+gmIgmII Vout = (sCgd7+gds7)(s(CI+Cc)+GI)

ECE 6412 - Analog Integrated Circuit Design - II Lecture 180 Power Supply Rejection Ratio (2/12/04)

P.E. Allen - 2002 Page 180-10

Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS - Continued Assuming that gmII > gmI and solving for the approximate roots of both the numerator and denominator gives sCc s(CcCI+CICII+CcCII) + 1 + 1 g C g g g Vss mI mII c mI mII PSRR- = Vout G g sC s ( C + C ) I ds7 gd 7 I c +1 + 1 g GI ds7 This equation can be rewritten as s s + 1 +1 |p | GB G A Vss 2 II v0 PSRR = V g sC out ds7 sCgd7 c gds7 +1 GI + 1 Comments: DC gain has been increased by the ratio of GII to gds7 Two poles instead of one, however the pole at -gds7/Cgd7 is large and can be ignored. Using the values of Ex. 6.3-1 and assume that Cds7 = 10fF, gives, PSRR-(0) = 76.7dB and Poles at -71.2kHz and -149MHz
P.E. Allen - 2002

ECE 6412 - Analog Integrated Circuit Design - II

Lecture 180 Power Supply Rejection Ratio (2/12/04)

Page 180-11

Frequency Response of the Negative PSRR of the Two-Stage Op Amp with VBias Connected to VSS
GIIAv0
gds7

GI Cc

;; ;; ;; ;; ;;
Invalid region of analysis GB |p2|

|PSRR-(j)| dB

Fig. 180-08

ECE 6412 - Analog Integrated Circuit Design - II Lecture 180 Power Supply Rejection Ratio (2/12/04)

P.E. Allen - 2002 Page 180-12

Approximate Model for Negative PSRR with VBias Connected to Ground

M3 M4

Cc

M6
Vout

VDD

M5 or M7 VBias

iss

M1

M2 M5

CI

CII

Vss VSS

VBias VBias grounded

M7 V ss VSS

Fig. 180-09

Path through the input stage is not important as long as the CMRR is high. Path through the output stage: vout issZout = gm7ZoutVss Vout 1 V = gm7Zout = gm7Rout sR C +1 ss out out

Vout Vss

20 to 40dB

0dB
ECE 6412 - Analog Integrated Circuit Design - II

1 RoutCout

Fig.180-10
P.E. Allen - 2002

Lecture 180 Power Supply Rejection Ratio (2/12/04)

Page 180-13

Approximate Model for Negative PSRR with VBias Connected to VSS

M3 M4

Cc

M6
Vout

VDD

rds7 CI rds7 Vss

VSS

vout Zout

M1

M2 M5

CII

Vss

What is Zout? Vt Zout = I t

VBias

M7 VBias connected to VSS

Path through Cgd7 is negligible

Fig. 180-11

gmIVt It = gmIIV1 = g GI+sCI+sCc GI+s(CI+Cc) Thus, Zout = gmIgMII

mII

Cc CII+Cgd7 CI
RI

It

gmIVout

+ V1 gmIIV1 -

rds6||rds7

+ Vout -

Vt

Fig.180-12

rds7 1+ Vss Zout s(Cc+CI) + GI+gmIgmIIrds7 -GI V = 1 = Pole at C +C s(Cc+CI) + GI out c I The two-stage op amp will never have good PSRR because of the Miller compensation.
ECE 6412 - Analog Integrated Circuit Design - II Lecture 180 Power Supply Rejection Ratio (2/12/04) P.E. Allen - 2002 Page 180-14

SUMMARY PSRR is a measure of the influence of power supply ripple on the op amp output voltage PSRR can be calculated by putting the op amp in the unity-gain configuration with the input shorted. The Miller compensation capacitor allows the power supply ripple at the output to be large The two-stage op amp will never have good PSRR unless some modifications are made.

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002