Lecture 400 Discrete-Time Comparators (4/8/02)

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LECTURE 400 DISCRETE-TIME COMPARATORS (LATCHES)

(READING: AH 475-483) Objective The objective of this presentation is: 1.) Illustrate discrete-time comparators 2.) Estimate the propagation delay time Outline Switched capacitor comparators Regenerative comparators (latches) Summary

ECE 6412 - Analog Integrated Circuit Design - II Lecture 400 Discrete-Time Comparators (4/8/02)

P.E. Allen - 2002 Page 400-2

Switched Capacitor Comparator

V1 V2 1 2 + C Cp VC + VOS 1
+

Vout A V2 + C

V1 - VOS + VOS + Cp VOS +

Vout

A switched capacitor comparator

Equivalent circuit when the 2 switches are closed

Fig. 8.5-1

1 Phase: The V1 input is sampled and the dc input offset voltage is autozeroed. VCp(1) = VOS VC(1) = V1 - VOS and 2 Phase: V C (V1-VOS)C VOSCp 2 Vout(2) =-A + AVOS C+C C+Cp + C+Cp p
C Cp C C = -A (V2-V1) C+Cp + VOSC+Cp + C+Cp + AVOS = -A(V2-V1) C+Cp A(V1-V2) if Cp is smaller than C. ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 400 Discrete-Time Comparators (4/8/02)

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Differential-In, Differential-Out Switched Capacitor Comparator

C
+ vin -

2 1 C 2 1

1 - +
+-

+ vout -

1
Fig. 8.5-2

Comments: Reduces the influence of charge injection Eliminates even harmonics

ECE 6412 - Analog Integrated Circuit Design - II Lecture 400 Discrete-Time Comparators (4/8/02)

P.E. Allen - 2002 Page 400-4

Regenerative Comparators Regenerative comparators use positive feedback to accomplish the comparison of two signals. Latches have a faster switching speed that the previous bistable comparators. NMOS and PMOS latch:
VDD I1 vo1 M1 I2 vo2 M2 vo1 I1 I2 M1 VDD M2 vo2

NMOS latch

PMOS latch

Fig. 8.5-3

How is the input applied to a latch? The inputs are initially applied to the outputs of the latch. Vo1 = initial input applied to vo1 Vo2 = initial input applied to vo2

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 400 Discrete-Time Comparators (4/8/02)

Page 400-5

Step Response of a Latch Circuit: Ri and Ci are the resistance and capacitance seen to ground from the ith transistor. Nodal equations:
1

VDD I1 vo1 M1 I2

VDD + + Vo1 + Vo2 Fig. 8.5-4

vo2 M2

C1

C2

Vo2 Vo1' gm1Vo2 R1 s -

Vo2' gm2Vo1 R2 s

V gm1Vo2+G1Vo1+sC Vo1- s = gm1Vo2+G1Vo1+sC1V o1-C1Vo1 = 0

o1
V o2 V gm2Vo1+G2Vo2+sC2 = gm2Vo1+G2Vo2+sC2V o2-C2Vo2 = 0 o 2 s Solving for Vo1 and Vo2 gives, R1C1 gm1R1 g m 1R 1 1 Vo1 = sR1C1+1 Vo1 - sR1C1+1 Vo2 = s1+1 Vo1 - s1+1 Vo2 2 R2C2 gm2R2 g m 2R 2 Vo2 = sR C +1 Vo2 - sR C +1 Vo1 = s +1 Vo2 - s +1 Vo1 2 2 2 2 2 2 Defining the output, Vo, and input, Vi, as Vo = Vo2-Vo1 and Vi = Vo2-Vo1

ECE 6412 - Analog Integrated Circuit Design - II Lecture 400 Discrete-Time Comparators (4/8/02)

P.E. Allen - 2002 Page 400-6

Step Response of the Latch - Continued Solving for Vo gives, gmR Vo = Vo2-Vo1 = s+1 Vi + s+1 Vo or Vi Vi 1-gmR Vi Vo = s+(1-gmR) = s = s+1 1-gmR + 1 where = 1-gmR Taking the inverse Laplace transform gives

vo(t) = Vi e-t/ = Vi e-t(1-gmR) / egmRt/Vi, if gmR >>1.

Define the latch time constant as 0.67WLCox C L gmR = gm = = 0.67Cox 2K(W/L)I if C Cgs. Vout(t) = et/L Vi
ECE 6412 - Analog Integrated Circuit Design - II

WL 3 2KI

P.E. Allen - 2002

Lecture 400 Discrete-Time Comparators (4/8/02)

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Step Response of a Latch - Continued Normalize the output voltage by (VOH-VOL) to get Vout(t) Vi t/L = e VOH-VOL VOH-VOL which is plotted as,
1

0.5 0.4
0.8 0.6 0.4 0.2 0 0 1

0.3

0.2 0.1 0.05

Vi VOH-VOL 0.03 0.01 0.005

Vout VOH-VOL

t L

5
Fig. 8.5-5

VOH- VOL The propagation delay time is tp = L ln 2Vi ECE 6412 - Analog Integrated Circuit Design - II Lecture 400 Discrete-Time Comparators (4/8/02) P.E. Allen - 2002 Page 400-8

Example 8.5-1 - Time domain characteristics of a latch. Find the time it takes from the time the latch is enabled until the output voltage, Vout, equals VOH-VOL if the W/L of the latch NMOS transistors is 10m/1m and the latch dc current is 10A when Vi = 0.1(VOH-VOL) and Vi = 0.01(VOH-VOL). Find the propagation time delay (Vout=0.5(VOH-VOL)) for the latch for each of these conditions. Solution The transconductance of the latch transistors is gm = 21101010 = 148S The output conductance is 0.4S which gives gmR of 59.2V/V. Since gmR is greater than 1, we can use the above results. Therefore the latch time constant is found as WL 3 (101)x10-18 L = 0.67Cox 2KI = 0.67(24x10-4) 2110x10-610x10-6 = 108ns If we assume that the propagation time delay is the time for the output to reach (VOHVOL), then for Vi = 0.01(VOH-VOL) that tp = 4.602L = 497ns and for Vi = 0.1(VOH-VOL) that tp = 2.306L = 249ns. If we assume that the propagation time delay is the time when the output is 0.5(VOHVOL), then using the above results or Fig. 8.5-5 we find for Vi = 0.01(VOH-VOL) that tp = 3.91L = 422ns and for Vi = 0.1(VOH-VOL) that tp = 1.61L = 174ns.
ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 400 Discrete-Time Comparators (4/8/02)

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Comparator using a Latch with a Built-In Threshold How does it operate? 1.) Devices in shaded region operate in the 1 M7 triode region. Latch M9 /Reset 2.) When the latch/reset goes high, the upper 1 M5 cross-coupled inverter-latch regenerates. The drain currents of M5 and M6 are steered to M3 vout+ obtain a final state determined by the mismatch R1 between the R1 and R2 resistances. M2 M1 vin+ W1 W2 1 + = K ( v ) + V VREFN L in T R1 L (VREF- - VT) and W W2 1 1 + V V ( v ) + ( V ) in T REF T L L R2 = KN 3.) The input voltage which causes R1 and R2 to be equal is given by vin(threshold) = (W2/W1)VREF W2/W1 = 1/4 generates a threshold of 0.25VREF. Performance 20Ms/s & 200W

VDD M8 1 M10 Latch /Reset 1 M6 M4 M2 VREF+

Fig. 8.5-6

vout-

R2 vin-

M1

T.B. Cho and P.R. Gray, A 10b, 20Msamples/s, 35mW pipeline A/D Converter, IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March 1995. ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 400 Discrete-Time Comparators (4/8/02)

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Simple, Low Power Latched Comparator

VDD 1 M9 1 M3 vin+ M1 M2 M5 vout+ voutM4 vinFig. 8.5-7

M7

M8 M10 M6

Dissipated 50W when clocked at 2MHz.

A. Coban, 1.5V, 1mW, 98-dB Delta-Sigma ADC, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250. ECE 6412 - Analog Integrated Circuit Design - II P.E. Allen - 2002

Lecture 400 Discrete-Time Comparators (4/8/02)

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Dynamic Latch Circuit:

VDD
Latch

M6

M8 VREF
vin

M3

M4 + vout
vout-

M7

M1 M5

M2

Latch

Fig. 8.5-8

Input offset voltage distribution:

Number of Samples
20 10 0 -15

= 5.65

Power dissipation/sampling rate = 4.3W/Ms/s

ECE 6412 - Analog Integrated Circuit Design - II Lecture 400 Discrete-Time Comparators (4/8/02)

;; ; ; ;; ; ; ;; ;;; ;;;
L = 1.2m (0.6m Process) -10 -5 0 5 10 Input offset voltage (mV)

15
Fig. 8.5-9

P.E. Allen - 2002 Page 400-12

SUMMARY Discrete-time comparators must work with clocks Switched capacitor comparators use op amps to transfer charge and autozero Regenerative comparators (latches) use positive feedback The propagation delay of the regenerative comparator is slow at the beginning and speeds up rapidly as time increases The highest speed comparators will use a combination of open-loop comparators and latches

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002