ECE 445 Computer Organization and Design Spring 2013 Project#5 MIPS Datapath for R, I, and J-type Instructions

Electrical and Computer Engineering George Mason University April 1, 2013

Objective

The objective of this lab is to modify the existing MIPS datapath for R- and I-type instructions (see Figure 3) to add J-type instructions (specied in Table 1). The top-level block diagram for the datapath is illustrated in Figure 1.
MemWrite MemRead

32 clock Reset 32 Dout 32 Address Write data Read data 32

Datapath

Data Memory

Figure 1: Block diagram of Datapath

Figure 2: Block diagram of Data memory

Required Reading
Before beginning work on the lab, read Chapter 4 in the text book and sections 1 and 2 of appendix D, which is included on the CD that accompanied the text book. Review the MIPS reference card (green card) that was included with the text book.

Required Knowledge
How to write VHDL code using the behavioral and structural models. How to use packages in VHDL. How to use the Xilinx ISE 14.2 toolkit to write VHDL code, generate schematic symbols for HDL models, create schematic based designs and test benches.
4 32 [31:26] 6

PCADD
32

Control
RegWrite

read address
32

[25:21] 32 [20:16] [15:11]

5 5 5 32

ALU
Zero Overflow
32

rs rt

rs

PC

Instruction
[31:0]

Register
rt

32

Instruction Memory
clock
[5:0]

rd File Write data

ALUout
32 4

clock

ALUCntl

ALU Control

Figure 3: Datapath for R-type Instructions

Design

The objective of this lab is to modify the existing MIPS datapath for R- and I-type instruction to add J-type instructions. In order to achieve this, you need to design/modify components that are required for the J-type instructions. A working design for the ALU, Register-File, Instruction Memory and Data memory are provided. You may use the provided ALU unit or may use your own design, assuming that it was designed properly and tested thoroughly. The logical shift operations are performed by ALU unit. These operations are not specied in the initial ALU design. You need to add these operations to the existing ALU operations. Consider ALU performs shift left logical (sll ) and shift right logical (srl ) when ALUCntl=1101 and ALUCntl=1110 respectively. The provided Data memory, Register-File and Instruction memory units provided must be used as they are pre-loaded with initial values and the test program respectively. The Data memory unit provided[Figure 2] has two control signals MemRead and MemWrite. The MemRead should be set to 1 while reading from memory and MemWrite set to 1 while writing to memory other wise set to 0. The Data memory has a delay of 200ps either to read or write. 2

Draw the datapath with all the additional components and control signals on paper and get it veried by the TA. This will help to avoid problems in the later stage. Table 1: R and I-type instructions to implement
No 1 2 3 4 5 6 7 9 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Operation Add Add unsigned Subract Subract unsigned And Or Xor Nor Set less than Set less than unsigned Jump Register Shift left logical Shift right logical Add Immediate Add Immediate Unsigned And Immediate Or Immediate Set Less Than Immediate Set Less Than Immediate Unsigned Load Word Store Word Branch On Equal Branch On Not Equal Jump Jump And Link Format R R R R R R R R R R R R R I I I I I I I I I I J J Mnemonic add addu sub subu and or xor nor slt sltu jr sll srl addi addiu andi ori slti sltiu lw sw beq bne j jal Opcodehex 00 00 00 00 00 00 00 00 00 00 00 00 00 08 09 0C 0D 0A 0B 23 2B 04 05 02 03 Functionhex 20 21 22 23 24 25 26 27 2A 2B 08 00 02 xx xx xx xx xx xx xx xx xx xx xx xx

Table 2: Initial contents of Data Memory

Memory loacation Memory loacation Memory loacation Memory loacation Initial value Initial value Memory loacation 20 21 22 23 Memory location Initial value Initial value Initial value Initial value 00 00 00 06

0 1 2 3

00 00 00 00

4 5 6 7

00 00 00 03

8 9 10 11

00 00 00 08

12 13 14 15

00 00 00 09

16 17 18 19

00 00 00 01

Testing

The instruction memory contains the test program which is shown in [ Program5]. Build a test bench with a clock period of 20ns and run the simulation for 1 clock cycles with reset=1 and subsequent clock cycles with reset=0. The initial contents of Data memory are shown in Table [2] The test program in instruction memory Label Instruction Mainp: add $t4, $zero, addi $s0, $zero, addi $s1, $zero, lw $t0, 0($t4) addi $t4, $t4, Comp: lw $t1, 0($t4) slt $t2, $t1, bne $t2, $zero, Inct: addi $t4, $t4, beq $s0, $s1, addi $s0, $s0, J Comp Swap: add $t0, $t1, J Inct Store: sw $t0, ($t4) $zero 1 5 4 $t0 Swap 4 Store 1 $zero

Deliverables

Once completed, submit a ZIPPED le with the following syntax jtypedatapath First Last.zip where First Last is your rst and last name. For instance, the le should be named like this jtypedatapath John Doe.zip. . The zipped le should include the following les : 1. Project folder(folder containing all the les of your design including Xilinx regenerated les) 2. Comments.txt (if you have any). Submit the zipped le through the blackboard. Failure to submit complete project folder would reduce your grade signicantly.  Points will be taken o if you do not follow the above instructions