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A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology

This paper appears in: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International Date of Conference: 17-21 Feb. 2013 Author(s): Liu, Tz-Yi Sandisk, Milpitas, CA, USA Yan, Tian Hong; Scheuerlein, Roy; Chen, Yingchang; Lee, Jeffrey KoonYee; Balakrishnan, Gopinath; Yee, Gordon; Zhang, Henry; Yap, Alex; Ouyang, Jingwen; Sasaki, Takahiko; Addepalli, Sravanti; Al-Shamma, Ali; Chen, Chin-Yu; Gupta, Mayank; Hilton, Greg; Joshi, Saurabh; Kathuria, Achal; Lai, Vincent; Masiwal, Deep; Matsumoto, Masahide; Nigam, Anurag ; Pai, Anil; Pakhale, Jayesh; Siau, Chang Hua; Wu, Xiaoxia; Yin, Ronald; Peng, Liping; Kang, Jang Yong; Huynh, Sharon; Wang, Huijuan; Nagel, Nicolas; Tanaka, Yoichiro; Higashitani, Masaaki; Minvielle, Tim; Gorla, Chandu; Tsukamoto, Takayuki; Yamaguchi, Takeshi; Okajima, Mutsumi; Okamura, Takayuki; Takase, Satoru; Hara, Takahiko; Inoue, Hirofumi; Fasoli, Luca; Mofidi, Mehrdad; Shrivastava, Ritu; Quader, Khandker Page(s): 210 - 211 Product Type: Conference Publications

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ABSTRACT
ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have been used for several megabit test-chips and memory macros [13]. This paper presents a MeOx-based 32Gb ReRAM test chip developed in 24nm technology.

Additional Details
Conference Location : San Francisco, CA, USA ISSN : 0193-6530 Print ISBN: 978-1-4673-4515-6 Digital Object Identifier : 10.1109/ISSCC.2013.6487703

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